Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06G—ANALOGUE COMPUTERS
  • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
  • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
  • G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division
  • G06G7/163—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division using a variable impedance controlled by one of the input signals, variable amplification or transfer function

Definitions

• the invention relates to a multiplier circuit according to the preamble of claim 1.
• analog multiplication circuits are often required which have two analog inputs, form a product of both input signals and pass this product on to an analog output.
• Multiplier circuits are known and frequently used components.
• an emitter-coupled transistor pair can be specified as the simplest implementation for an analog multiplier circuit (see Gray, Meyer, "Analysis and Design Of Analog Integrated Circuits", Second Edition, John Wiley and son, 1984, on pages 590 to 593).
• the base connections bwz form in FIG. 10.6.
• the common emitter connection of the transistor pair has the two analog inputs and the collector connections the outputs of an analog multiplier.
• Analog multiplier circuits are used, for example, as a phase detector or in frequency doubler circuits.
• the multiplier circuit is intended to supply an output voltage which is proportional to the phase difference at the input, and this up to the highest possible frequency.
• the output voltage of the phase detector should be in the middle of the modulation range. This corresponds to a phase error of zero.
• the modulation range of the phase detector should be 180 °.
• a frequency doubler also contains a 90 * phase shifter in order to be able to achieve effective frequency doubling in the case of large-signal operation with sinusoidal input signals of the same phase.
• a Gilbert cell is often used as a multiplication circuit for phase detection or frequency doubling.
• the construction and use of such a Gilbert cell can be found in the publication by Gray, Meyer already mentioned: "Analysis and Design of Analog Integrated Circuits" on pages 593 to 605.
• the Gilbert cell provides an XOR operation as a logic function. The suitability of this circuit at frequencies close to the cutoff frequency of the bipolar transistors is deteriorated by the different transit times in the lower and upper circuit levels of the Gilbert cell.
• the total transit time difference between the input signals of the upper and lower circuit level results in addition to an additional throughput time due to the differential level in the lower circuit level ⁇ ne also a further cycle time due to the different number of level shift levels.
• this asymmetry leads to a phase error that increases rapidly with increasing frequency and greatly reduces the symmetry of the output characteristic curve around the central position at 90 * .
• the same transit time effect leads to a " change in the amplitude relationships of the counter clock outputs.
• the invention is based on the object of specifying a multiplier circuit which, when used as a phase detector even for high frequencies, has a symmetrical characteristic with a 90 * phase difference of the input signals and which, when used in a frequency doubler circuit, does not " change " the amplitude relationships at the push-pull outputs leads at high frequencies.
• the cut-off frequency of the multiplication circuit according to the invention is no longer limited by the phase error but by the switching time of the bipolar transistors alone, and is therefore higher than in conventional multiplication circuits.
• the output signal with a 90 'phase difference is exactly in the middle of the modulation range.
• FIG. 1 An exemplary embodiment of the invention is shown in the drawing in FIG. The drawings show in detail:
• FIG. 2 shows a multiplier circuit according to the invention
• FIG. 3 shows an example of use of the multiplication circuit according to the invention in a PLL circuit
• FIG. 4 the detector characteristic curve of the PLL circuit according to FIG. 3.
• Figure 1 shows an analog multiplier cell according to the prior art, which is also referred to as a Gilbert cell. Their structure and mode of operation can be found in the aforementioned publication by Gray, Meyer: “Analysis and Design Of Analog Integrated Circuits” Figures 10.9, 10.10 and 10.16 on pages 593 to 605. Depending on the size ratio of the threshold voltage of the input transistors to the input signals, three areas can be defined for the practical application of this multiplier cell.
• the amplitude of one of the input signals is larger compared to that the temperature voltage of the input transistors
• both input signals are higher in amplitude than that of the temperature voltage of the input transistors.
• the latter application area is particularly suitable for the detection of phase differences between two amplitude-limited input signals, as is often required in PLL circuits.
• the multiplier cell according to FIG. 1 can be divided into a lower and downstream upper circuit level, first input terminals E1, E2 being assigned to the upper circuit level and second input terminals E3 being assigned to the lower circuit level.
• the multiplier cell is connected between a first voltage terminal AK1, which is connected to a negative pole of the supply voltage, and a second voltage terminal AK2, which is connected to ground.
• a first and second resistance element W1, W2 is arranged between the first voltage terminal AK1 and the first and second output terminal AI, A2 of the multiplier cell.
• the lower circuit level contains a first emitter-coupled transistor pair with a first and second bipolar transistor T1, T2, and the upper circuit level contains two emitter-coupled transistor pairs that have a third, fourth and fifth and sixth bipolar transistor T3, T4, T5 and T6 exhibit.
• a base connection of the first and a base connection of the second bipolar transistor T1 and T2 respectively form the two first input terminals E3, E4 of the multiplier cell.
• An emitter connection of the first and an emitter connection of the second bipolar transistor are jointly connected to the first voltage terminal AK1 via a current source IQ.
• Bipolar transistor T1 is connected to the emitter connection of the third and at the same time to the emitter connection of the fourth bipolar transistor T3, T4, while a collector connection of the second bipolar transistor T2 is connected to an emitter connection of the fifth and together with an emitter connection of the sixth
• Bipolar transistor T5, T6 is connected.
• a base connection of the third and a base connection of the sixth bipolar transistor T3, T6 together form the first E1 of the two second input terminals E1, E2 and a base connection of the fourth together
• a base connection of the fifth bipolar transistor T4, T5 form the second E2 of the two second input terminals E1, E2.
• the collector connection of the third and the collector connection of the fifth bipolar transistor T3, T5 together represent the first AI of the two output terminals AI, A2 and are connected to the second voltage terminal AK2 via the first resistance element W1, while the collector connection of the fourth and the Kol ⁇
• the detector connection of the sixth bipolar transistor T4, T6 forms the second A2 of the two output terminals AI, A2 and is also to be connected to the second voltage terminal AK2 via the second resistance element W2.
• the Gilbert cell is a modification of an emitter-coupled transistor pair. It allows a four-quadrant multiplication, so that both input signals can lie in the positive as well as in the negative value range.
• all bipolar transistors used are npn bipolar transistors. From the DC current analyzes of the Gilbert cell on pages 493 to 495 of the publication by Gray, Meyer "Analysis And Design Of Analog Integrated Circuits" it follows that the voltage at the output terminals of the Gilbert cell is a product of the hyperbolic tangent functions of the input signals . For small input signals, the hyperbolic tangent function can be replaced by its argument in a first approximation.
• this circuit deteriorates at frequencies near the cutoff frequency of the bipolar transistors due to the different transit times in the lower and upper circuit level.
• this asymmetry leads to a phase Sen error, which increases rapidly with increasing frequency and greatly reduces the symmetry of the output characteristic around the center position at 90 * .
• This same runtime effect also leads to a " change in the amplitude ratios of the push-pull outputs when used in a frequency doubler circuit.
• each signal S1 and S2 therefore passes through both the slower and the faster transmission path and the output signal at the output terminals AI 1 and A2 1 is the sum of these two components.
• the cutoff frequency of this new arrangement is no longer limited by the phase error, but rather by the switching time of the bipolar transistors alone, and thus higher than in the multiplication circuit according to the prior art from FIG. 1. For all frequencies below this cutoff frequency If the output signal is at a 90 * phase difference between the output signals, it is exactly in the middle of the modulation range.
• the multiplier circuit according to the invention contains two multiplier cells, each of which is to be constructed individually as a Gilbert cell, as in FIG. 1.
• the outputs of both multiplier cells are connected in parallel and the inputs of the same are connected to the inputs of the multiplier circuit via level shifter stages LSI ', ... LS4 1 or LSI 1 ' ... LS4- » .
• an ohmic resistor Wl 'and W2- connects the outputs AI 1 and A2 1 with the second voltage terminal AK2.
• Each multiplication cell contains a current source, as well as a lower and downstream upper circuit level.
• the lower GmbHs ⁇ planar, each having an emitter-coupled pair of transistors (Tl 1, T2 1 / Tl ', T2 ") are the inputs E3', E4 ', and E3', E4 'assigned to, while in the upper circuit plane, respectively two emitter-coupled transistor pairs (T3-, T4 '/ T5', T6- or T3 ", T4" / T5 ", T6") can be controlled via the inputs El ', E2 ⁇ or El ", E2".
• the output AI 1 of the multiplier circuit is formed according to FIG.
• Output A2 1 is to be established by a common connection between the collector outputs of T4 1 , T6 1 from MZ1 and the collector outputs of T4 ′′ and T6 ′′ from MZ2.
• output AI 1 is via the resistance element Wl 1 and the output A2 'to be connected to the second voltage terminal AK2 via the resistance element W2 1 .
• the level shifters at the inputs of the two multiplication cells MZl, MZ2 can be divided into two groups: a first group, which is structured in one step and to which LSI 1 , LS2 1 , LSI "and LS2" belong, and a second group of three ⁇ level shifters, to which LS3 1 , LS4 ', LS3 "and LS4" are counted.
• a single stage is built up from a bipolar npn transistor with a resistance element or a current source. The input of such a level shifter is the base connection, while the collector connection is connected to the second voltage terminal AK2 and the emitter connection is connected to the first voltage terminal AKl via the resistance element or the current source.
• the emitter connection also forms the output of a one-stage level shifter. If the level shifter has multiple stages, the individual stages are connected in series and the output of the preceding level shifter stage is switched to the input of the subsequent level shifter stage. From FIG. 2 it can further be seen that the three-stage level shifter LS3 1 on input E3 1 , the three-stage level shifter LS4 1 on input E4 ', the three-stage level shifter LS3 "on input E3" and the likewise three-stage level shifter LS4 " input E4 "is switched.
• the single-stage level shifters LSI 1 and LS2- with the input El 1 or E2 'and LSI ", LS2" are each to be connected to the input El "or E2".
• the inputs of the multiplier circuit ME1 ... ME4 are via the associated level shifters with the inputs of the two Connect multiplier cells as follows.
• the connection ME1 is connected on the one hand via the level shifter LS3 1 to E3 1 and via the level shifter LSI "with El” and the connection ME2 via the level shifter LS4 'with E4' and via the level shifter LS2 "with E2".
• the connection ME3 is via the level shifter
• the second voltage terminal AK2 must be connected to the reference potential and the first voltage terminal AK1 to a negative pole of the supply voltage (for example - 5 volts).
• All bipolar transistors used are also designed as npn bipolar transistors, as in FIG.
• FIG. 3 shows a circuit for clock recovery with the aid of a phase-locked loop PLL in which the multiplier circuit according to the invention can advantageously be installed.
• a phase-locked loop also called a phase-locked loop, represents a particularly important application of control technology in communications technology.
• the PLL circuit ensures that an output signal UA is set so that it matches the frequency of an input signal UE, in this way precisely that a phase shift between the two signals remains constant.
• the PLL circuit has the task of recovering a stable clock signal UA from the data stream in order to clock the decision-maker flip-flop FF.
• NRZ signals non-turn to zero
• the phase position of the clock signal relative to the input data stream UE 1 is set by an adjustable phase shifter PS 1 .
• the input current UE 1 is therefore switched both at the input of the decision-maker flip-flop FF and directly via the preprocessing stage VV as the input signal UE to the PLL circuit, and the clock input of the decision-maker flip-flop FF is via the adjustable phase shifter PS 1 connected to the output signal UA of the PLL circuit.
• the regenerated data stream UA 'can then be taken as an output signal from the decision-maker flip-flop FF.
• the decision flip-flop FF works as a sample and hold circuit and stores the signal value that was present at the sampling time for an entire clock period.
• the PLL circuit PLL itself contains a symmetrical phase detector SPD, a loop filter SF, a voltage-controlled frequency oscillator VCO, a phase shifter PS and a symmetrical frequency doubler SFV.
• the symmetrical phase detector SPD forms a control deviation signal from the input signal UE and the output signal of the symmetrical frequency doubler SFV, which is applied via a loop filter SF to the voltage-controlled frequency oscillator VCO.
• the loop filter SF has a low-pass function, dampens the higher-frequency signal component of the control deviation signal and forms a DC voltage signal for regulating the voltage-controlled frequency oscillator VCO.
• the output of the symmetrical frequency doubler SFV is switched to the first input of the symmetrical phase detector SPD and the input signal UE to the second input of the same, and the output of the symmetrical phase detector is connected to the voltage-controlled frequency oscillator VCO via the loop filter SF.
• the output of the voltage-controlled frequency oscillator VCO is connected on the one hand directly and on the other hand via a phase shifter PS to the symmetrical frequency doubler circuit SFV.
• the phase shifter PS is necessary here for frequency doubling, since the symmetrical frequency doubler circuit SFV requires two input signals shifted by 90 * in large signal mode.
• the voltage-controlled oscillator is usually the element that limits the operating frequency of the entire loop.
• the voltage-controlled oscillator is inserted into the PLL circuit together with a symmetrical frequency doubler implemented by the multiplier circuit according to the invention, this speed limit can be overcome.
• the speed gain that can be achieved can then be used for the overall loop if, in contrast to the standard circuit, the symmetrical phase detector is also constructed with the aid of the multiplier circuit according to the invention and this speed requirement is thereby satisfied.
• the usable frequency range of a frequency doubler circuit constructed with the symmetrical multiplier circuit according to the invention can be increased compared to standard circuits.
• the frequency-dependent phase error of a simple multiplication detector according to the prior art no longer has to be compensated in the phase detector PS '. Only the running time of the preprocessing stage VV can be compensated for by the phase shifter PS 1 .
• FIG. 4 shows the detector characteristic curve, according to which the two input signals for the synchronous phase detector (in this case UA and UE) are regulated to a fixed phase distance of 90 * .
• a PLL circuit acts like a feedback loop and has the effect that the system deviation signal U is always minimized. If, instead of the multiplier circuit according to the invention, standard components were used in the PLL circuit in FIG. 3 in the synchronous phase detector SPD and the synchronous frequency doubler SFV, the sinusoidal detector characteristic curve would shift to the right for increasing frequencies and thus a phase error in the phase relationship generate the two signals UA, UE (by arrow direction for high frequencies indicated in Figure 4). As already stated, this would have to be compensated for by an adjustable phase shifter PS 1 .

Landscapes

• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Mathematical Physics (AREA)
• Theoretical Computer Science (AREA)
• Power Engineering (AREA)
• Software Systems (AREA)
• Computer Hardware Design (AREA)
• General Physics & Mathematics (AREA)
• Manipulation Of Pulses (AREA)
• Amplitude Modulation (AREA)

Applications Claiming Priority (2)

Publications (1)

Family

ID=6381766

Family Applications (1)

Country Status (5)

Families Citing this family (26)

Family Cites Families (3)

• 1989
  • 1989-05-31 DE DE3917714A patent/DE3917714A1/de not_active Withdrawn
• 1990
  • 1990-05-17 US US07/773,556 patent/US5151624A/en not_active Expired - Fee Related
  • 1990-05-17 EP EP90906893A patent/EP0474653A1/de not_active Withdrawn
  • 1990-05-17 WO PCT/DE1990/000371 patent/WO1990015397A1/de not_active Application Discontinuation
  • 1990-05-17 JP JP2507316A patent/JPH04506124A/ja active Pending

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events