Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L7/00—Arrangements for synchronising receiver with transmitter
  • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
  • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
  • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Definitions

• Circuit arrangement for generating synchronization signals when transmitting data.
• the invention relates to a circuit arrangement for generating synchronization signals during data transmission, according to the preamble of patent claim 1.
• a clock control is provided in the reception unit, which generates reception clocks from the received data signals and feeds them to a sampling stage. There, the receive clocks scan the data signals and recover the transmitted data from the data signals. For this purpose, the data signals should be sampled in their middle as far as possible.
• Such a receiving unit is shown in the form of a block diagram in FIG. 1 and its mode of operation is explained in more detail together with the time diagrams shown in FIG. 2, in which the time t in the abscissa direction and the instantaneous values of signals are shown in the ordinate direction.
• the binary-coded data signals D are supplied on the one hand to a pulse generator IG and on the other hand to the sampling stage AB, which recovers the transmitted data from the data signals D using reception clocks ET and makes them available as reception data ED for further processing poses.
• the receive clocks ET are generated in a clock control TS.
• the pulse generator IG generates synchronization signals SY. These synchronization signals SY are applied to the clock control TS and this adjusts the phase position of the receive clocks ET in such a way that the receive clocks ET always sample the data signals D in the middle thereof.
• the pulse generator IG At respectively corresponding times on the falling edges of the data signals D, the pulse generator IG generates the synchronization signals SY, by means of which the phase position of the reception clocks ET generated in the clock control TS is set such that the data signals D are in the middle thereof at the times t1 to t5 can be scanned by the rising edges of the receive clocks ET in order to recover the received data ED.
• the data signals can be subject to distortion. If of these data signals the
• Receive clocks are derived, the data signals can not be sampled safely, since the receive clocks are only synchronized by the edges of the data signals.
• the invention is therefore based on the object of specifying a circuit arrangement for generating synchronization signals, the use of which means that the data signals are also scanned with great certainty if they are subject to distortion.
• a special feature of the invention is that the distortions of the data signals are taken into account when generating the synchronization signals.
• the invention enables data signals with distortions of up to 50% of their pulse duration to be reliably detected Most and yet the circuit arrangement requires little effort and it can be manufactured as an integrated circuit. Advantageous developments of the invention are specified in the subclaims.
• FIG. 1 shows a block diagram of a receiving unit for transmitted data signals
• FIG. 3 shows a block diagram of a circuit arrangement according to the invention
• a clock generator TG generates clock pulses T1 and T2.
• the clock pulses T2 have half the repetition frequency of the clock pulses T1 and are generated from them by frequency division, for example by means of a flip-flop.
• the clock pulses T1 and T2 are supplied to the various components of the circuit arrangement, only the feed to a switching stage SS is shown.
• the repetition frequency of the clock pulses T1 is, for example, equal to 128 times the nominal repetition frequency of the data signals D. Further details of the circuit arrangement are explained in more detail below in connection with the time diagrams shown in FIG. 4, in which the time t in the abscissa direction and the instantaneous values of signals in the ordinate direction , and counter readings ZS of a counter Z are shown analogously.
• the data signals D are present at a synchronization stage SYS, in which they are synchronized with the clock pulses T1.
• a data signal D assumes the binary value 1
• the synchronization stage SYS generates a load pulse L, which sets the counter Z to an initial value AN, for example 64, by means of initial value signals ANS and resets a release level FR, and via the synchronization stage SYN a blocking signal Sl for the switching stage SS picks up.
• the synchronization stage SYS generates a switchover signal D3 for the clock pulses T1 and T2, a data signal which switches the clock pulses T2 through the switching stage SS as clock pulses T3 to the counter Z.
• the clock pulses T3 advance the counter Z and count it down to a final value EN, for example 0. As soon as it reaches a counter reading 32 which corresponds to half the initial value AN, it emits a signal Z1 which sets the release level FR and for generation of an enable signal FR1, since then the data signal D has a pulse duration of at least 50% of the target duration in the undistorted case. Otherwise, the output of the clock pulses T3 would be blocked immediately by the blocking signal S1 and the counting would thus be ended.
• the synchronization stage SYS also outputs an enable signal FR2 to the output stage AS and this generates a synchronization signal SY which is used to set the phase position of the receive clocks ET.
• Synchronization signal SY generates the blocking signal S1, with which the switching stage SS is blocked and the counting is ended.
• the data signal D is sampled again in the middle by a reception clock ET. With the next change in the binary value of the data signal D, a similar process is repeated and the data signal D is sampled again at the time t3.
• the synchronization stage SYS outputs the data signal D4 as a changeover signal to the switching stage SS and this now also switches the clock pulses T1 the higher repetition frequency to the counter Z so that it reaches its final value EN faster and the synchronization signal SY is emitted earlier at the time t5.
• the phase position of the reception clocks ET is thus reset, so that the corresponding data signal D is sampled closer to its center at time t6.
• the counter Z can also be counted up instead of downwards.
• the initial value signal ANS always sets it to the initial value AN of 0 and the clock pulses T3 then count it up to a final value EN of 64.
• the data signals D are shortened by up to 50% due to distortion.
• the corresponding undistorted data signals D are shown in dashed lines.
• the synchronization signals SY are not always due to the distorted data signals D on their edges, but by the
• Counter Z is generated, which is counted from the predetermined initial value AN to the predetermined final value EN.
• the synchronization signal SY is generated, with which the reception clock ET is synchronized.
• the clock pulses T2 with a low repetition frequency are switched over to the clock pulses T1 with a high repetition frequency, so that the end value EN is reached more quickly and the reception clock ET can be synchronized in advance.
• a switch is made to the clock pulses T1 with the higher sequence frequency, and at times t5 and t9 the leading synchronization signals SY are generated.
• FIG. 5 of the circuit arrangement is explained in more detail below together with the time diagrams shown in FIG. 6, in which the time t in the abscissa direction and the instantaneous values of signals and the counter readings ZS of the counter Z are shown analogously in the ordinate direction.
• a clock generator TG is provided, which clock pulses T1, T and T2 generated, the clock pulses T1 having twice the repetition frequency as the clock pulses T2 and the clock pulses corresponding to the inverted clock pulses T1.
• the repetition frequency of the clock pulses T1 is, for example, equal to 128 times the repetition frequency of the undistorted data signals D.
• the circuit arrangement is reset by a reset signal R, which is applied to the components in the manner shown and resets flip-flops F1 to F3, F8 and F9.
• the data signals D are present at an input of an antivalence element A, by means of which the polarity of the data signals D can optionally be inverted.
• the antivalence element A outputs the data signal D1 at its output, which is present at the clock input of the flip-flop F1, at whose data input the binary value 1 is present.
• the binary value of the data signal D changes, for example from 0 to 1, provided that the flip-flop F9 is reset, the binary value of the data signal D1 at the output of the antivalence element A also changes from 0 to 1 and the flip-flop F1 is set.
• the output of the flip-flop F1 is connected to the data input of the flip-flop F2, at the clock input of which the clock pulses T1 are present and that together with the flip-flop F3 for the synchronization of the data signals D and D1 with the clock pulses T1 and 1 serves.
• the flip-flop F2 is set with the next clock pulse T1.
• the non-inverting output of flip-flop F2 is connected to an input of a NOR gate N2, to the data input of flip-flop F3, to the reset input of a flip-flop F4 and to a first input of a NAND gate N1, the second input of which is connected to the inverting output of the flip-flop F3 is connected. Since the flip-flop F3 is reset, the NAND gate N1 emits the load pulse L with the binary value 0, which loads the value 64 into the counter Z by means of initial value signals ANS with the binary values 1000000 and resets a flip-flop F5 via an inverter I.
• the enable signal FR1 at the inverting output of the flip-flop F5 enables an AND gate U2.
• the inverting output of the flip-flop F2 is connected to the data input of the flip-flop F4, at whose clock input the clock pulses T1 are present.
• the flip-flop F4 is already reset, so that the state of the flip-flop F4 does not change with the next clock pulse T1.
• the clock pulses are at the clock input of the flip-flop F3 on and with the next clock pulse this flip-flop F3 is also set.
• the charging pulse L thus again assumes the binary value 1 and it sets a further flip-flop F6, which releases two NAND elements N3 and N4 by means of a blocking signal S1. These are each connected to an output of the flip-flop F3 and the data signals D3 and D4 are present on them on the one hand as changeover signals and on the other hand the clock pulses T1 and T2. Since the flip-flop F3 is set, inverted clock pulses T2 are emitted via the NAND gate N3 and supplied to the counter Z as clock pulses T3 via an AND gate U1. This begins by counting down from its initial value 64 to an end value.
• the counter Z As soon as the counter Z has reached its counter reading 32 at the time t2, it emits a corresponding counter signal Z1 which is present at the data input of the flip-flop F5 and sets it.
• the enable signal FR1 at the inverting output of this flip-flop F5 now blocks the AND gate U2.
• the flip-flop F5 essentially forms the release stage FR and the circuit arrangement is only released when the data are each longer than 50% of their desired duration. Otherwise, the AND gate U2 would generate a reset signal that blocks the switching stage SS.
• data signal D again assumes binary value 0 and thus data signal D1 also assumes binary value 0.
• the flip-flop F1 is reset.
• the flip-flop F2 is also reset with the next clock pulse T1.
• the next clock pulse sets flip-flop F3 back.
• the next clock pulse T1 sets the flip-flop F4 and this in turn holds the flip-flop F5 in the set state by a set signal SE.
• the counter Z As soon as the counter Z has reached its final value 0, it outputs an overflow signal with the binary value 0 at its output at time t4 as the final value signal ES, which sets a flip-flop F7 via the NOR gate N2.
• the flip-flop F7 outputs the synchronization signal SY at its output.
• the synchronization signal SY resets the flip-flop F6 via an OR gate 02, which in turn blocks the NAND gates N3 and N4 by means of the blocking signal S1 and prevents a further counting of the counter Z.
• the flip-flop F7 is reset again and the synchronization signal SY is ended again.
• the synchronization signal SY adjusts the phase of the reception clock ET and at time t5 the data signal D is sampled again. A similar process as after time t1 is repeated after time t6.
• the NOR gate N2 does not emit a set signal to the flip-flop F7, since the flip-flop F2 is set and thereby the NOR gate N2 is blocked.
• the counter Z If the counter Z has reached a counter reading before changing the binary value of the data signal D from 1 to 0, which is assigned to a distortion of the data signal D by more than 100%, it outputs a counter signal Z2 to a flip-flop F8 via an AND gate U3 this sets and at its exit Issues blocking signal S2.
• This blocking signal S2 also resets the flip-flop F6 and prevents the delivery of further clock pulses T1 or T2 to the counter Z. It also resets the flip-flop F1 and sets a flip-flop F9, the output of which is connected to the antivalence element A.
• the antivalence element A now inverts the data signal D and with the next change in the binary value of the data signal D at the time t6, a similar process is repeated as between the times t1 and t2.

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• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Synchronisation In Digital Transmission Systems (AREA)

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• 1989
  • 1989-04-27 DE DE3914006A patent/DE3914006C1/de not_active Expired - Fee Related
• 1990
  • 1990-04-20 WO PCT/DE1990/000295 patent/WO1990013191A1/de not_active Application Discontinuation
  • 1990-04-20 US US07/721,612 patent/US5235596A/en not_active Expired - Fee Related
  • 1990-04-20 EP EP90906119A patent/EP0470092A1/de not_active Withdrawn

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