EP0467607B1 - Halbleiterspeicheranordnung - Google Patents

Halbleiterspeicheranordnung Download PDF

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Publication number
EP0467607B1
EP0467607B1 EP91306365A EP91306365A EP0467607B1 EP 0467607 B1 EP0467607 B1 EP 0467607B1 EP 91306365 A EP91306365 A EP 91306365A EP 91306365 A EP91306365 A EP 91306365A EP 0467607 B1 EP0467607 B1 EP 0467607B1
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EP
European Patent Office
Prior art keywords
memory cell
memory
voltage
signal
memory cells
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Expired - Lifetime
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EP91306365A
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English (en)
French (fr)
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EP0467607A3 (en
EP0467607A2 (de
Inventor
Takaki c/o NEC CORPORATION Kohno
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NEC Corp
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NEC Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • G11C17/123—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices comprising cells having several storage transistors connected in series

Definitions

  • This invention relates to a semiconductor memory device, and more particularly to, a mask programmable read only memory in which electric field stress applied to memory cells is relieved.
  • a conventional mask programmable read only memory comprises a plurality of memory cell matrices each having a plurality of memory cell blocks.
  • Each of the memory cell blocks comprises a plurality of memory cells serially connected, and the serially connected memory cells are connected through a block selection transistor to a digit line on one side thereof, and are connected to ground on the other side thereof.
  • the memory cell unit is composed, for instance, in such a manner that N channel MOS enhancement transistor having a threshold voltage of 1.0 V and N channel MOS depletion transistor having a threshold voltage of -5.0 V are assigned to store binary signals in accordance with the difference of the threshold voltages which is resulted from the injection of impurity, for instance, P into the transistors.
  • one of the memory cell matrices is selected by a Y-decoder circuit, while one of the memory cell blocks is selected in the selected memory cell matrix by a block decoder circuit.
  • the selected memory cell block one of the memory cells is accessed in accordance with the application of low level signal (O V) by an X-decoder circuit, while non-accessed memory cells are applied with high level signal (5 V).
  • O V low level signal
  • 5 V high level signal
  • a potential of the digit line which is thereby connected through the turned-on memory cells including the accessed memory cell to ground is lowered, for instance, from 1.2 V to 1.1 V.
  • This potential change is amplified in a sense amp circuit to provide information read from the accessed memory cell.
  • the accessed memory cell is the enhancement transistor, it is not turned on under the application of low level signal. Therefore, the potential change does not occur.
  • information stored in the memory cell unit is read upon the access of a predetermined one of the memory cells by applying a low level signal thereto, while a high level signal is applied to the non-accessed memory cells of the selected block, and to the remaining memory cells of the selected memory cell matrix and the non-selected memory cell matrices.
  • EP-A-0 297 540 discloses a semiconductor memory device as indicated in the preamble of claim 1. It comprises of a plurality of selection transistors, each being connected at one end to a column line and each having a gate connected to a common row line, and a plurality of groups of cell transistors, each group being connected in series between the other end of a respective one of said selection transistors and a reference potential and whose control gates are connected to row lines, each group of cell transistors being connected to common lines.
  • a semiconductor memory device comprises a memory cell unit comprising a plurality of memory cell groups each of said memory cell groups comprising a digit line and a plurality of memory cell blocks, each of said memory cell blocks comprising a predetermined number of serially connected memory cells which are connected to a predetermined number of word lines, respectively, and serially connected between said digit line and a fixed potential, each of said predetermined number of memory cells including a transistor for storing information according to first and second threshold voltages, said first threshold voltage being higher than said second threshold voltage;
  • the conventional mask programmable read only memory comprises an address buffer circuit 101 for temporally storing an address signal of n bits (a 1 , a 2 , ... a n ), assuming that n is 7 hereinafter, a chip enable signal buffer circuit 102 for temporally storing a chip enable signal Ce, a selection signal generating circuit 103 for generating a selection signal Sj, assuming that j is 1 to 4 hereinafter, by receiving the two bits a 1 and a 2 of the address signal and the chip enable signal Ce, an X-decoder circuit 104 for generating a word line signal Wjk, assumping that k is 1 to 4 hereinafter, by receiving the two bits a 3 and a 4 of the address signal and the selection signal Sj, a block decoder circuit 105 for selecting one memory cell block (to be explained in Fig.
  • a Y-decoder circuit 106 for controlling the selection of one memory cell matrix (to be explained in Fig. 2) by receiving the two bits a 6 and a 7 of the address signal, a memory cell unit 107 having memory cell matrices 107a, 107b, 107c and 107d (to be explained in Fig. 2), a Y-selector 108 for selecting one of the memory cell matrices 107a, 107b, 107c and 107d, and a sense amp circuit 109 for amplifying a signal read from an accessed memory cell.
  • the memory cell unit 107 comprises the memory cell matrices 107a, 107b, 107c and 107d, each of which comprises the two memory cell blocks as shown in the block of the memory cell matrix 10 7a.
  • memory cells M 1 , M 2 , M 3 and M 4 each consisting of a transistor selected dependently on storing binary states from an N-MOS enhancement transistor having a threshold voltage of 1.0 V and an N-MOS depletion transistor having a threshold voltage of -5.0 V, are connected serially to be positioned between ground and a block selection transistor Q B1 of an N-MOS enhancement transistor having a threshold voltage of 1.0 V.
  • the block selection transistor Q B1 is connected commonly to a digit line D 1 and to a Y-selection transistor Q Y1 of an N-MOS enhancement transistor having a threshold voltage of 1.0 V.
  • the memory cells M 1 , M 2 , M 3 and M 4 are connected at gates to the word lines W 11 , W 12 , W 13 and W 14 each connected to the X-decoder circuit 104, and the block and Y-selection transistors Q B1 and Q Y1 are connected at gates to the block and Y-decoder circuits 105 and 106, correspondingly.
  • serially connected memory cells M 5 , M 6 , M 7 and M 8 are positioned between a block selection transistor Q B2 connected to the digit line D 1 and ground, wherein type and threshold voltage of the transistors are the same as those of the first one of the memory cell blocks.
  • the selection signal generating circuit 103 comprises inverters 31 and 32 for inverting the two bits a 1 , and a 2 of the address signal, inverters 33 and 34 for inverting output signals of the inverters 31 and 32, NAND circuits 39 to 42, respectively, for receiving the output signals of the inverters 31 and 32, the output signal of the inverter 31 and an output signal of the inverter 34, an output signal of the inverter 33 and the output signal of the inverter 32, and the chip enable signal Ce and the output signals of the inverters 33 and 34, inverters 35 to 38, respectively, connected to the NAND circuits 39 to 42 to provide the selection signals S 1 to S 4 which are supplied to the X-decoder circuit 104.
  • the X-decoder circuit 104 comprises a NAND circuit 21 for receiving the two bits a 3 and a 4 of the address signal and the selection signal Sj, and inverters 22 and 23 for receiving an output signal of the NAND circuits 21 and supplying output signals, respectively, to a P-MOS transistor 24 connected to a power supply Vcc and an N-MOS transistor 25 connected to ground, wherein the word line signal Wjk is supplied from a common node of source to drain path of the P-and N-MOS transistors 24 and 25.
  • the address signal a 1 , a 2 , ?? a 7 having the two bits a 1 and a 2 of a high level is supplied to the address buffer circuit 101, and the chip enable signal Ce of a low level is supplied to the chip enable buffer circuit 102, so that the selection signal Sj of a low level is generated in the selection signal generating circuit 103 to be supplied to the X-decoder circuit 104, in which the word line signal Wjk of a high level is generated to be supplied to all of the memory cells in the memory cell matrices 107a, 107b, 107c and 107d of the memory cell unit 107 regardless of the address signal bits a 3 and a 4 .
  • the stand-by mode is set, as shown in Fig. 5.
  • the chip enable signal Ce becomes high
  • one of the selection signals S 1 , S 2 , S 3 and S 4 becomes high in the selection signal generating circuit 103 dependently on contents of the address signal bits a 1 and a 2 , as shown in Fig. 7.
  • the selection signal S 1 is high due to the two bits a 1 and a 2 of a low level
  • the selection signals S 2 to S 4 are low
  • the word line signals W 11 , W 12 , W 13 and W 14 are determined in the X-decoder circuit 104 by contents of the two bits a 3 and a 4 supplied to the NAND circuit 21 along with the selection signal S 1 , as shown in Fig. 6.
  • the word line signal W 11 is low, because the N-MOS transistor 25 is turned on, while the P-MOS transistor 24 is turned off.
  • the word line signals W 12 , W 13 and W 14 are high, as shown in Fig. 7.
  • the address signal bit a 5 of a high level is decoded in the block decoder circuit 105, so that the block selection transistor Q Y1 is turned on to select the first one of the memory cell blocks in the memory cell matrix 107a which is selected in accordance with the turning-on of the Y-selection transistor Q Y1 by the address signal bits a 6 and a 7 supplied to the Y-decoder circuit 106.
  • the first memory cell M 1 ; M 5 of each of the memory cell blocks in the memory cell matrix 107 a is applied with a low level signal, while all of the remaining memory cells of the memory cell matrix 107a and the memory cells of the memory cell matrices 107b, 107c and 107d are applied with a high level, as shown in Fig. 7.
  • the accessed memory cell M 1 is an N-MOS enhancement transistor, it is not turned on, so that the digit line D 1 is not changed regarding a potential (for instance, 1.2 V to be maintained).
  • the accessed memory cell M 1 is an N-MOS depletion transistor, it is turned on, so that the digit line D 1 is changed regarding the potential (for instance, lowering from 1.2 V to 1.1 V).
  • This change is transmitted to the sense amp circuit 109, in which it is amplified to be supplied to an output buffer circuit (not shown).
  • an output buffer circuit not shown
  • FIG. 8 an X-decoder circuit included in the mask programmable read only memory of the first preferred embodiment is shown, while other circuits are not shown, because the same circuits as used in the conventional mask programmable read only memory as shown in Figs. 1 to 4 are adopted in the first preferred embodiment.
  • the X-decoder circuit 104 comprises a first NAND circuit 11 for receiving two bits a 3 and a 4 of an address signal of, for instance, seven bits a 1 , a 2 , dividing a 7 and generating a first NAND signal, a second NAND circuit 12 for receiving a selection signal Sj from a selection signal generating circuit (Fig.
  • a third NAND circuit 13 for receiving the selection signal Sj from the selection signal generating circuit and the first NAND signal from the first NAND circuit 11 and generating a third NAND signal
  • a P-MOS transistor 14 for generating a word line signal Wjk of a high level in accordance with the turning-on by receiving the second NAND signal
  • an N-MOS transistor 15 for generating the word line signal Wjk of a low level in accordance with the turning-on by receiving the third NAND signal.
  • the selection signals S 1 to S 4 are all low at the time of stand-by mode, as shown in Fig. 9.
  • the word line signal Wjk is low, as shown in Fig. 9, because the P-MOS transistor 14 is turned off, while the N-MOS transistor 15 is turned on, regardless of contents of the address signal bits a 3 and a 4 supplied to the first NAND circuit 11.
  • the active mode is set to read information from an accessed memory cell of the memory cell unit.
  • a memory cell M 1 will be accessed.
  • the two bits a 1 and a 2 of the address signal are low, so that the selection signal S 1 becomes high in the selection signal generating circuit, while the selection signals S 2 to S 4 becomes low, as shown in Fig. 11.
  • the memory cell matrix 107a (Fig. 2) including the memory cell M 1 is selected, and the memory cell matrices 107b, 107c and 107d are not selected.
  • the address signal bits a 3 and a 4 of a high level are supplied to the first NAND circuit 11, as shown in Fig. 10, so that the first NAND signal of a low level is supplied to the second and third NAND circuits 12 and 13.
  • the selection signal S 1 of a high level is supplied to the third NAND circuit 13, so that the P-MOS transistor 14 is not turned on, while the N-MOS transistor 15 is turned on to provide the word line signal W 11 of a low level for the memory cell M 1 .
  • all word line signals are low in the memory cell matrices 107b, 107c and 107d of the memory cell unit 107 which are not selected in accordance with the selection signals S 2 to S 4 of a low level, regardless of contents of the bits a 3 and a 4.
  • the first memory cell M1;M5 of each memory cell block in the memory cell matrix 107a is applied with a low level signal
  • the remaining memory cells M2-M4; M6-M8 in the memory cell blocks of said memory cell matrix 107a are applied with a high level signal
  • all of the memory cells M1-M4; M5-M8 in all of the memory cell blocks in the memory cell matrices 107b, 107c, 107d are applied with said low level signal as shown in Fig. 11.
  • all of the word lines are set to be low at the time of stand-by mode, and the word lines connected to the memory cells of the memory cell matrices which are not selected are all set to be low at the time of active mode. Consequently, electric field stress applied to memory cells is relieved to enhance the reliability of the mask programmable read only memory.
  • FIG. 12 an X-decoder circuit included in a mask programmable read only memory of the second preferred embodiment according to the invention is shown, wherein like parts are indicated by like reference numerals as used in Fig. 8.
  • the X-decoder circuit comprises a voltage control circuit 16 connected to a common node of source to drain path of the P- and N-MOS transistors 14 and 15 to supply a word line signal Wjk to word lines connected to memory cells, in addition to the structure as shown in Fig. 8.

Claims (3)

  1. Halbleiterspeichereinrichtung, die aufweist:
    eine Speicherzelleneinheit (107), die eine Vielzahl von Speicherzellengruppen (107a - 107d) aufweist, wobei jede der Speicherzellengruppen eine Digitleitung und eine Vielzahl von Speicherzellenblöcken (M1 - M4, M5 - M8) aufweist, wobei jeder der Speicherzellenblöcke eine vorbestimmte Anzahl von in Reihe verbundenen Speicherzellen (M1 - M4) aufweist, die mit einer vorbestimmten Anzahl von Wortleitungen (W11 - W14) verbunden sind und in Reihe zwischen der Digitleitung und einem festen Potential verbunden sind, wobei jede der vorbestimmten Anzahl von Speicherzellen einen Transistor zum Speichern von Information entsprechend ersten und zweiten Schwellenspannungen einschließt, wobei die erste Schwellenspannung höher ist als die zweite Schwellenspannung;
    erste Mittel (108) zum Auswählen einer Speicherzellengruppe (107a) von der Vielzahl von Speicherzellengruppen entsprechend einem Adreßsignal;
    zweite Mittel (105) zum Auswählen eines Speicherzellenblocks aus der Vielzahl von Speicherzellenblöcken in der einen Speicherzellengruppe entsprechend dem Adreßsignal; und
    dritte Mittel (104) zum Auswählen einer Speicherzelle (M1) aus den in Reihe verbundenen Speicherzellen in dem einem Speicherzellenblock entsprechend dem Adreßsignal; wobei:
    die dritten Mittel eine erste Spannung an die eine Speicherzelle (M1) und eine zweite Spannung an die in Reihe verbundenen Speicherzellen (M2 - M4) mit Ausnahme dieser einen Speicherzelle in dem einen Speicherzellenblock (ERSTER SPEICHERZELLENBLOCK) einer ausgewählten Speicherzellengruppe (107a) anlegen, wobei die erste Spannung niedrigen ist als die erste Schwellenspannung und höher ist als die zweite Schwellenspannung, und wobei die zweite Spannung höher ist als die erste Schwellenspannung, dadurch gekennzeichnet, daß entsprechende Speicherzellen in jedem der Speicherzellenblöcke (M1 - M4, M5 - M8) innerhalb einer einzelnen Speicherzellengruppe (107a) mit denselben Wortleitungen (W11 - W14) verbunden sind, wobei jede Speicherzellengruppe (107a, 107b, 107c, 107d) mit unterschiedlichen Wortleitungen verbunden sind, daß die dritten Mittel die erste Spannung an eine Speicherzelle (M5) und die zweite Spannung an die in Reihe verbundenen Speicherzellen (M6 - M8) mit Ausnahme der einen Speicherzelle (M5) in dem Speicherzellenblock in jedem der übrigen Speicherzellenblöcken (ZWEITER SPEICHERZELLENBLOCK) der ausgewählten Speicherzellengruppe (107a) anlegen, und daß die dritten Mittel die erste Spannung an die Speicherzellen der Speicherzellenblöcke der nicht ausgewählten Speicherzellengruppen (107b,..., 107d) anlegen.
  2. Halbleiterspeichereinrichtung nach Anspruch 1, bei der
    die dritten Mittel (104) in gleicher Anzahl wie die Wortleitungen vorgesehen sind, wobei jedes der dritten Mittel erste und zweite Transistoren (15, 14) aufweist, die abwechselnd entsprechend dem Adreßsignal und einem Chip-Freigabesignal ein- und ausgeschaltet werden, wobei die ersten und zweiten Transistoren die ersten und zweiten Spannungen liefern.
  3. Halbleiterspeichereinrichtung nach Anspruch 1 oder 2, bei der
    jedes der dritten Mittel weiter eine Spannungssteuerschaltung (16) zum Steuern der zweiten Spannung aufweist, damit diese in einem vorgegebenen Ausmaß niedriger ist als eine Leistungsversorgungsspannung (Vcc).
EP91306365A 1990-07-16 1991-07-15 Halbleiterspeicheranordnung Expired - Lifetime EP0467607B1 (de)

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Application Number Priority Date Filing Date Title
JP18842890A JP2586187B2 (ja) 1990-07-16 1990-07-16 半導体記憶装置
JP188428/90 1990-07-16

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EP0467607A2 EP0467607A2 (de) 1992-01-22
EP0467607A3 EP0467607A3 (en) 1993-04-07
EP0467607B1 true EP0467607B1 (de) 1997-04-09

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EP (1) EP0467607B1 (de)
JP (1) JP2586187B2 (de)
DE (1) DE69125535T2 (de)

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US7005350B2 (en) * 2002-12-31 2006-02-28 Matrix Semiconductor, Inc. Method for fabricating programmable memory array structures incorporating series-connected transistor strings
US7233522B2 (en) * 2002-12-31 2007-06-19 Sandisk 3D Llc NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same
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US6822903B2 (en) * 2003-03-31 2004-11-23 Matrix Semiconductor, Inc. Apparatus and method for disturb-free programming of passive element memory cells
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US20050128807A1 (en) * 2003-12-05 2005-06-16 En-Hsing Chen Nand memory array incorporating multiple series selection devices and method for operation of same
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EP0467607A3 (en) 1993-04-07
EP0467607A2 (de) 1992-01-22
JP2586187B2 (ja) 1997-02-26
US5301144A (en) 1994-04-05
JPH0474397A (ja) 1992-03-09
DE69125535D1 (de) 1997-05-15
DE69125535T2 (de) 1997-07-17

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