EP0435701B1 - Display control method and apparatus for ferroelectric liquid crystal panel - Google Patents

Display control method and apparatus for ferroelectric liquid crystal panel Download PDF

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Publication number
EP0435701B1
EP0435701B1 EP90314433A EP90314433A EP0435701B1 EP 0435701 B1 EP0435701 B1 EP 0435701B1 EP 90314433 A EP90314433 A EP 90314433A EP 90314433 A EP90314433 A EP 90314433A EP 0435701 B1 EP0435701 B1 EP 0435701B1
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Prior art keywords
data
signal
display
electrodes
memory
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EP90314433A
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German (de)
English (en)
French (fr)
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EP0435701A2 (en
EP0435701A3 (en
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Takaji Numao
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Sharp Corp
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Sharp Corp
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G09G3/3629—Control of matrices with row and column drivers using a passive matrix using liquid crystals having memory effects, e.g. ferroelectric liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/04—Partial updating of the display screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms

Definitions

  • the present invention relates to a display control method and apparatus for a ferroelectric liquid crystal panel (hereinafter abbreviated also as FLCD).
  • FLCD ferroelectric liquid crystal panel
  • Fig. 1 is a block diagram schematically showing a typical conventional configuration of a display system using an FLCD 1.
  • a signal necessary for the image display is digitized, and the digital signal outputted to a CRT (cathode ray tube) 3 displaying images from a personal computer 2 is used.
  • the digital signal outputted from the personal computer 2 is transformed in a separate control circuit 4, and by the transformation signal the image is displayed on the FLCD 1.
  • Fig. 2 is a cross-sectional view showing a schematic configuration of the FLCD 1.
  • a signal electrode S consisting of indium tin oxide (hereinafter abbreviated as ITO) being arranged plurally in parallel on the surface of one glass substrate 5a, and covered by a transparent insulating film 6a consisting of SiO2 thereon.
  • a scanning electrode L consisting of ITO is arranged plurally in parallel in a direction orthogonal to the signal electrode S, and covered by an insulating film 6b consisting of SiO2 thereon.
  • orientation films 7a, 7b consisting of polyvinyl alcohol and treated by rubbing processing are formed respectively.
  • the two glass substrates 5a, 5b are bonded together with a sealing agent 8 partially leaving an injection port, which is sealed by the sealing agent 8 after a ferroelectric liquid crystal 9 is introduced into a space between the orientation films 7a, 7b by vacuum injection therethrough.
  • the two glass substrates 5a, 5b thus bonded together are clamped between two polarizing plates 10a, 10b arranged such that their respective polarizing axes intersect orthogonally.
  • Fig. 3 is a plan view showing the configuration, in which a scanning side driving circuit 11 is connected to the scanning electrode L of the FLCD 1 having a simple matrix configuration above mentioned, and a signal side driving circuit 12 is connected to the signal electrode S.
  • the scanning side driving circuit 11 is a circuit for applying voltages to the scanning electrodes L
  • the signal side driving circuit 12 is a circuit for applying voltages to the signal electrodes S.
  • the scanning electrodes L are 32 and the signal electrodes S are 16, i.e.
  • Fig. 4 is a waveform diagram showing respective signals outputted from the personal computer 2.
  • Fig. 4 (1) is a horizontal synchronizing signal HD which gives the timing of one scanning interval of a screen of the CRT 3
  • Fig. 4 (2) is a vertical synchronizing signal VD showing a period for one picture screen
  • Fig. 4 (3) shows display data Data of an image.
  • Fig. 4 (4) is a waveform diagram showing an expanded scanning interval of the horizontal synchronizing signal HD
  • Fig. 4 (5) is a waveform diagram showing an expanded scanning interval of the display data Data
  • Fig. 4 (6) is a waveform diagram showing a data transfer clock CLK of the display data Data for one picture element.
  • Fig. 5 is a waveform diagram showing respective signals outputted from the control circuit 4.
  • Fig. 5 (1) is a waveform diagram showing a clock YCLK for sequentially transferring the selective signal YI which selects the scanning electrode L, in a shift register, not shown, included in the scanning side driving circuit 11,
  • Fig. 5 (2) is a waveform diagram showing the selective signal YI and Fig. 5.
  • (3) shows the display data DATA corresponding to respective picture elements of the FLCD 1.
  • Fig. 5 (4) is a waveform diagram showing an expanded one period of the clock YCLK
  • Fig. 5 (5) is a waveform diagram showing an expanded one period of the clock YCLK of the selective signal YI, Fig.
  • Fig. 5 (6) is a waveform diagram showing an expanded one period of the clock YCLK of the display data DATA
  • Fig. 5 (7) is a waveform diagram showing a display data transfer clock XCLK for sequentially transferring the display data DATA, in a shift register, not shown, included in the signal side driving circuit 12
  • Fig. 5 (8) is an expanded waveform diagram of a latch pulse LP which gives timing for taking in and holding the display data DATA in the shift register of the signal side driving circuit 12, into a separate register, not shown, included in the same signal side driving circuit 12
  • Fig. 5 (9) is a waveform diagram showing a signal VC which designates kinds of voltage applied to the scanning electrodes L
  • Fig. 5 (10) is a waveform diagram showing a signal VS which designates kinds of voltage applied to the signal electrodes S.
  • a function is given to transform four kinds of signals show in Fig. 4, i.e. the horizontal synchronizing signal HD, vertical synchronizing signal VD, display data Data and data transfer clock YCLK, into seven kinds of signals shown in Fig. 5, i.e. the clock YCLK, selective signal YI, display data DATA, display data transfer clock XCLK, latch pulse LP and signals VC, VS.
  • Fig. 6 is a waveform diagram showing respective impressed voltage wave forms to the scanning electrodes L and the signal electrodes S used in a driving method of the FLCD 1 proposed in Japanese Patent Application Laid Open No. Sho 64-59389 (1989).
  • a waveform shown in Fig. 6 (1) is applied to the scanning electrode L and is the waveform of a selective voltage A which is able to rewrite a memory state of picture elements on the scanning electrodes L, or a luminance state displayed, and though a waveform shown in Fig. 6 (2) is applied to the scanning electrodes L, it is the waveform of a non-selective voltage B which can not rewrite the display state of picture elements on the scanning electrodes L.
  • Fig. 6 (3) is the waveform of a rewriting bright voltage C applied to the signal electrodes S when rewriting the picture elements into the "bright” luminance state
  • a waveform shown in Fig. 6 (4) is the waveform of a rewriting dark voltage D applied to the signal electrodes S when rewriting the picture elements into the "dark” luminance state
  • a waveform shown in Fig. 6 (5) is the waveform of a non-rewriting voltage G applied to the signal electrodes S when the display state of the picture element S is not rewritten.
  • Fig. 6 (6) through Fig. 6 (11) show the waveforms of the effective voltage applied to the picture element Aij, among which, a waveform A-C in Fig.
  • FIG. 6 (6) shows the waveform when the selective voltage A is applied to the scanning electrode Li and the rewriting bright voltage C is applied to the signal electrode Sj
  • a waveform A-D in Fig. 6 (7) shows the waveform when the selective voltage A is applied to the scanning electrode Li and the rewriting dark voltage D is applied to the signal electrode Sj
  • a waveform A-G in Fig. 6 (8) shows the waveform when the selective voltage A is applied to the scanning electrode Li and the non-rewriting voltage G is applied to the signal electrode Sj
  • FIG. 6 (9) shows the waveform when the non-selective voltage B is applied to the scanning electrode Li and the rewriting bright voltage C is applied to the signal electrode Sj
  • a waveform B-D in Fig. 6 (10) shows the waveform when the non-selective voltage B is applied to the scanning electrode Li and the rewriting dark voltage D is applied to the signal electrode Sj
  • a waveform B-G in Fig. 6 (11) shows the waveform when the non-selective voltage B is applied to the scanning electrode Li and the non-rewriting voltage G is applied to the signal electrode Sj.
  • the picture element Aij rewritten into the "bright” display state from the "dark” display state is represented by a symbol C corresponding to the rewriting bright voltage C
  • the picture element Aij rewritten into the "dark” display state from the "bright” display state is represented by a symbol D corresponding to the rewriting dark voltage D
  • the picture element Aij which remains as the "dark” display state is indicated by a symbol F
  • the picture element Aij which remains as the bright display state is indicated by an uninscribed symbol
  • the picture element Aij of symbol F and that of uninscribed symbol correspond to the non-rewriting voltage G.
  • Fig. 9 shows respective voltage waveforms applied to the scanning electrodes L1, L2, L3, signal electrodes S5, S6, and picture elements A15, A16, A25, A26 at this time.
  • Fig. 9 (1) shows a waveform of the transferring clock YCLK of the selective signal YI at the shift register in the scanning side driving circuit 11
  • Fig. 9 (2) shows a waveform of the selective signal YI
  • Fig. 9 (3) shows an impressed voltage waveform to the scanning electrode L1
  • Fig. 9 (4) shows an impressed voltage waveform to the scanning electrode L2
  • Fig. 9 (5) shows an impressed voltage waveform to the scanning electrode L3
  • Fig. 9 (6) shows an impressed voltage waveform to the signal electrode S5, Fig.
  • Fig. 9 (7) shows an impressed voltage waveform to the signal electrode S6, Fig. 9 (8) shows an effective voltage waveform applied to the picture element A15, Fig. 9 (9) shows an effective voltage waveform applied to the picture element A16, Fig, 9 (10) shows an effective voltage waveform applied to the picture element A25 and Fig. 9 (11) shows an effective voltage waveform applied to the picture element A26.
  • a symbol E, F in parentheses corresponds to the non-symbolic picture element in Fig. 8, that is, it indicates that the non-rewriting voltage G is applied to the non-symbolic picture element in Fig. 8.
  • the voltages applied to the picture element Aij are substantially equal whether or not the scanning electrode Li is selected, as far as its display state is not rewritten. Thereby, even in the case of low-speed driving wherein the time required for applying the selective voltage A to a certain scanning electrode Li and to the same scanning longer than 33.3 millisecond (corresponds to 30 Hz), it can be displayed without sensing any flicker.
  • the present invention provides a controller for a ferroelectric liquid crystal display panel, the panel comprising an array of picture elements each defined by the intersection of one of a plurality of scanning electrodes and one of a plurality of signal electrodes, and ferroelectric liquid crystal disposed therebetween, the controller comprising: control means for supplying selection signals for selecting scanning electrodes of the display panel and, during the selection of each scanning electrode, data signals for applying data to the signal electrodes of the display panel; characterised by: a first memory which receives and stores the data for the next display frame; a second memory which receives and stores that part of the data for the current display frame which differs from said data for the next display frame; a line memory for storing the result of a comparison, on a line-by-line basis, of said data for the next display frame with said data for the current display frame, for each line; and said control means being arranged to supply, according to the content of said line memory, a succession of said selection signals which excludes selection signals for all or certain of
  • the present invention provides a method of controlling a ferroelectric liquid crystal display panel, the panel comprising an array of picture elements each defined by the intersection of one of a plurality of scanning electrodes and one of a plurality of signal electrodes, and ferroelectric liquid crystal disposed therebetween, the method comprising: supplying to the display panel, selection signals for selecting scanning electrodes thereof and, during the selection of each scanning electrode, data signals for applying data to the signal electrodes thereof; characterised by: storing in a first memory the data for the next display frame; storing in a second memory that part of the data for the current display frame which differs from said data for the next display frame; comparing, on a line-by-line basis, said data for the next display frame with said data for the current display frame; storing in memory the result of the comparison for each line; and the supplying step comprising outputting, according to the content of said memory, a succession of said selection signals which excludes selection signals for all or certain of all the scanning electrodes which correspond to lines for which
  • the selective voltage is not applied at all or only applied to some of the (m-q) scanning electrodes, so that even when p scanning electrodes out of the rest (m-q) are selected, the selective voltage is not applied to (m-q-p) scanning electrodes during one frame.
  • a frame period is considerably shortened.
  • the scanning electrodes wherein the displayed data of the picture elements on the scanning electrode displayed at present is the same as the display data in the following frame, are not selected at all in the following frame or are selected at the rate of one out of several scanning electrodes, even in the case of a ferroelectric liquid crystal panel having a large number of scanning electrodes, the frame period can be shortened by the decreased number of scanning electrodes being selected in one frame, and a response time till the display data inputted is displayed on the picture screen can be shortened accordingly.
  • Fig. 10 is a block diagram showing a configuration of a display system in which a display control apparatus for a ferroelectric liquid crystal panel as one embodiment of the invention is applied.
  • the configuration of the display system is schematically as same as the case of a conventional display system stated above, and wherein a signal necessary for the image display is digitized, and the digital signal outputted to a CRT (cathode ray tube) 23 for image display from a personal computer 22 is used.
  • the digital signal outputted from the personal computer 22 is transformed in a control circuit 24 serving as the display control apparatus of the embodiment, the transformation signal displaying images on an FLCD 21.
  • the FLCD 21 As to the specific configuration of the FLCD 21, since it is as same as the conventional FLCD 1 shown in Fig. 2, explanation thereof will be omitted.
  • FIG. 11 is a block diagram schematically showing, a configuration of the control circuit 24.
  • a frame memory for display data 25 is a memory for holding display data Data for one picture screen outputted from the personal computer 22. From the frame memory for display data 25, transformation data Rx indicating the difference between the display data displayed at present on the picture screen of the FLCD 21 and display data to be displayed in the following frame is output.
  • a line memory 26 is a memory for, in response to the transformation data Rx outputted from the frame memory for display data 25, holding line difference identification data indicating whether there is even one picture element which is different in the display data displayed at present and display data to be displayed in the following frame, in the picture elements on each scanning electrode of the FLCD 21, separately for each scanning electrode.
  • line memory 26 a 1-bit memory area is allocated respectively for holding the line difference identification data of each of the scanning electrodes.
  • a frame memory for reference 27 is a memory for holding the transformation data Rx for one picture screen outputted from the frame memory for display data 25.
  • An input control circuit 28 is a circuit for controlling data writing into the frame memory for display data 25, line memory 26 and frame memory for reference 27, in response to the horizontal synchronizing signal HD, vertical synchronizing signal VD and clock CLK outputted from the personal computer 22, and signals OW, OAc and OAs outputted from an output control circuit 29.
  • the output control circuit 29 is a circuit for controlling the read out of hold data from the frame memory for display data 25, line memory 26 and frame memory for reference 27 and the output of a drive control circuit 30.
  • the drive control circuit 30 is a circuit for outputting the signal which controls the display drive of the FLCD 21, in response to data DO given from the frame memory for display data 25 and data DRE given from the frame memory for reference 27.
  • Fig. 12 is a plan view showing a configuration, wherein to the scanning electrodes L of the FLCD 21 of a simple matrix construction above mentioned a scanning side driving circuit 31 is connected, and to the signal electrodes S a signal side driving circuit 32 is connected.
  • the scanning side driving circuit 31 is a circuit for applying the voltage to the scanning electrodes L
  • the signal side driving circuit 32 is a circuit for applying the voltage to the signal electrodes S.
  • the FLCD 21 having 32 scanning electrodes L and 16 signal electrodes S, i.e.
  • Fig. 13 is a view schematically showing the transformation data Rx of one picture screen held in the frame memory for reference 27 in the form of display on the picture screen of the FLCD 21, when the picture screen of the FLCD 21 is switched to a state wherein Japanese characters meaning "ORDINARY DIELECTRIC" are displayed by the "dark” display picture elements indicated by oblique lines as shown in Fig. 12, from a state wherein Japanese characters meaning "FERROELECTRIC” shown in Fig. 3 in the explanation of the prior art are displayed.
  • the portions of the display where the picture elements are provided with the oblique lines represent that, the transformation data Rx of the picture elements is the data which indicates that display data displayed at present and display data to be displayed in the following frame are different.
  • Fig. 14 and Fig. 15 are waveform diagrams showing respective output signals outputted from the control circuit 24 to the FLCD 21 at switching operation of the picture screen.
  • Fig. 14 (1) and Fig. 15 (1) are waveform diagrams showing a clock YCLK for sequentially transferring the selective signal YI which selects the scanning electrodes L in a shift register, not shown, included in the scanning side driving circuit 11,
  • Fig. 14 (2) and Fig. 15 (2) are waveform diagrams showing the selective signal YI
  • Fig. 14 (3) and Fig. 15 (3) show display data DATA corresponding to each picture element of the FLCD 21.
  • Fig. 15 (4) are waveform diagrams showing the clock LCLK given to the scanning side driving circuit 31 at every one selective time of the scanning electrodes L.
  • Fig. 14 (5) is an expanded waveform diagram showing one period of the clock YCLK
  • Fig. 14 (6) is an expanded waveform diagram showing one one period of the clock YCLK of the selective signal YI
  • Fig. 14 (7) is an expanded waveform diagram showing one period of the clock YCLK of the display data DATA
  • Fig. 14 (8) is a waveform diagram showing data transfer clock XCLK for sequentially transferring the display data DATA in a shift register, not shown, included in the signal side driving circuit 32, Fig.
  • FIG. 14 (9) is an expanded waveform diagram of a latch pulse LP which gives timing for taking in and holding the display data DATA in the shift register of the signal side driving circuit 32, in a separate register, not shown, included in the same signal side driving circuit 32
  • Fig. 14 (10) is a waveform diagram showing the signal VC which designates the kinds of voltage applied to the scanning electrodes L
  • Fig. 14 (11) is a waveform diagram showing the signal VS which designates the kinds of voltage applied to the signal electrode S.
  • Fig. 15 (1) through Fig. 15. (4) show the waveforms following respective waveforms of Fig. 14 (1) through Fig. 14 (4).
  • Fig. 16 is a waveform diagram showing respective signals outputted from the input control circuit 28 at the operation.
  • Fig. 16 (1) shows a waveform of an input side clock ISCP in which the data transfer clock CLK outputted from the personal computer 22 is delayed by the constant time
  • Fig. 16 (2) shows a waveform of a timing pulse RE for parallel transformation of the display data Data
  • Fig. 16 (3) shows data of a line address Ac of the frame memory for display data 25, line memory 26 and frame memory for reference 27 corresponding to the scanning electrodes L
  • Fig. 16 (4) shows data of a row address As of the frame memory for display data 25 and the frame memory for reference 27 corresponding to the signal electrodes S, Fig.
  • FIG. 16 (5) shows a waveform of a timing pulse IOE for reading data from the frame memory for display data 25, line memory 26 and frame memory for reference 27 on the input side in synchronism with the clock ISCP
  • Fig. 16 (6) shows a waveform of a timing pulse IWE for writing data into the frame memory for display data 25, line memory 26 and frame memory for reference 27 on the input side in synchronism with the clock ISCP
  • Fig. 16 (7) shows a waveform of a timing pulse OOE for reading data from the output side of the frame memory for display data 25 and the frame memory for reference 27
  • Fig. 16 (8) shows a waveform of a timing pulse ROE which is outputted to the line memory 26 in synchronism with the clock ISCP
  • Fig. 16 (9) also shows a waveform of a timing pulse RWE which is sent out to the line memory 26 in synchronism with the clock ISCP.
  • Fig. 17 is a waveform diagram showing respective signals outputted from the output control circuit 29 at the operation.
  • Fig. 17 (1) shows a waveform diagram of an output side clock CP
  • Fig. 17 (2) shows a waveform of a timing pulse LO for serial transformation of data which are outputted to the frame memory for display data 25, line memory 26 and frame memory for reference 27 in synchronism with the clock CP
  • Fig. 17 (3) shows line difference identification data SAME given to the output control circuit 29 from the line memory 26 shown for reference
  • Fig. 17 (4) shows a timing pulse OW synchronizing with the clock CP
  • Fig. 17 (5) shows an output side line address OAc of the memories given to the frame memory for display data 25, line memory 26 and frame memory for reference 27, Fig.
  • Fig. 17 (6) shows an output side row address OAs of the memories given to the frame memory for display data 25 and the frame memory for reference 27
  • Fig. 17 (7) is a waveform diagram showing a timing pulse HCE for producing the clock YCLK given to the scanning side driving circuit 31 in the drive control circuit 30
  • Fig. 17 (8) is a waveform diagram showing a timing pulse HP for producing the clock LCLK given to the scanning side driving circuit 31, the latch pulse LP given to the signal side driving circuit 32 and respective impressed voltages in the drive control circuit 30,
  • Fig. 17 (9) is a waveform diagram showing a timing pulse VP for producing the selective signal YI given to the scanning side driving circuit 31 in the drive control circuit 30.
  • Fig. 18 is a waveform diagram showing respective voltage waveforms applied to the scanning electrodes L1, L2, L3, signal electrodes S5, S6 and picture elements A15, A16, A25, A26.
  • Fig. 18 (1) shows a waveform of the transfer clock YCLK of the selective signal YI in the shift register in the scanning side driving circuit 31 for reference
  • Fig. 18 (2) shows a waveform of the selective signal YI
  • Fig. 18 (3) shows a waveform of the clock LCLK which gives the timing of one selective time.
  • Fig. 18 (4) shows an impressed voltage waveform to the scanning electrode L1
  • Fig. 18 (5) shows an impressed voltage waveform to the scanning electrode L2
  • Fig. 18 (6) shows an impressed voltage waveform to the scanning electrode L3, Fig.
  • Fig. 18 (7) shows an impressed voltage waveform to the signal electrode S5
  • Fig. 18 (8) shows an impressed voltage waveform to the signal electrode S6
  • Fig. 18 (9) shows an effective voltage waveform applied to the picture element A15
  • Fig. 18 (10) shows an effective voltage waveform applied to the picture element A16
  • Fig. 18 (11) shows an effective voltage waveform applied to the picture element A25
  • Fig. 18 (12) shows an effective voltage waveform applied to the picture element A26.
  • a symbol E, F in parentheses corresponds to the non-symbolic picture element in Fig. 8, that is, it indicates that the non-rewriting voltage G is applied to the non-symbolic picture element in Fig. 8.
  • the operation abovementioned is controlled by the input control circuit 28. That is, in the input control circuit 28, the horizontal synchronizing signal HD and the vertical synchronizing signal VD outputted from the personal computer 22 are used for initialization, and the clock ISCP obtained by delaying the data transfer clock CLK outputted from the personal computer 22 by a constant time is used as a clock, and outputted to the frame memory for display data 25 with the clock ISCP and the timing pulse RE for parallel transformation of the display data Data.
  • a timing pulse IOE for reading out data from the memories 25, 26 and 27, a timing pulse IWE for writing data into the memories 25, 26 and 27 and address data switching an output-side line address OAc and an input-side line address OAc of these memories as a line address Ac accessing the memories 25, 26 and 27 are outputted from the input control circuit 28. Furthermore, from the input control circuit 28, in synchronism with the clock CP outputted from the output control circuit 29, a timing pulse OOE for reading out data from the memories 25, 27, and address data switching an output-side row address OAs and an input-side row address OAs of respective memories as a row address As accessing these memories are outputted.
  • data DO held in the frame memory for display data 25 and data DRE held in the frame memory for reference 27 are outputted to the drive control circuit 30.
  • a data transfer time T1 necessary for actually outputting the data DO and DRE is set sufficiently shorter than one selective time (6.t0), and the line difference data SAME of the line memory 26 corresponding to the scanning electrode L is confirmed by the output control circuit 29 before entering the data transfer time T1.
  • timing pulses ROE, RWE controlled by a timing pulse OW outputted from the output control circuit 29 and outputted to the line memory 26 from the input control circuit 28, and a timing pulse LO which is outputted to the frame memory for display data 25, line memory 26 and frame memory for reference 27 from the output control circuit 29.
  • a timing pulse VP for producing the selective signal YI inputted to the scanning side driving circuit 31 a timing pulse HCE for producing the clock YCLK inputted to the scanning side driving circuit 31
  • a timing pulse HP for producing the clock LCLK inputted to the scanning side drawing circuit 31 a latch pulse LP given to the signal side driving circuit 32 and respective impressed voltages, are outputted respectively.
  • the kinds of signal voltage applied to the signal electrodes S are decided by the data DO of the frame memory for display data 25 and the data DRE of the frame memory for reference 27. That is, for example, when the data DO is "bright" display data and the data DRE is data indicating the difference between display data in the present frame and the following frame, a rewriting bright voltage C is selected as the signal voltage, and when the data DO is "dark” display data and the data DRE is data indicating the difference between display data in the present and after frames, a rewriting dark voltage D is selected as the signal electrode.
  • a non-rewriting voltage G is selected as the signal electrode.
  • a display screen of a personal computer is rarely rewritten all at once, thus the number of scanning electrodes for which display data are changed can be substantially reduced depending upon a program design.
  • a word processor there is little chance that characters for several lines are rewritten at a time since the display data for each character is inputted, therefore, when one screen corresponds to one page, the number of scanning electrodes, for which the display data used to be rewritten, per one screen is about one line of characters and very few. Accordingly, in case the display control apparatus is used for display control of such personal computer and word processor, a frame period is shortened considerably and a response speed at which the screen is rewritten for the input is quickened.
  • a first-half waveform of the non-rewriting voltage G is equal to a first half waveform of the rewriting dark voltage D
  • a later-half waveform of the non-rewriting voltage G is equal to a later-half waveform of the rewriting bright voltage C.
  • the cost of the signal side driving circuit 32 can be cut.
  • polarizing plates are disposed so that the polarizing axis is parallel or orthogonal to the local alignment of the liquid crystal molecules.
  • the rewriting bright voltage C is used as a rewriting dark voltage
  • the rewriting dark voltage D is used as a rewriting bright voltage.
  • a waveform of a non-rewriting voltage is composed of a first-half waveform, which can not rewrite a picture element by combining with a selective voltage, of either the rewriting bright voltage or the rewriting dark voltage and a later-half waveform, which can not rewrite a picture element by combining with a selective voltage, of either the rewriting bright voltage or the rewriting dark voltage.
  • Fig. 19 shows the output control circuit 29 which is constituted by, four counters 33a to 33d, three D flip-flops 34a to 34c, six NAND gates 35a to 35f, one AND gate 36a, four NOR gates 37a to 37d, two OR gates 38a, 38b and four DIP switches 39a to 39d.
  • Fig. 20 shows the frame memory for display data 25 which is constituted by, eight NOT gates 40a to 40h, eight EX-OR gates 41a to 41h, two shift registers with latch 42a, 42b, one 3-state output buffer 43, one shift register 44, one static RAM (Random Access Memory) 45, two D flip-flops 46a, 46b, five NAND gates 47a to 47e, four AND gates 48a to 48d and a switch 49.
  • Fig. 21 shows the line memory 26 which is constituted by, one static RAM 50, four NOT gates 51a to 51d, two 3-state output buffers 52a, 52b, four D flip-flops 53a to 53d, two NAND gates 54a, 54b and ten AND gates 55a to 55j.
  • Fig. 22 shows the frame memory for reference 27 which is constituted by, seven NOT gates 56a to 56g, one static RAM 57, two D flip-flops 58a, 58b, one three-state output buffer 59, one shift register 60, eleven NAND gates 61a to 61k, four AND gates 62a to 62d and eight OR gates 63a to 63h.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)
EP90314433A 1989-12-29 1990-12-28 Display control method and apparatus for ferroelectric liquid crystal panel Expired - Lifetime EP0435701B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP342512/89 1989-12-29
JP1342512A JPH03203776A (ja) 1989-12-29 1989-12-29 強誘電性液晶パネルの表示制御装置

Publications (3)

Publication Number Publication Date
EP0435701A2 EP0435701A2 (en) 1991-07-03
EP0435701A3 EP0435701A3 (en) 1992-08-26
EP0435701B1 true EP0435701B1 (en) 1995-10-25

Family

ID=18354317

Family Applications (1)

Application Number Title Priority Date Filing Date
EP90314433A Expired - Lifetime EP0435701B1 (en) 1989-12-29 1990-12-28 Display control method and apparatus for ferroelectric liquid crystal panel

Country Status (4)

Country Link
EP (1) EP0435701B1 (ja)
JP (1) JPH03203776A (ja)
KR (1) KR940003428B1 (ja)
DE (1) DE69023215T2 (ja)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920006903A (ko) * 1990-09-27 1992-04-28 쯔지 하루오 액정표시 장치의 제어방법 및 표시 제어장치
JP3251064B2 (ja) * 1991-11-07 2002-01-28 シャープ株式会社 液晶パネルの表示制御装置
JP2996564B2 (ja) * 1991-11-08 2000-01-11 シャープ株式会社 液晶パネルの駆動方法
ATE171808T1 (de) * 1992-07-31 1998-10-15 Canon Kk Anzeigesteuergerät
EP0608053B1 (en) * 1993-01-11 1999-12-01 Canon Kabushiki Kaisha Colour display system
JP3222691B2 (ja) * 1994-07-04 2001-10-29 キヤノン株式会社 変化ライン検出装置および方法
JP3900663B2 (ja) * 1997-06-25 2007-04-04 ソニー株式会社 光学空間変調素子及び画像表示装置
JP2000182508A (ja) 1998-12-16 2000-06-30 Sony Corp 電界放出型カソード、電子放出装置、および電子放出装置の製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6118929A (ja) * 1984-07-05 1986-01-27 Seiko Instr & Electronics Ltd 強誘電性液晶電気光学装置
JP2768421B2 (ja) * 1987-08-31 1998-06-25 シャープ株式会社 強誘電性液晶表示装置の表示方法
AU634725B2 (en) * 1988-10-31 1993-03-04 Canon Kabushiki Kaisha Display system

Also Published As

Publication number Publication date
EP0435701A2 (en) 1991-07-03
DE69023215T2 (de) 1996-04-25
JPH03203776A (ja) 1991-09-05
KR940003428B1 (ko) 1994-04-22
KR910013036A (ko) 1991-08-08
EP0435701A3 (en) 1992-08-26
DE69023215D1 (de) 1995-11-30

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