EP0421772B1 - Display apparatus - Google Patents

Display apparatus Download PDF

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Publication number
EP0421772B1
EP0421772B1 EP90310846A EP90310846A EP0421772B1 EP 0421772 B1 EP0421772 B1 EP 0421772B1 EP 90310846 A EP90310846 A EP 90310846A EP 90310846 A EP90310846 A EP 90310846A EP 0421772 B1 EP0421772 B1 EP 0421772B1
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EP
European Patent Office
Prior art keywords
display
data
image data
pixel
display apparatus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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EP90310846A
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German (de)
English (en)
French (fr)
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EP0421772A3 (en
EP0421772A2 (en
Inventor
Atsushi Mizutome
Hiroshi Inoue
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Canon Inc
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Canon Inc
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Publication date
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Publication of EP0421772A2 publication Critical patent/EP0421772A2/en
Publication of EP0421772A3 publication Critical patent/EP0421772A3/en
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Publication of EP0421772B1 publication Critical patent/EP0421772B1/en
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G09G3/3629—Control of matrices with row and column drivers using a passive matrix using liquid crystals having memory effects, e.g. ferroelectric liquid crystals
    • G09G3/364—Control of matrices with row and column drivers using a passive matrix using liquid crystals having memory effects, e.g. ferroelectric liquid crystals with use of subpixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G09G3/3629—Control of matrices with row and column drivers using a passive matrix using liquid crystals having memory effects, e.g. ferroelectric liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0232—Special driving of display border areas
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0464—Positioning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/02—Graphics controller able to handle multiple formats, e.g. input or output formats
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels

Definitions

  • the present invention relates to a display apparatus and, more particularly, to an output circuit of image information which is suitable for application to a display apparatus using a binary display element such as a ferroelectric liquid crystal display element or the like having a bistability (memory performance) for an electric field.
  • a binary display element such as a ferroelectric liquid crystal display element or the like having a bistability (memory performance) for an electric field.
  • Fig. 10 shows a list of the above modes.
  • the number of constructing bits per pixel differs every display mode and a storage format in an image memory (VRAM) also differs. Hence, in the mode in which the number of constructing bits per pixel is large, the multi-color display can be executed.
  • VGA display mode 13(h)
  • VGA display mode 13(h)
  • An output flow of color information is as follows. First, when a certain address in a VRAM is accessed, the image data (bits/pixel: mode 13(h)) in a VRAM functions as an address to select a color register in a color palette in which color information has previously been stored.
  • the color palette has 256 color registers of 18 bits (6 bits for each of R, G, and B). The color information has been stored in the color registers.
  • the color data of R, G, and B each comprising six bits are read out and are led to D/A converters in the same color palette.
  • One D/A converter is provided for each of R, G, and B and converts the 6-bit color data into the analog signal and sends to a display (CRT).
  • the output method of the color information has advantages such that: the multi-color display can be realized although a data amount of the VRAM is not so large; the color on the display screen can be changed by rewriting the data of the color registers without needing to rewrite the data in the VRAM; the number of lines connected to the display can be reduced; and the like. Therefore, the above method is mainly a standard method in the present personal computers.
  • the resolution also differs every display mode.
  • the resolution is set to 320 x 200 pixels (picture elements) in the case of the mode D(h) and is set to 640 x 480 pixels in the case of the mode 12(h).
  • CTR display
  • the display modes which can display are restricted (limited).
  • multiscan partial CRTs of the automatic tracking type or the like called "multiscan” and “multisync”
  • a method whereby the scanning frequency of an electron beam is switched in accordance with each display mode is used to support the display modes in a relatively wide range. Therefore, if the display is executed in a display mode of small amount of display information (low resolution), the number of characters or numerals which are displayed as rough images is large.
  • the gradation (color) data in the depth direction which is inherently used for the CRT must be converted into the gradation data in the lateral direction (extending direction) in accordance with the arrangement of the pixels of the actual display apparatus in accordance with the display mode.
  • the display is executed in various display modes which have conventionally been used in the CRT or the like by using a display apparatus such as a ferroelectric liquid crystal display apparatus or the like of a high resolution (1000 x 1000 pixels or more)
  • the redundant pixels occur on the side of the liquid crystal display apparatus because the resolution in the CRT display mode is lower (an amount of display information is smaller) than the effective number of pixels (resolution) of the liquid crystal display apparatus.
  • the enlarged display can be also executed by simultaneously driving a plurality of electrodes in the vertical and lateral directions in a lump on the side of the liquid crystal display apparatus.
  • the enlarged display from one time to four times can be realized. Even if such an enlarged display is used, redundant pixels also occur in the portion out of the effective display area depending on the relation between the number of effective pixels (resolution) of the liquid crystal display apparatus and the resolution in the display mode.
  • Patent Abstracts of Japan, Vol 10, No. 232 (P-486) published 12 August 1986 and JP-A-61067024 discloses a method of driving a bistable liquid crystal display.
  • EP-A-0295691 discloses a display mode switching system for a plasma display apparatus.
  • the system can automatically or manually switch between colour graphic adapter (CGA) and enhanced colour graphic adapter (EGA) display modes.
  • CGA colour graphic adapter
  • EVA enhanced colour graphic adapter
  • EP-A-0195203 discloses a display controller for displaying an image on either a CRT display unit or a liquid crystal display unit.
  • a controller includes a memory in which image data is stored.
  • the present invention is made to eliminate the foregoing problems which cannot be realized by an image information output circuit which is used in a conventional CRT or the like. It is an object of the invention to realize an image information output circuit for displaying the screens in various display modes which have been used in a conventional CRT or the like onto a display apparatus using a binary display element such as a ferroelectric liquid crystal display apparatus or the like without losing image data.
  • a display apparatus which uses a display panel using a liquid crystal and which can display image data in a plurality of display modes with different display parameters such as the number of pixels, display colour, minimum pixel unit, said apparatus comprising: memory means for storing image data; said apparatus being characterised in further comprising: pixel data output means for taking an arbitrary number of pixel data from the image data stored in said memory means and for outputting that number of pixel data in pixel data units; conversion means for converting the pixel data output by said pixel data output means into binary data to be displayed on the display panel; display data output means for converting the binary data converted by said conversion means into display data corresponding to the display modes and for outputting the converted display data; and display control means for controlling the display panel to display thereon the display data output by said display data output means.
  • Fig. 2 is a whole constructional diagram of a graphics controller provided on the side of a main body apparatus such as a personal computer or the like as a supply source of image information and a ferroelectric liquid crystal display apparatus.
  • the image information output circuit according to the invention is provided in the graphics controller in Fig. 2.
  • the display panel is constructed by arranging 1024 scanning electrodes and 2560 information electrodes like a matrix and sealing a ferroelectric liquid crystal into a space between two glass plates which were subjected to an orientation process.
  • Scanning lines are connected to a scanning electrode driving circuit.
  • Information lines are connected to an information electrode driving circuit.
  • One pixel has a construction of two bits/pixel in which one pixel is divided into portions having an area ratio of 3:2 as shown in ⁇ in the display panel in Fig. 2.
  • the gradation display of four levels per pixel can be performed.
  • a display controller receives the display information from the image information output circuit according to the invention and controls the scanning electrode driving circuit and the information electrode driving circuit.
  • the graphics controller comprises: a CPU (central processing unit: hereinafter, referred to as a GCPU) to control the whole display functions; a VRAM (image information storing memory); and a display interface serving as an image information output circuit according to the invention.
  • the graphics controller controls the management of the display information and the whole communication between a host CPU and the display apparatus.
  • Fig. 1 is a constructional diagram of the display interface according to the invention.
  • the display interface comprises: a gradation conversion section 1 to convert image data from the VRAM into area gradation data; a border register 2 to determine data in the portion out of an effective display area; a scanning line address generator 3; and a data selector 4 for converting the image data into an output format to transfer the image data to the liquid crystal display apparatus.
  • the number of constructing bits per pixel of the image data stored in a VRAM 5 differs every display mode in a manner such that it is set to 4 bits/pixel in the mode 3(h) and is set to 8 bits/pixel in the mode 13(h).
  • data of two bytes (16 bits) in the image data stored in the VRAM 5 is always output by a single reading operation (access) for the VRAM 5. Therefore, the number of pixels which are output by a single access to the VRAM 5 differs depending on the display mode. For instance, the image data of four pixels is output in the case of the mode 3(h) by the single access.
  • the image data of two pixels is output in the case of the mode 13(h) by the single access. Since a palette RAM 12, which will be explained hereinlater, executes a gradation conversion on a pixel unit basis, the image data which was read out of the VRAM 5 must be led to the palette RAM 12 on a pixel unit basis.
  • a pixel multiplexer 11 is provided for this purpose.
  • Fig. 3 shows an image data conversion format of the pixel multiplexer 11.
  • the conversion modes are switched by a command from a GCPU 6 (Fig. 2).
  • the pixel multiplexer 11 is operated in a conversion mode B.
  • the pixel multiplexer 11 extracts the data of two pixels of VSD0 to VSD3 and VSD4 to VSD7 at the first phase from VSD0 to VSD15 including data of four pixels which are output from the VRAM 5 and leads as Q0 to Q3 and Q8 to Q11 to the palette RAM 12 and a palette RAM 13, respectively.
  • the data of two pixels of VSD8 to VSD11 and VSD12 to VSD15 are led to the palette RAMs 12 and 13 as Q0 to Q3 and Q8 to Q11, respectively.
  • the pixel multiplexer 11 separately leads the image data to the palette RAMs 12 and 13 at two phases.
  • conversion modes A and C correspond to the cases where the image data format in the VRAM is set to 8 bits/pixel and 2 bits/pixel, respectively.
  • the image data is led to the palette RAM 12 on a pixel unit basis.
  • the palette RAMs 12 and 13 correspond to a portion for converting the pixel data (color information) from the VRAM 5 into the ON/OFF data of the pixels of the actual display panel on a unit pixel basis, respectively.
  • the conversion from ⁇ color information in the depth direction> into ⁇ gradation information in the lateral direction> (area gradation) according to the invention is realized in the above portion.
  • two palette RAMs have been arranged in parallel as a countermeasure for a point that the image data conversion rate in the palette RAM is slower than a required transfer rate to the display apparatus. If a processing speed of the palette RAM is sufficiently high, no problem occurs even when only one palette RAM is used. On the contrary, in the case where a reading speed from the VRAM 5 or operating speeds of the multiplexers 11 and 14 are enough high, by increasing the number of palette RAMs, the processing speed of the conversion system can be raised in correspondence to it.
  • Each of the palette RAMs 12 and 13 is constructed by 256 registers having a length of eight bits which are called palette registers.
  • the gradation information (ON/OFF data of the pixels) corresponding to the color information of the pixels is previously written by the GCPU 6.
  • the same gradation information is written into the palette RAMs 12 and 13.
  • Figs. 4A to 4C are diagrams each showing the relation between the gradation data (ON/OFF data of pixels) of the palette register in the palette RAM and the arrangement of the pixels of the actual display panel.
  • Fig. 4C shows the minimum pixel unit of the display panel used in the embodiment. As mentioned above, one pixel is divided into portions at an area ratio of 3:2 and the gradation display of four levels is realized by respectively independently driving the two portions.
  • Each of Figs. 4B and 4A shows a handling of one pixel in the enlarged display mode. By handling four pixels and sixteen pixels as one pixel in a lump, respectively, the enlarged display of two times and four times can be realized. The number of gradations which can be displayed also increases to 8 levels and 16 levels.
  • the gradation data of the palette register corresponds to the ON/OFF data of each pixel on the display panel at a ratio of 1:1.
  • the pixel data (color information) from the VRAM 5 functions as an address to select the palette register in the palette RAM. For instance, in the case where the pixel data (color information) from the VRAM 5 relates to 4 bits/pixel, one of the 16 palette registers is selected. On the other hand, in the case where the pixel data relates to 8 bits/pixel and 2 bits/pixel, one of the 256 palette registers and one of the 4 palette registers are selected. When a certain palette register is selected, the gradation data PL0 to PL7 and PH0 to PH7 stored therein are output and are led to the pixel multiplexer 14 at the next stage.
  • the pixel multiplexer 14 executes a process to convert the ON/OFF data (data of at most eight bits) of the pixel which is output from the palette RAM into the number of bits which can be displayed in accordance with the enlarged display mode (e.g., 1x, 2x, 4x) of the display panel.
  • Fig. 6 shows conversion modes of the pixel multiplexer 14.
  • a conversion mode B is selected in the case of executing the enlarged display of two times (2x) by the display panel.
  • the number of gradation data which can be obtained per pixel is equal to four bits, only four lower bits (PL0 to PL3; PH0 to PH3) are extracted from the 8-bit data PL0 to PL7 and PH0 to PH7 which are output from the palette RAMs 12 and 13, respectively.
  • the extracted eight bits are output as PIX0 to PIX7.
  • conversion modes A and C show conversion formats in the enlarged display mode of four times (4x) and in the equal magnification mode (1x), respectively.
  • the pixel data (color information) in the VRAM 5 is converted into the gradation data on the display panel by the two multiplexers 11 and 14 and the palette RAMs.
  • the border register 2 has been provided to store data which is output to the border portion.
  • Fig. 7 shows a construction of a border register.
  • the border register fundamentally comprises one register of a length of eight bits and the eight bits correspond to border data BD0 to BD7 (Fig. 7), respectively.
  • the border register 2 has a construction of what is called a double buffer. Data in the border register 2 can be rewritten at an arbitrary timing from the GCPU 6.
  • the actual border data is set into a border register output stage at a timing of a horizontal or vertical sync signal.
  • a timing to transmit the data set in the border register 2 is controlled by horizontal and vertical blanking signals (HBlank and VBlank).
  • border data is output when either one of the horizontal and vertical blanking signals is set to the Lo (low) level (in the blanking period).
  • Image data in the effective display area is output in a period of time other than the blanking period.
  • the scanning line address generator 3 has been provided to generate scanning line address data A0 to A15 of the display panel.
  • the generator 3 comprises a 12-bit binary counter (up to 4096 scanning lines can be selected) which uses as clocks a horizontal sync signal Hsync which is input from the display controller on the liquid crystal display apparatus side.
  • the counter can preset a count value (scanning line address data) from the GCPU 6 at an arbitrary timing. Further, a count-up width (how many scanning lines should be jumped and scanned) can be also set.
  • the data selector 4 has been provided to realize those transfer formats.
  • the data selector 4 time-sharingly switches three kinds of data such as image data PD0 to PD7 which were subjected to the gradation conversion, border data BD0 to BD7, and scanning line address data A0 to A15 on the basis of timing control signals from the GCPU 6 and sends the switched data to the display apparatus.
  • Fig. 9 shows an example of a transfer format from the display interface serving as an image information output circuit according to the invention which conforms with the methods of the above propositions.
  • the data selector 4 first outputs the scanning line address data A0 to A15 by two cycles (four clocks (CLK)) by the timing control from the GCPU 6. Then, the border data BD0 to BD7 from the border register 2 are continuously transmitted onto communication lines PIX0 to PIX7 for a period of time until the HBlank is set to the Hi (high) level.
  • the image data PD0 to PD7 in the effective display area which were subjected to the gradation conversion are transmitted onto the communication lines PIX0 to PIX7.
  • the GCPU 6 again sets the HBlank to the Lo level.
  • the data selector 14 again allows the border data BD0 to BD7 to be transmitted onto the communication lines PIX0 to PIX7 and finishes the transfer of the data (640 pixels) of all of the pixels.
  • Fig. 9 shows transfer timings in the horizontal scanning direction.
  • the data selector 4 also similarly distinguishes the border area and the effective display area by using the vertical blanking signal with respect to the vertical scanning direction and switches the output data.
  • the effective display area can be also displayed at an arbitrary position on the display screen.
  • an image information output circuit having: a first multiplexer to lead image data which is read out of an image memory to the next stage every pixel; palette RAMs for outputting ON/OFF data of predetermined pixels on the basis of data which is output from the first multiplexer; and a second multiplexer to convert the data from the palette RAMs into an output format to transfer it to a display apparatus.
  • the converting process of the image data and the process of an area (frame portion) out of the effective display area are executed in accordance with a display mode request from a main body CPU.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Measuring Pulse, Heart Rate, Blood Pressure Or Blood Flow (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Compounds Of Unknown Constitution (AREA)
  • Preparation Of Compounds By Using Micro-Organisms (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Vehicle Body Suspensions (AREA)
  • Diaphragms For Electromechanical Transducers (AREA)
  • Image Generation (AREA)
  • Liquid Crystal (AREA)
  • Forging (AREA)
  • Led Device Packages (AREA)
EP90310846A 1989-10-06 1990-10-04 Display apparatus Expired - Lifetime EP0421772B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP261297/89 1989-10-06
JP1261297A JP2877381B2 (ja) 1989-10-06 1989-10-06 表示装置及び表示方法

Publications (3)

Publication Number Publication Date
EP0421772A2 EP0421772A2 (en) 1991-04-10
EP0421772A3 EP0421772A3 (en) 1992-11-19
EP0421772B1 true EP0421772B1 (en) 1995-12-27

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EP90310846A Expired - Lifetime EP0421772B1 (en) 1989-10-06 1990-10-04 Display apparatus

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EP (1) EP0421772B1 (ja)
JP (1) JP2877381B2 (ja)
KR (2) KR940002237B1 (ja)
AT (1) ATE132287T1 (ja)
AU (1) AU638754B2 (ja)
CA (1) CA2027043C (ja)
DE (1) DE69024448T2 (ja)
DK (1) DK0421772T3 (ja)
ES (1) ES2081942T3 (ja)
GR (1) GR3018924T3 (ja)

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JPS5731268A (en) * 1980-07-31 1982-02-19 Matsushita Electric Ind Co Ltd Frame signal generator
JPS6151554U (ja) * 1984-09-05 1986-04-07
JPS6167024A (ja) * 1984-09-10 1986-04-07 Canon Inc 液晶素子の駆動法
JPS61213896A (ja) * 1985-03-19 1986-09-22 株式会社　アスキ− デイスプレイコントロ−ラ
JP2535324B2 (ja) * 1985-05-13 1996-09-18 キヤノン株式会社 表示制御装置
JPS6334593A (ja) * 1986-07-30 1988-02-15 ホシデン株式会社 多階調表示方法
EP0295691B1 (en) * 1987-06-19 1994-11-23 Kabushiki Kaisha Toshiba Display mode switching system for plasma display apparatus
JP2797435B2 (ja) * 1989-05-26 1998-09-17 ヤマハ株式会社 表示コントローラ

Also Published As

Publication number Publication date
EP0421772A3 (en) 1992-11-19
AU6385890A (en) 1991-04-11
AU638754B2 (en) 1993-07-08
KR940002345B1 (ko) 1994-03-23
DE69024448D1 (de) 1996-02-08
JPH03123386A (ja) 1991-05-27
DE69024448T2 (de) 1996-05-23
EP0421772A2 (en) 1991-04-10
CA2027043C (en) 1995-02-14
CA2027043A1 (en) 1991-04-07
KR910008602A (ko) 1991-05-31
ES2081942T3 (es) 1996-03-16
GR3018924T3 (en) 1996-05-31
KR940002237B1 (ko) 1994-03-19
ATE132287T1 (de) 1996-01-15
DK0421772T3 (da) 1996-01-29
JP2877381B2 (ja) 1999-03-31

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