CA2027043C - Display apparatus - Google Patents
Display apparatusInfo
- Publication number
- CA2027043C CA2027043C CA002027043A CA2027043A CA2027043C CA 2027043 C CA2027043 C CA 2027043C CA 002027043 A CA002027043 A CA 002027043A CA 2027043 A CA2027043 A CA 2027043A CA 2027043 C CA2027043 C CA 2027043C
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- Prior art keywords
- display
- data
- image data
- pixel
- display apparatus
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3622—Control of matrices with row and column drivers using a passive matrix
- G09G3/3629—Control of matrices with row and column drivers using a passive matrix using liquid crystals having memory effects, e.g. ferroelectric liquid crystals
- G09G3/364—Control of matrices with row and column drivers using a passive matrix using liquid crystals having memory effects, e.g. ferroelectric liquid crystals with use of subpixels
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3622—Control of matrices with row and column drivers using a passive matrix
- G09G3/3629—Control of matrices with row and column drivers using a passive matrix using liquid crystals having memory effects, e.g. ferroelectric liquid crystals
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0232—Special driving of display border areas
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/04—Changes in size, position or resolution of an image
- G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/04—Changes in size, position or resolution of an image
- G09G2340/0464—Positioning
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2360/00—Aspects of the architecture of display systems
- G09G2360/02—Graphics controller able to handle multiple formats, e.g. input or output formats
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2074—Display of intermediate tones using sub-pixels
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Liquid Crystal Display Device Control (AREA)
- Measuring Pulse, Heart Rate, Blood Pressure Or Blood Flow (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Compounds Of Unknown Constitution (AREA)
- Preparation Of Compounds By Using Micro-Organisms (AREA)
- Controls And Circuits For Display Device (AREA)
- Vehicle Body Suspensions (AREA)
- Diaphragms For Electromechanical Transducers (AREA)
- Image Generation (AREA)
- Liquid Crystal (AREA)
- Forging (AREA)
- Led Device Packages (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
There is provided a display apparatus which uses a display panel using a liquid crystal having a bistability or a memory performance such as a ferro-electric liquid crystal and can display image data in various display modes in which the number of pixels (resolution), display color, minimum pixel unit, and the like respectively differ. The display apparatus comprises: a memory to store the image data; a pixel data output circuit to output the image data stored in the memory every pixel data; a converter to convert the pixel data which was output from the pixel data output circuit into binary data which is displayed on the display panel; a display data output circuit for converting the binary data converted by the converter into the display data corresponding to the display mode and outputting; and a display controller for allowing the image data which was output by the display data output circuit to be displayed on the display panel.
A multiplexer is used as a pixel data output circuit.
An RAM in which binary data has been stored is used as a converter.
There is provided a display apparatus which uses a display panel using a liquid crystal having a bistability or a memory performance such as a ferro-electric liquid crystal and can display image data in various display modes in which the number of pixels (resolution), display color, minimum pixel unit, and the like respectively differ. The display apparatus comprises: a memory to store the image data; a pixel data output circuit to output the image data stored in the memory every pixel data; a converter to convert the pixel data which was output from the pixel data output circuit into binary data which is displayed on the display panel; a display data output circuit for converting the binary data converted by the converter into the display data corresponding to the display mode and outputting; and a display controller for allowing the image data which was output by the display data output circuit to be displayed on the display panel.
A multiplexer is used as a pixel data output circuit.
An RAM in which binary data has been stored is used as a converter.
Description
I
, 7 DO SPLAY APPARATUS
BACKGROUND OF THE INVENTION
Field of the Invention The present invention relates to a display apparatus and, more particularly, to an output circuit of image information which is suitable for application to a display apparatus using a binary display element such as a ferroelectric liquid crystal display element or the like having a bistability (memory performance) for an electric field.
elated Background Art Recently in displays of personal computers, work stations, and the like, realization of a large display screen and a high resolution is rapidly being progressed. Many display modes including the conventional display modes exist. When explaining an example of a graphics environment of a personal computer made of IBM tirade name: International Business Machines Corporation) which is generally frequently used, there are ten and a few kinds of display modes such as CGA
(Color Graphic Adapter), ETA (Enhanced Graphic Adapter, VIA (Video Graphic Adapter), and the like. The resole-lions and the numbers of colors which can be displayed in those display modes are different, respectively.
Fig. 10 shows a list of the above modes.
r, 1 (1) With respect to the display color:
As will be understood from Fig. 10, the number of constructing bits per pixel (bits/pixel) differs every display mode and a storage format in an image memory (TRAM) also differs. Apparently, in the mode in which the number of constructing bits per pixel is large, the multi-color display can be executed.
Explanation will now be made as an example with respect to the display mode 13(h) (VIA) which can perform the highest multi-color display in the graphics environ-mint of the personal computer made by IBM Corporation.
An output flow of color information is as follows. First, when a certain address in a TRAM is accessed, the image data (bits/pixel: mode 13(h)) in a TRAM functions as an address to select a color register in a color palette in which color information has previously been stored.
In the case of the VIA, the color palette has 256 color registers of 18 bits I bits for each of R, G, and B).
The color information has been stored in the color registers. When one of the 256 color registers is selected by image data from the TRAM, the color data of R, G, and B each comprising six hits are read out and are led to D/A converters in the same color palette.
One D/A converter is provided for each of R, G, and 25 By and converts the 6-bit color data into the analog signal and sends to a display (CRETE. -The output method of the color information , I
1 color palette + analog output) as mentioned above has advantages such that: the multi-color display can be realized although a data amount of the TRAM is not so large; the color on the display screen can be changed by rewriting the data of the color registers without needing to rewrite the data in the TRAM; the number of lines connected Jo the display can be reduced; and the like. Therefore, the above method is mainly a standard method in the present personal computers.
lo (2) With respect to the resolution:
In Fig. 10, the resolution also differs every display mode For instance, the resolution is set to 320 200 pixels (picture elements in the case of the mode Do and is set to 640 x 480 pixels in the case of the mode 12(h). Such a method whereby all of a number of kinds of display modes are supported by one display (CRT) is hitherto considered to be relatively difficult.
In general, the display modes which can display are restricted (limited). On the other hand, in partial Cuts of the automatic tracking type or the like called "multi scan" and "multi sync", a method whereby the scanning frequency of an electron beam is switched in accordance with each display mode is used to support the display modes in a relatively wide range. Therefore, if the display is executed in a display mode of small amount of display information (low resolution), the number of characters or numerals which are displayed as rough 4 Jo I 3 1 images is large.
Different from the case of displaying by the CRT or the like, the following points must be considered in the case where various kinds of display modes of different display colors and resolutions are applied to a display apparatus using a liquid crystal such as a ferroelectric liquid crystal or the like having the memory performance and color information is displayed.
(1) With respect to the display color:
In the case of a display apparatus using a binary display element represented by a ferroelectric liquid crystal display apparatus or the like, it is difficult to express gradations (in the depth direction) in an analogous manner in one pixel (picture element) like a CRT or the like, that is, to three-dimensionally execute a gradation display. In the case of executing the grade-lion display by the binary display element, in general, a process such that the gradation (color) data in the depth direction is developed in the lateral direction 20 extending direction) is executed and the color Norma lion is two-dimensionally displayed (area gradation).
Therefore, in the case where color information is displayed by the ferroelectric liquid crystal display apparatus or the like in various display modes of different display colors, the gradation (color) data in the depth direction which is inherently used for the CRT must be converted into the gradation data in Jo '3 1 the lateral direction (extending direction) in accordance with the arrangement of the pixels of the actual display apparatus in accordance with the display mode.
, 7 DO SPLAY APPARATUS
BACKGROUND OF THE INVENTION
Field of the Invention The present invention relates to a display apparatus and, more particularly, to an output circuit of image information which is suitable for application to a display apparatus using a binary display element such as a ferroelectric liquid crystal display element or the like having a bistability (memory performance) for an electric field.
elated Background Art Recently in displays of personal computers, work stations, and the like, realization of a large display screen and a high resolution is rapidly being progressed. Many display modes including the conventional display modes exist. When explaining an example of a graphics environment of a personal computer made of IBM tirade name: International Business Machines Corporation) which is generally frequently used, there are ten and a few kinds of display modes such as CGA
(Color Graphic Adapter), ETA (Enhanced Graphic Adapter, VIA (Video Graphic Adapter), and the like. The resole-lions and the numbers of colors which can be displayed in those display modes are different, respectively.
Fig. 10 shows a list of the above modes.
r, 1 (1) With respect to the display color:
As will be understood from Fig. 10, the number of constructing bits per pixel (bits/pixel) differs every display mode and a storage format in an image memory (TRAM) also differs. Apparently, in the mode in which the number of constructing bits per pixel is large, the multi-color display can be executed.
Explanation will now be made as an example with respect to the display mode 13(h) (VIA) which can perform the highest multi-color display in the graphics environ-mint of the personal computer made by IBM Corporation.
An output flow of color information is as follows. First, when a certain address in a TRAM is accessed, the image data (bits/pixel: mode 13(h)) in a TRAM functions as an address to select a color register in a color palette in which color information has previously been stored.
In the case of the VIA, the color palette has 256 color registers of 18 bits I bits for each of R, G, and B).
The color information has been stored in the color registers. When one of the 256 color registers is selected by image data from the TRAM, the color data of R, G, and B each comprising six hits are read out and are led to D/A converters in the same color palette.
One D/A converter is provided for each of R, G, and 25 By and converts the 6-bit color data into the analog signal and sends to a display (CRETE. -The output method of the color information , I
1 color palette + analog output) as mentioned above has advantages such that: the multi-color display can be realized although a data amount of the TRAM is not so large; the color on the display screen can be changed by rewriting the data of the color registers without needing to rewrite the data in the TRAM; the number of lines connected Jo the display can be reduced; and the like. Therefore, the above method is mainly a standard method in the present personal computers.
lo (2) With respect to the resolution:
In Fig. 10, the resolution also differs every display mode For instance, the resolution is set to 320 200 pixels (picture elements in the case of the mode Do and is set to 640 x 480 pixels in the case of the mode 12(h). Such a method whereby all of a number of kinds of display modes are supported by one display (CRT) is hitherto considered to be relatively difficult.
In general, the display modes which can display are restricted (limited). On the other hand, in partial Cuts of the automatic tracking type or the like called "multi scan" and "multi sync", a method whereby the scanning frequency of an electron beam is switched in accordance with each display mode is used to support the display modes in a relatively wide range. Therefore, if the display is executed in a display mode of small amount of display information (low resolution), the number of characters or numerals which are displayed as rough 4 Jo I 3 1 images is large.
Different from the case of displaying by the CRT or the like, the following points must be considered in the case where various kinds of display modes of different display colors and resolutions are applied to a display apparatus using a liquid crystal such as a ferroelectric liquid crystal or the like having the memory performance and color information is displayed.
(1) With respect to the display color:
In the case of a display apparatus using a binary display element represented by a ferroelectric liquid crystal display apparatus or the like, it is difficult to express gradations (in the depth direction) in an analogous manner in one pixel (picture element) like a CRT or the like, that is, to three-dimensionally execute a gradation display. In the case of executing the grade-lion display by the binary display element, in general, a process such that the gradation (color) data in the depth direction is developed in the lateral direction 20 extending direction) is executed and the color Norma lion is two-dimensionally displayed (area gradation).
Therefore, in the case where color information is displayed by the ferroelectric liquid crystal display apparatus or the like in various display modes of different display colors, the gradation (color) data in the depth direction which is inherently used for the CRT must be converted into the gradation data in Jo '3 1 the lateral direction (extending direction) in accordance with the arrangement of the pixels of the actual display apparatus in accordance with the display mode.
(2) With respect to the resolution:
In the case where the display is executed in various display modes which have conventionally been used in the CRT or the like by using a display apparatus such as a ferroelectric liquid crystal display apparatus or the like of a high resolution (Lowe x Lowe pixels or more), the redundant pixels (the pixels remain) occur on the side of the liquid crystal display apparatus because the resolution in the CRT display mode is lower (an amount of display information is smaller) than the effective number of pixels (resolution) of the liquid crystal display apparatus. In such a case, the enlarged display can be also executed by simultaneously driving a plurality of electrodes in the vertical and lateral directions in a lump on the side of the liquid crystal display apparatus. For instance, in the case of displaying the screen in the mode Do (320 x 200 pixels) by the ferroelectric liquid crystal display apparatus of 1280 x 1024 pixels or the like, the enlarged display from one time to four times can be realized. Even if such an enlarged display is used, redundant pixels also 25 occur in the portion out of the effective display area -I
depending on the relation between the number of effective pixels (resolution) of the liquid crystal display apparatus 1 and the resolution in the display mode.
Therefore, it is necessary to execute a proper process to the portion border portion) of the redundant pixels out of the effective display area.
In the case of displaying in the display mode of a low resolution by the CRT, the portion to which an electron beam is not irradiated is held black (dark) by thinning out and scanning the fluorescent display surface by reducing the scanning frequency of the electron beam. however, in the case of the ferroelectric liquid crystal display apparatus, if no image data is input, a state of the pixel is not assured (bright or dark, on or off). Therefore, it is necessary to also input data into the portion of the redundant pixels and to drive and control.
SUMMARY OF THE INVENTION
The present invention is made to eliminate the foregoing problems which cannot be realized by an image information output circuit which is used in a conventional CRT or the like. It is an object of the invention to realize an image information output circuit for displaying the screens in various display modes which have been used in a conventional CRT or the like onto a display apparatus using a binary display element such as a ferroelectric liquid crystal display apparatus or the like without losing image data.
- 7 - ?,~
1 Another object of the invention is to realize an image information output circuit of a display apparatus using a ferroelectric liquid crystal or the like having a bistability [memory performance), comprising: a first 5 multiplexer for leading image data which is read out of an image memory to the next stage every pixel data;
palette Rams each for outputting pixel data on the hasps of the data which is output from the first multiplexer;
and a second multiplexer for converting the pixel data from the palette RAM into an output format to transfer to the display apparatus, wherein a converting process of the image data and a process for an area frame portion) out of the effective display area are executed in accordance with a display mode request from the main body CPU, thereby making it possible to cope with a number of various display modes.
BRIEF DESCRIPTION OF TIE DRAWINGS
Fig. 1 is a constructional diagram of an image information output circuit according to the invention;
Fig. 2 is a whole constructional diagram of a graphics controller including the image information output circuit according to the invention and of a ferry-electric liquid crystal display panel unit;
Fig. 3 is a diagram showing a data conversion format of a pixel multiplexer 11;
Figs. PA to 4C are diagrams each showing the 8 2~i7~
1 relation between the gradation data of a palette register in a palette RAM and the arrangement of the pixels of an actual display panel;
Figs. PA to 5C are diagrams each showing the relation between the image data from a VIM and the addresses of a palette register;
Fig. 6 is a diagram showing a data conversion format of a pixel selector 14;
Fig. 7 is a diagram showing a construction of a border register and examples of border data and a display pattern;
Fig. 8 is a diagram showing the relation between the position of a border portion on a display screen and the horizontal and vertical blanking signals;
Fig. 9 is a diagram showing an example of a transfer format from an image information output circuit according to the invention; and Fig. AYE and 10B is a diagram showing display modes in a personal computer made by IBM Corporation.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Fig. 2 is a whole constructional diagram of a graphics controller provided on the side of a main body apparatus such as a personal computer or the like as a supply source of image information and a ferry-electric liquid crystal display apparatus. The image information output circuit according to the invention _ 9 _ f '3 1 is provided in the graphics controller in Fig. 2.
The display panel is constructed by arranging 1024 scanning electrodes and 2560 information electrodes like a matrix and sealing a ferroelectric liquid crystal S into a space between two glass plates which were subjected to an orientation process. Scanning lines are connected to a scanning electrode driving circuit. Information lines are connected to an information electrode driving circuit. One pixel has a construction of two bits/pixel in which one pixel is divided into portions having an area ratio of 3:2 as shown in O in the display panel in Fig. 2. The gradation display of four levels per pixel can be performed.
A display controller receives the display informal lion from the image information output circuit according to the invention and controls the scanning electrode driving circuit and the information electrode driving circuit.
The graphics controller comprises: a CPU (central processing unit: hereinafter, referred to as a GCPU) to control the whole display functions; a TRAM (image information storing memory); and a display interface serving as an image information output circuit according to the invention. The graphics controller controls the management of the display information and the whole communication between a host CPU and the display apparatus.
Fig. 1 is a constructional diagram of the display 1 interface according to the invention. The display interface comprises: a gradation conversion section 1 to convert image data from the TRAM into area gradation data; a border register 2 to determine data in the portion out of an effective display area; a scanning line address generator 3; and a data selector 4 for converting the image data into an output format to transfer the image data to the liquid crystal display apparatus. The operation will now be described hereinbelow with reference to the drawings.
(1) Gradation conversion section When explaining the display modes under the graphics environment of the personal computer made by IBM Corporation as an example, the number of constructing bits per pixel of the image data stored in a TRAM 5 differs every display mode in a manner such that it is set to 4 bits/pixel in the mode I and it set to 8 bits/pixel in the mode 13(h). In the embodiment, data of two bytes (16 bits) in the image data stored in the TRAM 5 is always output by a single reading opera-lion (access) for the TRAM 5. Therefore, the number of pixels which are output by a single access to the TRAM 5 differs depending on the display mode. For instance, the image data of four pixels is output in the case of the mode I by the single access. The image data of two pixels is output in the case of the mode 13(h) by the single access. Since a palette RAM
~V~.~J;~
1 12, which will be explained herein later, executes a gradation conversion on a pixel unit basis, the image data which was read out of the TRAM 5 must be led to the palette RAM 12 on a pixel unit basis A pixel multiplexer 11 is provided for this purpose. Fig. 3 shows an image data conversion format of the pixel multiplexer 11. The conversion modes are switched by a command from a GCPU 6 (Fig. 2). For instance, in the display mode I, the image data of four pixels is output from the TRAM 5 by the single access. Therefore, the pixel multiplexer 11 is operated in a conversion mode B. In the conversion mode B, the pixel multiplexer 11 extracts the data of two pixels of VSDo to VSD3 and VSD4 to VSD7 at the first phase from VSDo to VSD15 including data of four pixels which are output from the TRAM 5 and leads as Q0 to Q3 and Q8 to Ill to the palette RAM 12 and a palette RAM 13, respectively. Then, at the second phase, the data of two pixels of VSD8 to VSD11 and VSD12 to VSD15 are led to the palette Rams 12 and 13 as Q0 to Q3 and Q8 to I respectively. As mentioned above, the pixel multiplexer 11 separately leads the image data to the palette Rams 12 and 13 at two phases. On the other hand, in Fig. 3, conversion modes A and C correspond to the cases where the image data format in the TRAM
is set to 8 bits/pixel and 2 bits/pixel, respectively.
In a manner similar to the case of the above 4 bits/pixel, r of 3 1 the image data is led to the palette RAM 12 on a pixel unit basis.
The palette Rams 12 and 13 correspond to a portion for converting the pixel data (color information from the TRAM 5 into the ON/OFF data of the pixels of the actual display panel on a unit pixel basis, respectively.
The conversion from color information in the depth direction> into gradation information in the lateral direction> (area gradation) according to the invention is realized in the above portion. In the embodiment of Fig. 1, two palette Rams have teen arranged in parallel as a countermeasure for a point that the image data conversion rate in the palette RAM is slower than a required transfer rate to the display apparatus. If a processing speed of the palette RAM is sufficiently high, no problem occurs even when only one palette RAM
is used. On the contrary, in the case where a reading speed from the TRAM S or operating speeds of the multi-plexers 11 and 14 are enough high, by increasing the number of palette Rams the processing speed of the conversion system can be raised in correspondence to it.
Each of the palette Rams 12 and 13 is constructed by 256 registers having a length of eight bits which are called palette registers. The gradation information (ON/OFF data of the pixels) corresponding to the color information of the pixels is previously written by the 1 GCPU 6. In the embodiment, the same gradation information is written into the palette Rams 12 and 13. Although the writing and reading operations for each palette RAM can be executed at arbitrary timings, they are ordinarily performed as necessary every horizontal or vertical scanning period.
Figs. PA to 4C are diagrams each showing the relation between the gradation data (ON/OFF data of pixels) of the palette register in the palette RUM and the arrangement of the pixels of the actual display panel. Fig. 4C shows the minimum pixel unit of the display panel used in the embodiment. As mentioned above, one pixel is divided into portions at an area ratio of I and the gradation display of four levels lo is realized by respectively independently driving the two portions. Each of Figs. 4B and PA shows a handling of one pixel in the enlarged display mode. By handling four pixels and sixteen pixels as one pixel in a lump, respectively, the enlarged display of two times and four times can be released The number of gradations which can be displayed also increases to 8 levels and 16 levels. As shown in Figs. PA to 4C, the gradation data of the palette register corresponds to the ON/OFF
data of each pixel on the display panel at a ratio of 1:1.
As shown in Figs. PA to 5C r the pixel data Jo (color information) from the TRAM 5 functions as an 1 address to select the palette register in the palette RAM. For instance, in the case where the pixel data (color information) from the TRAM 5 relates to 4 bits/
pixel, one of the 16 palette registers is selected.
On the other hand, in the case where the pixel data relates to 8 bits/pixel and 2 bits/pixel, one of the 256 palette registers and one of the 4 palette registers are selected. When a certain palette register is selected, the gradation data Pro to PLY and Pro to PHI
stored therein are output and are led to the pixel multiplexer 14 at the next stage.
The pixel multiplexer 14 executes a process to convert the ON/OFF data (data of at most eight bits) of the pixel which is output from the palette RAM into the number of bits which can be displayed in accordance with the enlarged display mode (e.g., lo, 2x, 4x) of the display panel.
Fig. 6 shows conversion modes of the pixel multiplexer 14. For instance, a conversion mode B is selected in the case of executing the enlarged display of two times (2x) by the display panel. At this time, since the number of gradation data which can be obtained per pixel is equal to four bits, only four lower bits IPLo to PLY; Pro to PHI) are extracted from the 8-bit data Pro to PLY and Pro to PHI which are output from the palette Rams 12 and 13, respectively. The extracted eight bits are output as Pucks to PUCKS. On the other - 15 Jo I
1 hand, conversion modes A and C show conversion formats in the enlarged display mode of four times (4x) and in the equal magnification mode (lo), respectively.
As described above, the pixel data (color information) in the TRAM 5 is converted into the gradation data on the display panel by the two multiplexes 11 and 14 and the palette Rams (2) Border register section As mentioned above, in the case where the number of effective pixels of the liquid crystal display apparatus is larger than the resolution of the display mode, some pattern must be displayed in the redundant pixels (border portion) out of the effective display area. The border register 2 has been provided to store data which is output to the border portion. Fig. 7 shows a construction of a border register. In the embodiment, the border register fundamentally comprises one register of a length of eight bits and the eight bits correspond to border data Boo to BD7 (Fig. 7), respectively. On the other hand, the border register 2 has a construction of what is called a double buffer.
Data in the border register 2 can be rewritten at an arbitrary timing from the GCPU 6. The actual border data is set into a border register output stage at a timing of a horizontal or vertical sync signal. A timing to transmit the data set in the border register 2 is controlled by horizontal and vertical blanking signals 1 (Blank and Blank). Fundamentally, as shown in Fig.
8, border data is output when either one of the horizontal and vertical blanking signals is set to the Lo (low) level (in the blanking period). Image data in the effective display area is output in a period of time other than the blanking period. Explanation will be made in detail in conjunction with the operation ox a data selector, which will be explained herein later.
to scanning line address data generator The scanning line address generator 3 has been provided to generate scanning line address data A to Aye of the display panel. The generator 3 comprises a 12-bit binary counter (up to 4096 scanning lines can be selected) which uses as clocks a horizontal sync signal Sync which is input from the display controller on the liquid crystal display apparatus side. The counter can preset a count value (scanning line address data) from the GCPU 6 at an arbitrary timing. Further, a count-up width (how many scanning lines should be jumped and scanned) can be also set.
I Output section to the liquid crystal display apparatus The image data transfer formats to the ferry-electric liquid crystal display apparatus have already been proposed by the same applicant as the present invention in Japanese Patent Application Nos. 61-212184, 63-285141, and the like with respect to a communicating to 1 method to realize a high resolution display in a display element having a memory performance. According to the above propositions, with respect to the transfer of image data, there is used a method whereby the scanning line address information and the image information are serially time-sharingly transferred on the same transmit-soon line for the scanning lines which need to be rewritten.
The data selector 4 has been provided to realize those transfer formats. The data selector 4 time-sharingly switches three kinds of data such as image data Pro to PD7 which were subjected to the gradation conversion, border data Boo to BD7, and scanning line address data A to Aye on the basis of timing control signals from the GCPU 6 and sends the switched data to the display apparatus.
Fig. 9 shows an example of a transfer format from the display interface serving as an image information output circuit according to the invention which conforms with the methods of the above propositions. In Fig.
9, when the horizontal sync signal Sync is input for a period of time when the horizontal blanking signal Blank is set to the Lo level (in the blanking period), the data selector 4 first outputs the scanning line address data A to Aye by two cycles (four clocks (ILK)) by the timing control from the GCPU 6. Then, the border data Boo to BD7 from the border register 2 are continuously 1 transmitted onto communication lines Pucks to PUCKS for a period of time until the Blank is set to the Hi (high) level. When the Bland is set to the Hi level (after completion of the blanking period), the image data Pro to PD7 in the effective display area which were subjected to the gradation conversion are transmitted onto the communication lines Pucks to PUCKS. In Fig. 9, when the information of 640 pixels (1280 dots/640 pixels) has been transferred as image data in the effective display area, the GCPU 6 again sets the Blank Jo the Lo level.
When the Blank is set to the Lo level, the data selector 14 again allows the border data Boo to BD7 to be transmit-ted onto the communication lines Pucks to PUCKS and finishes the transfer of the data (640 pixels) of all of the pixels.
Fig. 9 shows transfer timings in the horizontal scanning direction. The data selector 4 also similarly distinguishes the border area and the effective display area by using the vertical blanking signal with respect to the vertical scanning direction and switches the output data.
Further, by controlling the timings of the Blank and Blank, the effective display area can be also displayed at an arbitrary position on the display screen.
As described above, in the display apparatus using the ferroelectric liquid crystal or the like having the bistability (memory performance), there is provided Jo , 1 an image information output circuit having: a first multiplexer to lead image data which is read out of an image memory to the next stage every pixel; palette Rams for outputting ON/OFF data of predetermined pixels on the basis of data which is output from the first multiplexer; and a second multiplexer to convert the data from the palette Rams into an output format to transfer it to a display apparatus. The converting process of the image data and the process of an area (frame portion) out of the effective display area are executed in accordance with a display mode request from a main body CPU. Thus, display screens in various display modes which have conventionally been used in a CRT or the like can be displayed on the display apparatus using a binary display element such as a ferroelectric liquid crystal display apparatus or the like without losing the image.
I
In the case where the display is executed in various display modes which have conventionally been used in the CRT or the like by using a display apparatus such as a ferroelectric liquid crystal display apparatus or the like of a high resolution (Lowe x Lowe pixels or more), the redundant pixels (the pixels remain) occur on the side of the liquid crystal display apparatus because the resolution in the CRT display mode is lower (an amount of display information is smaller) than the effective number of pixels (resolution) of the liquid crystal display apparatus. In such a case, the enlarged display can be also executed by simultaneously driving a plurality of electrodes in the vertical and lateral directions in a lump on the side of the liquid crystal display apparatus. For instance, in the case of displaying the screen in the mode Do (320 x 200 pixels) by the ferroelectric liquid crystal display apparatus of 1280 x 1024 pixels or the like, the enlarged display from one time to four times can be realized. Even if such an enlarged display is used, redundant pixels also 25 occur in the portion out of the effective display area -I
depending on the relation between the number of effective pixels (resolution) of the liquid crystal display apparatus 1 and the resolution in the display mode.
Therefore, it is necessary to execute a proper process to the portion border portion) of the redundant pixels out of the effective display area.
In the case of displaying in the display mode of a low resolution by the CRT, the portion to which an electron beam is not irradiated is held black (dark) by thinning out and scanning the fluorescent display surface by reducing the scanning frequency of the electron beam. however, in the case of the ferroelectric liquid crystal display apparatus, if no image data is input, a state of the pixel is not assured (bright or dark, on or off). Therefore, it is necessary to also input data into the portion of the redundant pixels and to drive and control.
SUMMARY OF THE INVENTION
The present invention is made to eliminate the foregoing problems which cannot be realized by an image information output circuit which is used in a conventional CRT or the like. It is an object of the invention to realize an image information output circuit for displaying the screens in various display modes which have been used in a conventional CRT or the like onto a display apparatus using a binary display element such as a ferroelectric liquid crystal display apparatus or the like without losing image data.
- 7 - ?,~
1 Another object of the invention is to realize an image information output circuit of a display apparatus using a ferroelectric liquid crystal or the like having a bistability [memory performance), comprising: a first 5 multiplexer for leading image data which is read out of an image memory to the next stage every pixel data;
palette Rams each for outputting pixel data on the hasps of the data which is output from the first multiplexer;
and a second multiplexer for converting the pixel data from the palette RAM into an output format to transfer to the display apparatus, wherein a converting process of the image data and a process for an area frame portion) out of the effective display area are executed in accordance with a display mode request from the main body CPU, thereby making it possible to cope with a number of various display modes.
BRIEF DESCRIPTION OF TIE DRAWINGS
Fig. 1 is a constructional diagram of an image information output circuit according to the invention;
Fig. 2 is a whole constructional diagram of a graphics controller including the image information output circuit according to the invention and of a ferry-electric liquid crystal display panel unit;
Fig. 3 is a diagram showing a data conversion format of a pixel multiplexer 11;
Figs. PA to 4C are diagrams each showing the 8 2~i7~
1 relation between the gradation data of a palette register in a palette RAM and the arrangement of the pixels of an actual display panel;
Figs. PA to 5C are diagrams each showing the relation between the image data from a VIM and the addresses of a palette register;
Fig. 6 is a diagram showing a data conversion format of a pixel selector 14;
Fig. 7 is a diagram showing a construction of a border register and examples of border data and a display pattern;
Fig. 8 is a diagram showing the relation between the position of a border portion on a display screen and the horizontal and vertical blanking signals;
Fig. 9 is a diagram showing an example of a transfer format from an image information output circuit according to the invention; and Fig. AYE and 10B is a diagram showing display modes in a personal computer made by IBM Corporation.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Fig. 2 is a whole constructional diagram of a graphics controller provided on the side of a main body apparatus such as a personal computer or the like as a supply source of image information and a ferry-electric liquid crystal display apparatus. The image information output circuit according to the invention _ 9 _ f '3 1 is provided in the graphics controller in Fig. 2.
The display panel is constructed by arranging 1024 scanning electrodes and 2560 information electrodes like a matrix and sealing a ferroelectric liquid crystal S into a space between two glass plates which were subjected to an orientation process. Scanning lines are connected to a scanning electrode driving circuit. Information lines are connected to an information electrode driving circuit. One pixel has a construction of two bits/pixel in which one pixel is divided into portions having an area ratio of 3:2 as shown in O in the display panel in Fig. 2. The gradation display of four levels per pixel can be performed.
A display controller receives the display informal lion from the image information output circuit according to the invention and controls the scanning electrode driving circuit and the information electrode driving circuit.
The graphics controller comprises: a CPU (central processing unit: hereinafter, referred to as a GCPU) to control the whole display functions; a TRAM (image information storing memory); and a display interface serving as an image information output circuit according to the invention. The graphics controller controls the management of the display information and the whole communication between a host CPU and the display apparatus.
Fig. 1 is a constructional diagram of the display 1 interface according to the invention. The display interface comprises: a gradation conversion section 1 to convert image data from the TRAM into area gradation data; a border register 2 to determine data in the portion out of an effective display area; a scanning line address generator 3; and a data selector 4 for converting the image data into an output format to transfer the image data to the liquid crystal display apparatus. The operation will now be described hereinbelow with reference to the drawings.
(1) Gradation conversion section When explaining the display modes under the graphics environment of the personal computer made by IBM Corporation as an example, the number of constructing bits per pixel of the image data stored in a TRAM 5 differs every display mode in a manner such that it is set to 4 bits/pixel in the mode I and it set to 8 bits/pixel in the mode 13(h). In the embodiment, data of two bytes (16 bits) in the image data stored in the TRAM 5 is always output by a single reading opera-lion (access) for the TRAM 5. Therefore, the number of pixels which are output by a single access to the TRAM 5 differs depending on the display mode. For instance, the image data of four pixels is output in the case of the mode I by the single access. The image data of two pixels is output in the case of the mode 13(h) by the single access. Since a palette RAM
~V~.~J;~
1 12, which will be explained herein later, executes a gradation conversion on a pixel unit basis, the image data which was read out of the TRAM 5 must be led to the palette RAM 12 on a pixel unit basis A pixel multiplexer 11 is provided for this purpose. Fig. 3 shows an image data conversion format of the pixel multiplexer 11. The conversion modes are switched by a command from a GCPU 6 (Fig. 2). For instance, in the display mode I, the image data of four pixels is output from the TRAM 5 by the single access. Therefore, the pixel multiplexer 11 is operated in a conversion mode B. In the conversion mode B, the pixel multiplexer 11 extracts the data of two pixels of VSDo to VSD3 and VSD4 to VSD7 at the first phase from VSDo to VSD15 including data of four pixels which are output from the TRAM 5 and leads as Q0 to Q3 and Q8 to Ill to the palette RAM 12 and a palette RAM 13, respectively. Then, at the second phase, the data of two pixels of VSD8 to VSD11 and VSD12 to VSD15 are led to the palette Rams 12 and 13 as Q0 to Q3 and Q8 to I respectively. As mentioned above, the pixel multiplexer 11 separately leads the image data to the palette Rams 12 and 13 at two phases. On the other hand, in Fig. 3, conversion modes A and C correspond to the cases where the image data format in the TRAM
is set to 8 bits/pixel and 2 bits/pixel, respectively.
In a manner similar to the case of the above 4 bits/pixel, r of 3 1 the image data is led to the palette RAM 12 on a pixel unit basis.
The palette Rams 12 and 13 correspond to a portion for converting the pixel data (color information from the TRAM 5 into the ON/OFF data of the pixels of the actual display panel on a unit pixel basis, respectively.
The conversion from color information in the depth direction> into gradation information in the lateral direction> (area gradation) according to the invention is realized in the above portion. In the embodiment of Fig. 1, two palette Rams have teen arranged in parallel as a countermeasure for a point that the image data conversion rate in the palette RAM is slower than a required transfer rate to the display apparatus. If a processing speed of the palette RAM is sufficiently high, no problem occurs even when only one palette RAM
is used. On the contrary, in the case where a reading speed from the TRAM S or operating speeds of the multi-plexers 11 and 14 are enough high, by increasing the number of palette Rams the processing speed of the conversion system can be raised in correspondence to it.
Each of the palette Rams 12 and 13 is constructed by 256 registers having a length of eight bits which are called palette registers. The gradation information (ON/OFF data of the pixels) corresponding to the color information of the pixels is previously written by the 1 GCPU 6. In the embodiment, the same gradation information is written into the palette Rams 12 and 13. Although the writing and reading operations for each palette RAM can be executed at arbitrary timings, they are ordinarily performed as necessary every horizontal or vertical scanning period.
Figs. PA to 4C are diagrams each showing the relation between the gradation data (ON/OFF data of pixels) of the palette register in the palette RUM and the arrangement of the pixels of the actual display panel. Fig. 4C shows the minimum pixel unit of the display panel used in the embodiment. As mentioned above, one pixel is divided into portions at an area ratio of I and the gradation display of four levels lo is realized by respectively independently driving the two portions. Each of Figs. 4B and PA shows a handling of one pixel in the enlarged display mode. By handling four pixels and sixteen pixels as one pixel in a lump, respectively, the enlarged display of two times and four times can be released The number of gradations which can be displayed also increases to 8 levels and 16 levels. As shown in Figs. PA to 4C, the gradation data of the palette register corresponds to the ON/OFF
data of each pixel on the display panel at a ratio of 1:1.
As shown in Figs. PA to 5C r the pixel data Jo (color information) from the TRAM 5 functions as an 1 address to select the palette register in the palette RAM. For instance, in the case where the pixel data (color information) from the TRAM 5 relates to 4 bits/
pixel, one of the 16 palette registers is selected.
On the other hand, in the case where the pixel data relates to 8 bits/pixel and 2 bits/pixel, one of the 256 palette registers and one of the 4 palette registers are selected. When a certain palette register is selected, the gradation data Pro to PLY and Pro to PHI
stored therein are output and are led to the pixel multiplexer 14 at the next stage.
The pixel multiplexer 14 executes a process to convert the ON/OFF data (data of at most eight bits) of the pixel which is output from the palette RAM into the number of bits which can be displayed in accordance with the enlarged display mode (e.g., lo, 2x, 4x) of the display panel.
Fig. 6 shows conversion modes of the pixel multiplexer 14. For instance, a conversion mode B is selected in the case of executing the enlarged display of two times (2x) by the display panel. At this time, since the number of gradation data which can be obtained per pixel is equal to four bits, only four lower bits IPLo to PLY; Pro to PHI) are extracted from the 8-bit data Pro to PLY and Pro to PHI which are output from the palette Rams 12 and 13, respectively. The extracted eight bits are output as Pucks to PUCKS. On the other - 15 Jo I
1 hand, conversion modes A and C show conversion formats in the enlarged display mode of four times (4x) and in the equal magnification mode (lo), respectively.
As described above, the pixel data (color information) in the TRAM 5 is converted into the gradation data on the display panel by the two multiplexes 11 and 14 and the palette Rams (2) Border register section As mentioned above, in the case where the number of effective pixels of the liquid crystal display apparatus is larger than the resolution of the display mode, some pattern must be displayed in the redundant pixels (border portion) out of the effective display area. The border register 2 has been provided to store data which is output to the border portion. Fig. 7 shows a construction of a border register. In the embodiment, the border register fundamentally comprises one register of a length of eight bits and the eight bits correspond to border data Boo to BD7 (Fig. 7), respectively. On the other hand, the border register 2 has a construction of what is called a double buffer.
Data in the border register 2 can be rewritten at an arbitrary timing from the GCPU 6. The actual border data is set into a border register output stage at a timing of a horizontal or vertical sync signal. A timing to transmit the data set in the border register 2 is controlled by horizontal and vertical blanking signals 1 (Blank and Blank). Fundamentally, as shown in Fig.
8, border data is output when either one of the horizontal and vertical blanking signals is set to the Lo (low) level (in the blanking period). Image data in the effective display area is output in a period of time other than the blanking period. Explanation will be made in detail in conjunction with the operation ox a data selector, which will be explained herein later.
to scanning line address data generator The scanning line address generator 3 has been provided to generate scanning line address data A to Aye of the display panel. The generator 3 comprises a 12-bit binary counter (up to 4096 scanning lines can be selected) which uses as clocks a horizontal sync signal Sync which is input from the display controller on the liquid crystal display apparatus side. The counter can preset a count value (scanning line address data) from the GCPU 6 at an arbitrary timing. Further, a count-up width (how many scanning lines should be jumped and scanned) can be also set.
I Output section to the liquid crystal display apparatus The image data transfer formats to the ferry-electric liquid crystal display apparatus have already been proposed by the same applicant as the present invention in Japanese Patent Application Nos. 61-212184, 63-285141, and the like with respect to a communicating to 1 method to realize a high resolution display in a display element having a memory performance. According to the above propositions, with respect to the transfer of image data, there is used a method whereby the scanning line address information and the image information are serially time-sharingly transferred on the same transmit-soon line for the scanning lines which need to be rewritten.
The data selector 4 has been provided to realize those transfer formats. The data selector 4 time-sharingly switches three kinds of data such as image data Pro to PD7 which were subjected to the gradation conversion, border data Boo to BD7, and scanning line address data A to Aye on the basis of timing control signals from the GCPU 6 and sends the switched data to the display apparatus.
Fig. 9 shows an example of a transfer format from the display interface serving as an image information output circuit according to the invention which conforms with the methods of the above propositions. In Fig.
9, when the horizontal sync signal Sync is input for a period of time when the horizontal blanking signal Blank is set to the Lo level (in the blanking period), the data selector 4 first outputs the scanning line address data A to Aye by two cycles (four clocks (ILK)) by the timing control from the GCPU 6. Then, the border data Boo to BD7 from the border register 2 are continuously 1 transmitted onto communication lines Pucks to PUCKS for a period of time until the Blank is set to the Hi (high) level. When the Bland is set to the Hi level (after completion of the blanking period), the image data Pro to PD7 in the effective display area which were subjected to the gradation conversion are transmitted onto the communication lines Pucks to PUCKS. In Fig. 9, when the information of 640 pixels (1280 dots/640 pixels) has been transferred as image data in the effective display area, the GCPU 6 again sets the Blank Jo the Lo level.
When the Blank is set to the Lo level, the data selector 14 again allows the border data Boo to BD7 to be transmit-ted onto the communication lines Pucks to PUCKS and finishes the transfer of the data (640 pixels) of all of the pixels.
Fig. 9 shows transfer timings in the horizontal scanning direction. The data selector 4 also similarly distinguishes the border area and the effective display area by using the vertical blanking signal with respect to the vertical scanning direction and switches the output data.
Further, by controlling the timings of the Blank and Blank, the effective display area can be also displayed at an arbitrary position on the display screen.
As described above, in the display apparatus using the ferroelectric liquid crystal or the like having the bistability (memory performance), there is provided Jo , 1 an image information output circuit having: a first multiplexer to lead image data which is read out of an image memory to the next stage every pixel; palette Rams for outputting ON/OFF data of predetermined pixels on the basis of data which is output from the first multiplexer; and a second multiplexer to convert the data from the palette Rams into an output format to transfer it to a display apparatus. The converting process of the image data and the process of an area (frame portion) out of the effective display area are executed in accordance with a display mode request from a main body CPU. Thus, display screens in various display modes which have conventionally been used in a CRT or the like can be displayed on the display apparatus using a binary display element such as a ferroelectric liquid crystal display apparatus or the like without losing the image.
I
Claims (12)
1. A display apparatus which uses a display panel using a liquid crystal having a memory performance and can display image data in a plurality of display modes in which the number of pixels, display color, minimum pixel unit, and the like respectively differ, comprising:
memory means for storing the image data;
pixel data output means for outputting the image data stored in the memory means pixel data by pixel data;
converting means for converting the pixel data which was output by the pixel data output means into binary data which is displayed on the display panel;
display data output means for converting the binary data which was converted by the converting means into display data corresponding to the display mode and outputting; and display control means for allowing the image data which was output by the display data output means to be displayed on the display panel.
memory means for storing the image data;
pixel data output means for outputting the image data stored in the memory means pixel data by pixel data;
converting means for converting the pixel data which was output by the pixel data output means into binary data which is displayed on the display panel;
display data output means for converting the binary data which was converted by the converting means into display data corresponding to the display mode and outputting; and display control means for allowing the image data which was output by the display data output means to be displayed on the display panel.
2. A display apparatus according to claim 1, wherein the pixel data output means is a multiplexer.
3. A display apparatus according to claim 1, wherein the converting means is an RAM (random access memory) in which binary data has been stored.
4. A display apparatus according to claim 1, wherein the converting means is constructed by a plurality of RAMs (random access memories) in each of which binary data has been stored.
5. A display apparatus according to claim 1, further having frame display means for displaying desired frame image data to an area out of an effective display area of the image data which was displayed on the display panel.
6. A display apparatus according to claim 5, wherein the frame display means outputs and displays the frame image data of the area out of the effective display area within horizontal and vertical blanking periods of time of the image data which is displayed in the effective display area.
7. A display apparatus according to claim 1, wherein the display data output means is a multiplexer.
8. A display apparatus according to claim 1, wherein the liquid crystal having the memory performance is a ferroelectric liquid crystal.
9. A display apparatus using a display panel using a liquid crystal having a memory performance, comprising:
frame display means for displaying frame image data to an area out of an effective display area to display image data of the display panel, wherein the frame display means outputs and displays the frame image data within horizontal and vertical blanking periods of time of the image data.
frame display means for displaying frame image data to an area out of an effective display area to display image data of the display panel, wherein the frame display means outputs and displays the frame image data within horizontal and vertical blanking periods of time of the image data.
10. A display apparatus according to claim 9, wherein the liquid crystal having the memory performance is a ferroelectric liquid crystal.
11. A display apparatus according to claim 9, wherein the frame display means sets the frame image data of the area out of the effective display area within one horizontal scanning period or one vertical display period of time of the image data.
12. A display apparatus according to claim 9, wherein the frame display means further has memory means for storing the frame image data which is displayed to the area out of the effective display area.
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|---|---|---|---|
| JP01-261297 | 1989-10-06 | ||
| JP1261297A JP2877381B2 (en) | 1989-10-06 | 1989-10-06 | Display device and display method |
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| CA2027043A1 CA2027043A1 (en) | 1991-04-07 |
| CA2027043C true CA2027043C (en) | 1995-02-14 |
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| JP3126360B2 (en) * | 1989-09-01 | 2001-01-22 | キヤノン株式会社 | Display system and display control method thereof |
| JPH0455890A (en) * | 1990-06-25 | 1992-02-24 | Canon Inc | Image data controller and display system |
| US5420603A (en) * | 1991-02-20 | 1995-05-30 | Canon Kabushiki Kaisha | Display apparatus |
| JP3143493B2 (en) * | 1991-06-21 | 2001-03-07 | キヤノン株式会社 | Display control device |
| EP0606993B1 (en) | 1993-01-11 | 2002-07-24 | Canon Kabushiki Kaisha | Colour gamut clipping |
| AU674037B2 (en) * | 1993-01-11 | 1996-12-05 | Canon Kabushiki Kaisha | Colour gamut clipping |
| AU679320B2 (en) * | 1994-03-11 | 1997-06-26 | Canon Kabushiki Kaisha | Computer display system controller |
| ES2114812B1 (en) * | 1996-03-25 | 1999-02-16 | Desarrollos Electronicos Proym | APPARATUS TO PROVIDE PRE-PROGRAMMED INFORMATION. |
| JPH09325741A (en) * | 1996-05-31 | 1997-12-16 | Sony Corp | Picture display system |
| WO1998010405A1 (en) * | 1996-09-03 | 1998-03-12 | United Technologies Automotive, Inc. | Method of controlling display image shading depending on image resolution |
| US5758135A (en) * | 1996-09-24 | 1998-05-26 | Seiko Epson Corporation | System and method for fast clocking a digital display in a multiple concurrent display system |
| JP2982722B2 (en) * | 1996-12-04 | 1999-11-29 | 日本電気株式会社 | Video display device |
| JP3572473B2 (en) | 1997-01-30 | 2004-10-06 | 株式会社ルネサステクノロジ | Liquid crystal display control device |
| GB0000715D0 (en) * | 2000-01-14 | 2000-03-08 | Micropix Technologies Limited | A liquid crystal display |
| WO2001091098A1 (en) * | 2000-05-24 | 2001-11-29 | Hitachi, Ltd. | Color/black-and-white switchable portable terminal and display device |
| CN111175562A (en) * | 2019-12-31 | 2020-05-19 | 常州瑞莱博自动化科技有限公司 | Bistable liquid crystal current indicator |
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| JPS5731268A (en) * | 1980-07-31 | 1982-02-19 | Matsushita Electric Ind Co Ltd | Frame signal generator |
| JPS6151554U (en) * | 1984-09-05 | 1986-04-07 | ||
| JPS6167024A (en) * | 1984-09-10 | 1986-04-07 | Canon Inc | Driving method of liquid crystal element |
| JPS61213896A (en) * | 1985-03-19 | 1986-09-22 | 株式会社 アスキ− | Display controller |
| JP2535324B2 (en) * | 1985-05-13 | 1996-09-18 | キヤノン株式会社 | Display controller |
| JPS6334593A (en) * | 1986-07-30 | 1988-02-15 | ホシデン株式会社 | Multi-contrast display |
| EP0295691B1 (en) * | 1987-06-19 | 1994-11-23 | Kabushiki Kaisha Toshiba | Display mode switching system for plasma display apparatus |
| JP2797435B2 (en) * | 1989-05-26 | 1998-09-17 | ヤマハ株式会社 | Display controller |
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- 1990-10-04 DK DK90310846.2T patent/DK0421772T3/en active
- 1990-10-04 ES ES90310846T patent/ES2081942T3/en not_active Expired - Lifetime
- 1990-10-04 EP EP90310846A patent/EP0421772B1/en not_active Expired - Lifetime
- 1990-10-04 DE DE69024448T patent/DE69024448T2/en not_active Expired - Fee Related
- 1990-10-05 AU AU63858/90A patent/AU638754B2/en not_active Ceased
- 1990-10-05 CA CA002027043A patent/CA2027043C/en not_active Expired - Lifetime
- 1990-10-06 KR KR1019900015904A patent/KR940002237B1/en not_active IP Right Cessation
-
1993
- 1993-11-17 KR KR1019930024475A patent/KR940002345B1/en not_active IP Right Cessation
-
1996
- 1996-02-07 GR GR960400330T patent/GR3018924T3/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| EP0421772A3 (en) | 1992-11-19 |
| AU6385890A (en) | 1991-04-11 |
| AU638754B2 (en) | 1993-07-08 |
| KR940002345B1 (en) | 1994-03-23 |
| DE69024448D1 (en) | 1996-02-08 |
| JPH03123386A (en) | 1991-05-27 |
| EP0421772B1 (en) | 1995-12-27 |
| DE69024448T2 (en) | 1996-05-23 |
| EP0421772A2 (en) | 1991-04-10 |
| CA2027043A1 (en) | 1991-04-07 |
| KR910008602A (en) | 1991-05-31 |
| ES2081942T3 (en) | 1996-03-16 |
| GR3018924T3 (en) | 1996-05-31 |
| KR940002237B1 (en) | 1994-03-19 |
| ATE132287T1 (en) | 1996-01-15 |
| DK0421772T3 (en) | 1996-01-29 |
| JP2877381B2 (en) | 1999-03-31 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed | ||
| MKEC | Expiry (correction) |
Effective date: 20121202 |