KR940002237B1 - Display apparatus - Google Patents

Abstract

There is provided a display apparatus which uses a display panel using a liquid crystal having a bistability or a memory performance such as a ferroelectric liquid crystal and can display image data in various display modes in which the number of pixels (resolution), display color, minimum pixel unit, and the like respectively differ. The display apparatus comprises: a memory to store the image data; a pixel data output circuit to output the image data stored in the memory every pixel data; a converter to convert the pixel data which was output from the pixel data output circuit into binary data which is displayed on the display panel; a display data output circuit for converting the binary data converted by the converter into the display data corresponding to the display modc and outputting; and a display controller for allowing the image data which was output by the display data output circuit to be displayed on the display panel. A multiplexer is used as a pixel data output circuit. An RAM in which binary data has been stored is used as a converter.

Description

Display

1 is a configuration diagram of an image information output circuit according to the present invention.

2 is an overall configuration diagram of a graphics controller and a strong dielectric liquid crystal display panel unit including the image information output circuit according to the present invention.

3 is a diagram showing a data conversion format of the pixel multiplexer 11. FIG.

4A to 4C are diagrams showing the relationship between the gradation data of the pallet registers in the pallet RAM and the pixel arrangement of the actual display panel.

5 is a diagram showing a relation between image data from a VRAM and an address of a pallet register.

6 shows a data conversion format of the pixel selector 14. FIG.

7 is a diagram illustrating an example of the configuration of the boundary register and boundary data and display patterns.

Fig. 8 is a diagram showing the relationship between the position of the boundary portion on the display screen and the horizontal and vertical blanking signals.

9 is a diagram showing an example of a transmission format from an image information output circuit according to the present invention.

Fig. 10 is a diagram showing a display mode in a personal computer of IBM Corporation.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and to be described in detail, for example, it is applied to a display device using a binarized display device having phase stability (memory) with respect to an electric field, such as a ferroelectric liquid crystal display device. The present invention relates to an output circuit of image information suitable for the following. In recent years, displays such as personal computers and workstations have rapidly developed large screens and high resolution, and there are many display modes including the conventional ones. For example, the graphics environment of the personal computer of the commonly used International Businness Machines Corp. (IBM) is 10 such as Color Graphic Adapter (CGA), Enhanced Graphic Adapter (EGA), and Video Graphlc Adapter (VGA). There are various display modes, and the resolution and the number of colors that can be displayed are different.

10 is his list.

(1) About display color; As can be seen from FIG. 10, the number of components (bits / pixel) per pixel varies with each display mode, and the storage format in the image memory (VRAM) is also different. Naturally, a multicolor display is possible for a mode having a large number of configuration bits per pixel.

Here, as an example, the display mode 13 (h) (VGA) capable of the most multi-color display in the graphics environment of the IBM personal computer is as follows.

First, when an address in the VRAM is accessed, the image data (bit / pixel mode 13 (h)) in the VRAM serves as an address for selecting a color register in the color palette in which color information is stored in advance. In the case of VGA, the color palette has 256 color registers of 18 bits (6 bits each of R, G, and B), and color information is stored in this color register. When one color register is selected from 256 by image data from the VRAM, the color data of R, G, and B, each of which is composed of 6 bits, is read out and derived into a D-A converter in the same color palette. D-A converters installed in R, G, and B each convert 6-bit color data into analog signals and send them to the display (CRT).

Such a method of outputting color information (color pallet + analog output) can be realized even if the amount of data in the VRAM is not large, or even if the data in the VRAM is not changed and input by changing the data in the color register. There are advantages in that the color on the screen can be changed, and the number of connections to the display can be reduced, and this is the standard method mainly used in personal computers.

(2) about resolution; In Fig. 10, the resolution is also different for each display mode, for example, 320x200 pixels (pixels) for mode D (h) and 640x480 pixels for mode 12 (h). It is conventionally relatively difficult to support all of these various display modes with one display (CRT), and it is common to define (limit) displayable display modes. In addition, some automatic tracking type CRTs called "multi-scan" or "multi-sync" use a method of switching the scanning frequency of the electron beam according to each display mode in order to support a relatively wide display mode. . For this reason, when displaying in a display mode with less display information (resolution or low), characters and numbers are often displayed without their teeth.

When various display modes having different display colors and resolutions as described above are applied to a display device using a liquid crystal having a memory property of ferroelectric liquid crystal and displayed, unlike the case of displaying on a CRT or the like, the following should be considered. .

(1) About display color; In the case of a display device using a binary display device represented by a ferroelectric liquid crystal display device, such as a CRT, expressing the gray scale analogously (depth direction) within one pixel (pixel), that is, three-dimensional Gradation display is difficult. When gray scale display is performed by the binarized display element, it is common to perform a process of expanding the gray scale (color) data in the depth direction in the horizontal direction (the spreading direction), and to display (area gray scale) two-dimensionally. Therefore, in the case of displaying various display modes having different display colors with a ferroelectric liquid crystal display device or the like, depending on the display mode, the gradation (color) data of the depth direction originally for the CRT is changed according to the arrangement of the pixels of the actual display device. To grayscale data in the direction of spreading).

(2) Regarding the resolution, the display device such as a ferroelectric liquid crystal display device having a high resolution (1000 × 1000 pixels or more) is displayed in various display modes conventionally used in CRTs, etc. Since the resolution of the CRT display mode is low (the display information is small), the remaining pixels (remaining pixels) are generated on the liquid crystal display side. In such a case, magnified display can be performed by simultaneously driving a plurality of vertical and horizontal electrodes together on the liquid crystal display side.

For example, when a screen of the mode D (h) (320x200 pixels) is displayed by a ferroelectric liquid crystal display device such as 1280x1024 pixels, an enlarged display of 1 to 4 times can be realized. Even when such enlarged display is employed, the remaining pixels are generated outside the effective display area depending on the relationship between the effective pixel number (resolution) of the liquid crystal display device and the resolution of the display mode.

Therefore, it is necessary to appropriately process the portion (boundary portion) of the remaining pixels of the effective display area.

When a low resolution display mode is displayed by CRT, the scanning frequency of the electron beam is lowered to scan the fluorescent display surface thinly, so that the unbeamed portion remains black (dark). However, in the case of a ferroelectric liquid crystal display device, the state of the pixel is not guaranteed without input of image data (light or dark, ON or OFF). For this reason, it is necessary to drive data by inputting data to the remaining pixel parts.

SUMMARY OF THE INVENTION The present invention has been made to eliminate the above-mentioned problems that cannot be realized in conventional image information output circuits used in CRTs. An image information output circuit for displaying without loss of image data on a display device using a digitizing display element is realized.

Still another object of the present invention is to provide a display device using a ferroelectric liquid crystal having bistable (memory) characteristics, comprising: a first multiplexer for guiding image data read from an image memory to a next step by one pixel data; Based on the data output from the multiplexer, a pallet RAM for outputting pixel data, and a second multiplexer for converting the pixel data from the pallet RAM to an output format for transferring to the display device. The image information output circuit of the display device which can adapt to various various display modes is realized by performing the conversion process of the image data and the processing of the area (frame portion) outside the effective display area in accordance with the display mode request.

2 is an overall configuration diagram of a graphics controller and a ferroelectric liquid crystal display device provided on a main body device such as a personal computer that is a source of image information. The image information output circuit according to the present invention is provided in the graphics controller in FIG.

In the display panel, 1024 scan electrodes and 2560 information electrodes are arranged on a matrix, and ferroelectric liquid crystal is encapsulated in two glass plates subjected to an alignment process. The scan line is a scan electrode driver circuit, and the information line is an information electrode driver circuit. Each is connected. In addition, one pixel (pixel) has a 2-bit / pixel configuration divided by an area ratio of 3: 2 as indicated by (circle) in the display panel of FIG. 2, and four levels of gradation display per pixel are possible.

The display controller receives display information from the image information output circuit according to the present invention and controls the scan electrode driving circuit and the information electrode driving circuit.

The graphics controller is composed of a CPU (central processing unit, hereinafter referred to as GCPU) and VRAM (image information memory) and a display interface which is an image information output circuit according to the present invention. Management of display information between devices and overall communication are controlled.

1 is a configuration diagram of a display interface according to the present invention. The circuit includes a gray scale converter 1 for converting image data from the VRAM into area grayscale data, a boundary register 2 for determining data outside the effective display area, a scan line address generator 3, and a liquid crystal display device. It consists of a data selector 4 which converts it into an output format for transferring data. The operation will be described below with reference to the drawings.

(1) tone conversion unit

The image data stored in the VRAM 5 is 4 bits / pixel in the mode (3) (h), 8 bits / pixel in the mode (13) (h), for example, in the display mode under the IBM graphics environment. In this way, the number of configuration bits per pixel (pixel) is different for each display mode. In this embodiment, the image data stored in the VRAM 5 is always configured to output two bytes (16 bits) in one read operation (access) to the VRAM 5. For this reason, the number of pixels output in one access to the VRAM 5 varies depending on the display mode, for example, four pixels in the mode 3 (h) and two pixels in the mode 13 (h). Minutes are output in one access. Since the pallet RAM 12 described later performs gradation conversion in units of one pixel, image data read out from the VRAM 5 must be guided to the pallet RAM 12 in units of one pixel.

For this reason, the pixel multiplexer 11 is provided. FIG. 3 shows the image data conversion format of the pixel multiplexer 11, and switching of these conversion modes is performed by an instruction from the GCPU 6 (FIG. 2). For example, in the display mode 3 (h), since four pixels (4 bits / pixel) of image data are output from the VRAM in one access, the pixel multiplexer 11 operates in the conversion mode B. FIG. In this conversion mode (B), the pixel multiplexer 11 has 2 of VSD ₀ to ₃ and VSD _{4 to 7} in the first phase from VSD ₀ to ₁₅ including 4 pixels of data output from the VRAM 5. each Q _0~3 extracts the data of the pixel, and a Q _8~11 induces a palette RAM (12), palette RAM (13). This time, the subsequent second data of VSD _8~1l, two pixels of the VSD _12~l5 in phase Q _0~3, and Q with _8~11 palette RAM (12), palette RAM (13), each of the To the. Next, this time in a second phase by a VSD _8~11 induces a palette RAM (12), palette RAM (13). Each Q _0~3, and Q with _8~11 induces a palette RAM (12), palette RAM (13). In this way, the multiplexer 11 divides the image data into two phases and guides the image data to the pallet RAM units 12 and 13. In Fig. 3, the conversion modes A and C are conversion modes in the case where the image data formats in the VRAM are 8 bits / pixel and 2 bits / pixel, respectively, and the image data is 1 as in the case of the 4 bits / pixel. It is comprised so that it may guide to the pallet RAM 12 by a pixel unit.

The pallet RAMs 12 and 13 convert the pixel data (color information) from the VRAM 5 into ON / OFF data of the pixels of the actual display panel in units of one pixel each. The conversion from <color information in the depth direction> to <gradation information in the horizontal direction> (area gradation) according to the present invention is realized here. In the embodiment of FIG. 1, two pallet RAMs are provided in parallel, but this is to cope with a delay compared to the transfer speed from the pallet RAM to the display device which requires conversion of image data. If the processing speed is fast enough, there is no problem at all.

On the contrary, in the case where the read speed of the VRAM 5 and the operation speed of the multiplexer 11.14 are sufficiently fast, it is also possible to increase the processing speed as a conversion system by increasing the number of pallet RAMs accordingly.

The pallet RAMs 12 and 13 are each constituted by 256 registers of 8-bit length called pallet registers, and the gray scale information (pixel ON / OFF data) corresponding to the color information of the pixels is pre-arranged by the GCPU 6 in advance. Is entered. In this embodiment, the same RAM information is input to the pallet RAMs 12 and 13.

In addition, although the input operation and reading operation in each pallet RAM can be performed by arbitrary timing, it is normally performed as needed between every horizontal syringe or every vertical syringe as needed.

4 (a) to 4 (c) show the relationship between the gradation data (the ON / OFF data of the pixels) of the pie register in the pallet RAM and the actual pixel arrangement of the display panel.

4 (c) shows a minimization unit of the display panel used in this embodiment.

As described above, one pixel is divided into an area ratio of 3: 2, and each of them is driven independently to realize four levels of gradation display.

4 (b) and 4 (a) show handling of one pixel in the enlarged display mode.

By treating four pixels and 16 pixels together as one pixel, the number of gray levels that can be displayed is increased to eight levels and sixteen levels at the same time.

As shown in Figs. 4 (a) to 4 (c), the gray scale data of the pallet register corresponds to 1: 1 with ON / OFF data of each pixel on the display panel.

As shown in FIG. 5, the pixel data (color information) from the VRAM 5 serves as an address for selecting a pallet register of the pallet RAM.

For example, when the pixel data (color information) from the VRAM 5 is 4 bits / pixel, one of the 16 pallet registers is selected. If the pixel data is 8 bits / pixel and 2 bits / pixel, one of 256 and four pallet registers is selected, respectively.

When any pallet register is selected, the gradation data PL _0-7 and PH _0-7 stored therein are output, and are guide | induced to the pixel multiplexer 14 of a next step.

The pixel multiplexer l4 converts ON / OFF data (up to 8 bits of data) of pixels output from the pallet RAM into the number of bits that can be displayed according to the enlarged display mode (eg, 1X, 2X, 4X) of the display panel. The process is performed.

6 shows the conversion mode of the pixel multiplexer 14.

For example, when performing 2x magnification display on the display panel, the conversion mode B is selected.

In this case, since the number of gradation data that can be taken per one song is 4 bits, the lower 4 bits (PL _{0 to 3} and PH respectively) among the 8-bit data PL _{0 to 7} and PH ₀ to 7 output from the pallet RAM 12 and 13 are used. Only _0-7 ) are extracted and output as PIX _0-7 . In addition, the conversion modes A and C indicate conversion formats at four times (4X) and equal multiples (1X), respectively.

As described above, the pixel data (color information) in the VRAM 5 is converted into gradation data on the display panel by the two multiplexers 11 and 14 and the pallet RAM.

(2) boundary register

As described above, when the effective pixel number of the liquid crystal display device is larger than the resolution of the posi mode, a certain pattern must be displayed on the remaining pixels (boundary portions) outside the effective display area. The boundary register 2 is provided for storing data output to this boundary.

7 shows the configuration of the boundary register.

In the present embodiment, the boundary register is basically one register of 8 bits in length, and each bit corresponds to the boundary data BO _{0 to} 7 (Fig. 7).

The boundary register 2 has a so-called double buffer structure, and can be inputted at any timing from the GCPU 6. The actual boundary data is set at the economic register output stage at the timing of the horizontal synchronizing signal or the vertical synchronizing signal.

It is the horizontal and vertical blank signals HBlank and VBlank that control the timing of sending out the data set in the boundary register 2. Basically, it is one of each of the blank signal, and the boundary data output to when the L ₀ level (blank period), in the period other than that outputted the image data in the effective display region as shown in claim 8, Fig. This will be described in detail in the operation of the data selector described later.

(3) Scan line address data generating section

The scan line address generator 3 is provided to generate scan line address data A ₀ to ₁₅ of the display panel. The scan line address generator 3 is a 12-bit binary counter (up to 4096 scan lines can be selected) whose clock is the horizontal synchronization signal Hsync input to the display controller on the liquid crystal display side. This counter can preset the counter value (scan line address data) in the CGPU 6 at an arbitrary timing.

Furthermore, the width of the countup (indicating how many scan lines are jumped and scanned) can also be set.

(4) Output section to the liquid crystal display device

The image data transmission format to the ferroelectric liquid crystal display device has already been applied to the communication method for realizing high resolution display in display elements having memory characteristics in Japanese Patent Application No. 61-212184 or Japanese Patent Application No. 63-285141. Is offering.

According to these proposals regarding the transfer of image data, the scanning line address information and the image information are serially time-divided and transmitted on the same transmission line with respect to the scanning line which needs to be rewritten.

The data selector 4 is provided to realize such a transmission format.

The data selector 4 uses the scan line address data based on the image data PD _0-7 , the boundary data BD _0-7 and the timing control signal from the GCPU 6 by the gray scale conversion. The three types of data (A _{0 to 15} ) are converted to time division and the converted data is sent to the display device.

9 is an example of a transmission format from a display interface serving as an image information output circuit according to the present invention according to the method of the above proposal.

10. The method of claim 9 also, the timing control of the horizontal blanking signal when (HBlank) is a horizontal synchronization signal (Hsync) input during the period to be set to L ₀ level (blank period), the data selector 4 has GCPU (6) First, the scanning line address data A ₀ to ₁₅ are output in two cycles (4 clocks CLK). Next, the boundary data BD _{0 to 7} from the boundary register 2 are subsequently transmitted on the communication line PIX ₀ to 7 for a period until the HBlank is set to the Hi level.

When the HBlank is set at the Hi level (after completion of the blank period), the image data PD ₀ to 7 in the effective display area for gradation conversion are transmitted on the communication lines DIX ₀ to 7.

When FIG. 9 as the image data in the effective display area, the information of 1280 pixels (640 pixels) in the GCPU minutes transmission (6) is again set to the L ₀ HBIank level.

Data selector 14 is set to L ₀ when the HBlank level to be transmitted again with the boundary data (BD _0~7) a communication line (PIX _0~7), ends the transmission of data of all the pixels (640 pixels).

9 shows transmission timing in the horizontal scanning direction.

The data selector 4 also distinguishes the boundary area from the effective display area by using a vertical blanking signal in the vertical scanning direction, and switches the output data.

Furthermore, by controlling the timing of HBlank and VBlnak, the effective display area can also be displayed at any position on the screen.

As described above, in a display device using a ferroelectric liquid crystal having a bistable (memory), the first multiplexer and the first multiplexer output the image data read from the image memory to the next step every pixel. Provided is an image information output circuit having a pallet RAM for outputting ON / OFF data of a predetermined pixel based on the second pixel, and a second multiplexer for converting data from the pallet RAM into an output format for transfer to a display device. do. Image data conversion processing corresponding to the display mode request from the main body CPU and processing outside the effective display area (frame portion) are performed.

Therefore, display screens in various display modes that have been used in conventional CRTs and the like can be displayed on a display device using a binary display element such as a ferroelectric liquid crystal display device or the like without loss of an image.

Claims (8)

A display device comprising a display panel with a liquid crystal for displaying image data in a plurality of display modes in which at least the number of pixels, the display color and the minimum subunit are each different, the display device comprising: storage means (5) for storing image data; Pixel data output means (11) for outputting image data stored in the storage means for each pixel data; Converting means (14) for converting pixel data output by said pixel data output means and composed of image data into a large number of display data which changes according to the number of pixels in one of various display modes and the number of pixels on the display panel; And display data output means (4) for outputting display data converted by said converting means to a display panel. The display device according to claim 1, wherein the pixel data output means comprises a multiplexer. 2. A display apparatus according to claim 1, wherein said display data output means comprises RAM (random access memory) storing binary data. The display apparatus according to claim 1, wherein said display data output means is constituted by a plurality of RAMs (random access memories) storing binary data. The display apparatus according to claim 1, further comprising frame display means for displaying predetermined frame image data outside the effective display area of the image data displayed on the display panel. 6. The display device according to claim 5, wherein the frame display means outputs and displays frame image data outside the effective display area within the horizontal and vertical blanking periods of the image data displayed on the effective display area. The display apparatus according to claim 1, wherein said display data output means comprises a multiplexer. The display device of claim 1, wherein the liquid crystal having a memory property comprises a ferroelectric liquid crystal.