EP0379169B1 - Circuit retardeur de signaux utilisant un circuit pompe de charge - Google Patents

Circuit retardeur de signaux utilisant un circuit pompe de charge Download PDF

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Publication number
EP0379169B1
EP0379169B1 EP90100915A EP90100915A EP0379169B1 EP 0379169 B1 EP0379169 B1 EP 0379169B1 EP 90100915 A EP90100915 A EP 90100915A EP 90100915 A EP90100915 A EP 90100915A EP 0379169 B1 EP0379169 B1 EP 0379169B1
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EP
European Patent Office
Prior art keywords
signal
circuit
delay
output
inverter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP90100915A
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German (de)
English (en)
Other versions
EP0379169A2 (fr
EP0379169A3 (en
Inventor
Hiroyuki C/O Intelleectual Property Div. Motegi
Kenji C/O Intelleectual Property Div. Matsuo
Akira C/O Intelleectual Property Div. Nagae
Hideaki C/O Intelleectual Property Div. Uchida
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Toshiba Corp
Toshiba Electronic Device Solutions Corp
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Toshiba Corp
Toshiba Microelectronics Corp
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Publication of EP0379169A3 publication Critical patent/EP0379169A3/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00323—Delay compensation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • H03K2005/00097—Avoiding variations of delay using feedback, e.g. controlled by a PLL
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • H03K2005/0013—Avoiding variations of delay due to power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's

Definitions

  • the present invention relates to a signal delay circuit
  • a signal delay circuit comprising: a first delay means, constituted by at least one delay stage having a signal delay time controlled on the basis of a control signal, for delaying an input signal having a predetermined frequency, a first logic circuit for detecting a signal delay amount of said first delay means, and a charge pump circuit, having a capacitor, for generating a DC voltage by charging and discharging said capacitor with currents of an arbitrary multiple of a reference current on the basis of the input signal and a detection signal from said first logic circuit, and feeding back the DC voltage to said first delay means as the control signal, said charge pump circuit comprising first setting means for setting to a first value the power ratio between the charge and discharge currents, which power ratio coincides with a reciprocal of a ratio of widths of predetermined levels of the input signal and the detection signal from said first logic circuit.
  • Such a circuit is disclosed in FR-A-2 604 836.
  • the invention also relates to a method of delaying an input signal comprising applying said input signal having a predetermined frequency to a first delay means, constituted by at least one delay stage having a signal delay time controlled on the basis of a control signal;
  • a signal delay circuit for delaying an input clock signal by a predetermined period, a frequency multiplier for outputting a clock signal having a frequency twice that of an input clock signal, and a voltage-controlled oscillator (to be referred to as a VCO hereinafter) for outputting a clock signal having a frequency corresponding to a control voltage are formed in a semiconductor integrated circuit as needed.
  • a conventional signal delay circuit is constituted by using elements such as resistors or capacitors. The values of these resistors or capacitors change in accordance with variations in process parameters in the manufacture. Therefore, in the conventional signal delay circuit, a signal delay amount is not uniformly determined.
  • a conventional frequency multiplier utilizes a signal delay amount produced by a circuit using an inverter and a capacitor. This signal delay amount changes in accordance with the characteristics of the inverter or the value of the capacitor. The characteristics of the inverter also depend on a power source voltage or an ambient temperature. Therefore, since the delay amount is not uniformly determined, lengths of "H"- and "L"-level periods vary.
  • the present invention has been made in consideration of the above situation, and has as its object to provide a signal delay circuit which is not adversely affected by variations in process parameters in the manufacture and can provide a predetermined delay amount.
  • the signal delay circuit initially defined is characterised in that said charge pump circuit further comprises second setting means for modifying said charge or said discharge current, thereby setting said power ratio to a different value from that set by said first setting means; and selecting means for selectively operating said first and second setting means in dependence on a first or a second external control signal, respectively, for selecting one or the other value of said power ratio.
  • the method of delaying a signal initially defined is characterised by arbitrarily controlling the charge or discharge current value in accordance with an external control signal, in order to set the power ratio to a different value.
  • Fig. 1 is a block diagram to assist in explaining embodiments according to the present invention.
  • reference symbol IN denotes a clock signal having a predetermined frequency.
  • the signal IN is supplied to a delay circuit 141.
  • the circuit 141 delays the signal IN, and its delay time is set in accordance with a control signal to be described later.
  • a delayed output signal from the delay circuit 141 is supplied to a delay amount detector 142.
  • the detector 142 detects the delay time with respect to the clock signal IN.
  • the signal IN is sometimes supplied to the detector 142 as indicated by a broken line in Fig. 1 as needed.
  • a detection signal from the detector 142 and the signal IN are supplied to a charge pump circuit 143.
  • the circuit 143 charges a predetermined capacitor for only a pulse period of the signal IN and discharges the predetermined capacitor for only a pulse period of the detection signal so that a charge amount and a discharge amount of the above capacitor equal to each other.
  • the circuit 143 generates a control voltage such that the delay time of the delay circuit 141 is arbitrarily set in accordance with a current power ratio between current power upon charge and current power upon discharge. The generated control voltage is fed back to the delay circuit 141 as a control signal.
  • the output from the charge pump circuit 143 is sometimes supplied to the delay circuit 141 via a low-pass filter circuit as needed.
  • Fig. 2 is a circuit diagram showing an arrangement of a signal delay circuit.
  • This embodiment comprises a reference current set circuit 1 and a charge pump circuit 2, both of which correspond to the charge pump circuit 143 shown in Fig. 1, a low-pass filter circuit 3, a delay circuit 4 corresponding to the delay circuit 141 shown in Fig. 1, and a logic circuit 5 corresponding to the delay amount detector 142 shown in Fig. 1.
  • the reference current set circuit 1 sets reference current values of inflow and outflow currents with respect to a capacitor to be described later in the charge pump circuit 2, and comprises a p-channel MOS transistor 21, a resistor 22, and an n-channel MOS transistor 23 inserted in series between an application point of a power source voltage V DD and an application point of a ground voltage GND.
  • the gate of the transistor 21 is connected to its drain, i.e., a node 24 at one terminal of the resistor 22.
  • the gate of the transistor 23 is connected to its drain, i.e., a node 25 at the other terminal of the resistor 22.
  • a current I ref flows through the transistor 21, the resistor 22, and the transistor 23.
  • the value of the resistor 22 is normally set much higher than ON resistances of the transistors 21 and 23 so that the value of I ref is determined by the value of the resistor 22.
  • the element size is the same as the transistor 21
  • a voltage V p which allows a current equal to the current I ref to flow through the p-channel MOS transistor is obtained at the node 24.
  • a voltage V n which allows a current equal to the current I ref to flow through the n-channel MOS transistor is applied to the node 25.
  • the voltages V p and V n are applied to the charge pump circuit 2.
  • the circuit 2 comprises two p-channel MOS transistors 27 and 28 inserted in series between the application point of the power source voltage V DD and an output node 26, two n-channel MOS transistors 29 and 30 inserted in series between the node 26 and the application point of the ground voltage GND, and a capacitor 31 consisting of, e.g., drain capacitances of the transistors 28 and 29 present at the output node and a wiring capacitance. Note that the above capacitor 31 is not parasitically present but may be a real capacitor.
  • the gates of the transistors 27 and 30 receive the voltages V p and V n , respectively, output from the reference current set circuit 1.
  • An input clock signal CLK IN having a predetermined frequency is supplied to the gate of the transistor 28.
  • An output signal c from the logic circuit 5 is supplied to the gate of the transistor 29.
  • the transistor 27 constitutes a current mirror circuit together with the transistor 21 in the circuit 1.
  • a current flowing through the transistor 27 is determined on the basis of the value of the reference current I ref and a size ratio between the transistors 21 and 27. For example, assuming that a W/L (ratio of a channel width to a channel length: current power of a transistor is determined by this value) of the transistor 21 is 1, a W/L of the transistor 27 is set to be A 1 (which is a positive value and a arbitrary value).
  • the transistor 30 constitutes a current mirror circuit together with the transistor 23 in the circuit 1.
  • a current flowing through the transistor 30 is determined on the basis of the value of the reference current I ref and a size ratio between the transistors 23 and 30. For example, assuming that a W/L of the transistor 23 is 1, a W/L of the transistor 30 is set to be A 2 (which is a positive value and a arbitrary value).
  • the transistors 27 and 28 flow a current to the capacitor 31. While the transistor 28 is kept on on the basis of the input clock signal CLK IN , the capacitor 31 is charged by a current having a predetermined value determined by the transistor 27.
  • the two n-channel MOS transistors 29 and 30 cause a current to flow out from the capacitor 31. While the transistor 29 is kept on on the basis of the output signal from the logic circuit 5, the capacitor 31 is discharged by a current having a predetermined value determined by the transistor 30.
  • the low-pass filter circuit 3 obtains a DC voltage by smoothing a terminal voltage of the capacitor 31 of the charge pump circuit 2, and comprises a resistor 32 and a capacitor 33. If the value of the capacitor 31 is sufficiently large, the capacitor 33 or the resistor 32 of the low-pass filter circuit 3 or the circuit 3 itself is not sometimes required. A signal d obtained by the circuit 3 is supplied to the delay circuit 4.
  • the delay circuit 4 is constituted by cascade-connecting, e.g., three delay stages 34, 35, and 36 having the same arrangement.
  • the input clock signal CLK IN is supplied to the first delay stage 34.
  • Output signals a and b from the delay stages 34 and 35 are sequentially supplied to the subsequent stages as input signals.
  • An output signal from the last delay stage 36 is supplied as a delay clock signal CLK OUT .
  • Each of the delay stages 34, 35, and 36 comprises a p-channel MOS transistor 38 connected at its one terminal to an input node 37, an inverter 39 having an input terminal connected to the other terminal of the transistor 38, a p-channel MOS transistor 40 having one terminal connected to the output terminal of the inverter 39, an inverter 41 having an input terminal connected to the other terminal of the transistor 40, an output node 42 connected to the output terminal of the inverter 41, and an inverter 43 having an input terminal connected to the output node 42.
  • the output signal d from the low-pass filter circuit 3 is supplied in parallel to the gates of the transistors 38 and 40 of each of the delay stages 34, 35, and 36.
  • the logic circuit 5 is for obtaining the signal c and comprises an inverter 44 for inverting an output signal from the inverter 43 of the delay stage 35, a NAND gate 45 for receiving an output signal from the inverter 44 and the output signal from the inverter 43 of the delay stage 34, and an inverter 46 for inverting an output signal from the NAND gate 45.
  • t 1 /t 2 A 2 /A 1 as described above, i.e., if a current power ratio between the transistors 27 and 30 coincides with a reciprocal of a pulse width ratio between the input clock signal CLK IN and the output signal c from the logic circuit 5, a charge amount flowing in the capacitor 31 is equal to that flowing out from the capacitor 31, and a voltage value of the output signal d from the low-pass filter circuit 3 is determined to be a certain arbitrary value.
  • ON resistances of the transistors 38 and 40 become predetermined values, and a delay amount in each delay stage becomes a predetermined value.
  • the delay amount t 2 in each delay stage of the delay circuit 4 is always controlled to be a predetermined value on the basis of the ratio of A 2 to A 1 by a phase synchronizing loop constituted by the charge pump circuit 2, the low-pass filter circuit 3, the delay circuit 4, and the logic circuit 5. That is, in this embodiment, the delay amount corresponding to 1/4 of the "L"-level period t 1 of the input clock signal CLK IN can be obtained in each delay stage, and the delay time of the output clock signal CLK OUT with respect to the input clock signal CLK IN is obtained as 3t 2 .
  • the ratio of A 2 to A 1 (A 2 /A 1 ) is set to be 4, and the three delay stages are provided in the delay circuit 4, thereby obtaining the delay time of 3t 2 .
  • Various delay times can be obtained by increasing/decreasing the value of A 2 /A 1 and the number of delay stages in the delay circuit 4.
  • Fig. 4 is a circuit diagram showing an arrangement according to the first modification of the circuit shown in Fig. 2.
  • the logic circuit 5 is constituted by the inverter 44, the NAND gate 45, and the inverter 46, the output signal c from the circuit 5 is supplied to the gate of the n-channel MOS transistor 29, and the input clock signal CLK IN is supplied to the gate of the p-channel MOS transistor 28.
  • a logic circuit 5 is constituted by a NOR gate 49 for receiving output signals from inverters 43 in delay stages 34 and 35 and an inverter 46 for inverting an output signal from the NOR gate 49, an output signal c from the circuit 5 is supplied to the gate of a p-channel MOS transistor 28, and an input clock signal CLK IN is supplied to the gate of an n-channel MOS transistor 29.
  • the output signal c from the circuit 5 has a relationship as shown in a timing chart of Fig. 5. If a ratio of A 2 in a transistor 30 to A 1 of a transistor 27 is set to coincide with a reciprocal of a pulse width ratio between the input clock signal CLK IN and the output signal c from the circuit 5, a delay time similar to that shown in Fig. 2 is obtained.
  • Fig. 6 is a circuit diagram showing an arranqement according to the second modification of thecircuit shown in Fig. 2.
  • This modification comprises, in the charge pump circuit 2, two n-channel MOS transistors 29 and 30 inserted in series between an output node 26 and an application point of a ground voltage GND, two n-channel MOS transistors 144 and 145 inserted in series between an output node 26 and an application point of the ground voltage GND, two NAND gates 146 and 147, and two inverters 148 and 149.
  • An output signal c from the logic circuit 5 is supplied in parallel to input terminals of the NAND gates 146 and 147, and select signals S2 and S1 are externally supplied to the other input terminals of the NAND gates 146 and 147.
  • Output signals from the NAND gates 146 and 147 are supplied to the gates of the transistors 144 and 29 via the inverters 148 and 149, respectively.
  • the voltage V n is supplied in parallel to the gates of the transistors 30 and 145.
  • the select signal S1 is switched to an "H" level
  • the transistor 29 is selected, and a delay time similar to that of the embodiment shown in Fig. 2 is obtained.
  • the select signal S2 is switched to the "H” level
  • the transistor 144 is selected to discharge the capacitor 31 in accordance with the current power of the transistor 145. For example, if the current power of the transistor 145 is set twice that of the transistor 30, the pulse width of the signal c shown in Fig. 3 is reduced to be 1/2.
  • a delay time in each delay stage of a delay circuit 4 becomes (1/2)t 2
  • a total delay time i.e., a delay time of an output clock signal CLK OUT with respect to an input clock signal CLK IN becomes (3/2)t 2 . That is, in this modification, a discharge current value of the charge pump circuit 2 can be controlled by the external control signals (S1 and S2). Note that such a modification can be similarly applied to the charge current side.
  • a logic circuit of this modification comprises a NAND gate 47 for receiving an output signal from an inverter 43 in the delay stage 34 and the input clock signal CLK IN and an inverter 48 for inverting an output signal from the NAND gate 47.
  • an output signal c from the logic circuit having the above arrangement has a pulse width t 2 similar to that shown in Fig. 2.
  • Figs. 9A, 9B, and 9C are circuit diagrams each showing another arrangement of the delay stage provided in the delay circuit 4.
  • An arrangement shown in Fig. 9A comprises a CMOS transmission gate 51 having parallel p- and n-channel MOS transistors and one terminal connected to an input node 37, an inverter 52 having an input terminal connected to the other terminal of the transmission gate 51, a CMOS transmission gate 53 having parallel p- and n-channel MOS transistors and one terminal connected to the output terminal of the inverter 52, an inverter 54 having an input terminal connected to the other terminal of the transmission gate 53 and an output terminal connected to an output node 42, and an inverter 55 having an input terminal connected to the output node 42.
  • An output signal d from the low-pass filter circuit 3 is supplied in parallel to the gates of the p-channel MOS transistor sides of the transmission gates 51 and 53, and a power source voltage V DD is supplied in parallel to the gates of the n-channel MOS transistor sides. That is, since the n-channel MOS transistors applied with the power source voltage V DD on their gates are connected in parallel to the p-channel MOS transistors 38 and 40 shown in Fig. 2, a change is obtained in the delay transmission characteristics of this delay stage.
  • a delay stage shown in Fig. 9B comprises two gate circuits 56 and 57 and an inverter 58.
  • the gate circuit 56 is constituted by two p-channel MOS transistors 60 and 61 inserted in series between an application point of a power source voltage V DD and an internal node 59, and an n-channel MOS transistor 62 inserted between the internal node 59 and an application point of a ground voltage GND.
  • An output signal d from the low-pass filter circuit 3 is supplied to the gate of the transistor 60, and a signal from an input node 37 is supplied to the gates of the transistors 61 and 62.
  • the other gate circuit 57 is constituted by two p-channel MOS transistors 60 and 61, and an n-channel MOS transistor 62.
  • the signal d is supplied to the gate of the transistor 60, and a signal from the internal node 59 is supplied to the gates of the transistors 61 and 62.
  • the inverter 58 inverts a signal from the output
  • ON resistances of the p-channel MOS transistors 60 in the gate circuits 56 and 57 are controlled in accordance with the output signal d from the low-pass filter circuit 3 to determine a delay amount.
  • a delay stage shown in Fig. 9C comprises an inverter 63 and a gate circuit 64.
  • a signal from the input node 37 is supplied to the inverter 63.
  • the gate circuit 64 is constituted by two p-channel MOS transistors 65 and 66 inserted in series between an application point of a power source voltage V DD and an output node 42 and an n-channel MOS transistor 67 inserted between the output node 42 and an application point of a ground voltage GND.
  • An output signal d from the low-pass filter circuit 3 is supplied to the gate of the transistor 65, and an output signal from the inverter 63 is supplied to the gates of the transistors 66 and 67.
  • An output signal from the inverter 63 is also used as an input signal to the logic circuit 5.
  • an ON resistance of the p-channel MOS transistor 65 in the gate circuit 64 is controlled in accordance with the output signal d from the low-pass filter circuit 3 to determine a delay amount.
  • the output signal d from the low-pass filter 3 is directly supplied to the delay circuit 4.
  • a signal d from a low-pass filter circuit 3 may be supplied to a level converter 6 and an output signal e from the converter 6 may be supplied to a delay circuit 4 via a low-pass filter 7.
  • the low-pass filter circuit 7 is provided as needed.
  • the level converter 6 is constituted by an inverter 73 which includes a p-channel MOS transistor 71 and an n-channel MOS transistor 72 and receives the signal d , and a source follower type inverter 76 which includes a p-channel MOS transistor 74 and an n-channel MOS transistor 75 and receives an output signal from the inverter 73.
  • the low-pass filter circuit 7 is constituted by a resistor 32 and a capacitor 33.
  • the output signal d from the low-pass filter circuit 3 changes within a voltage range from V DD to GND.
  • Fig. 11 is a circuit diagram showing an arrangement of a clock signal generator.
  • the signal delay circuit which the ratio of A 2 /A 1 is set to be 4 shown in Fig. 2, is used to extract an output clock signal CLK OUT1 having a frequency twice that of an input clock signal CLK IN and an output clock signal CLK OUT2 having a frequency four times that of the signal CLK IN .
  • an output logic circuit 8 is additionally provided in a signal delay circuit comprising a reference current set circuit 1, a charge pump circuit 2, a low-pass filter circuit 3, a delay circuit 4, and a logic circuit 5 as shown in Fig. 2.
  • the logic circuit 8 is constituted by two logic circuits 9 and 10.
  • the logic circuit 9 includes an inverter 81 for inverting the input clock signal CLK IN , an inverter 82 for inverting an output signal from an inverter 43 in a delay stage 35, an AND gate 83 for receiving the signal CLK IN and an output signal from the inverter 43 in the delay stage 35, an AND gate 84 for receiving output signals from the inverters 81 and 82, a NOR gate 85 for receiving output signals from the AND gates 83 and 84, and an inverter 86 for inverting an output signal from the NOR gate 85.
  • the logic circuit 9 outputs the clock signal CLK OUT1 having a frequency twice that of the signal CLK IN .
  • the other logic circuit 10 includes an inverter 87 for inverting the signal CLK IN , inverters 88 to 90 for inverting output signals from inverters 43 in delay stages 34 to 36, respectively, an AND gate 91 for receiving the signal CLK IN and an output signal from the inverter 43 in the delay stage 34, an AND gate 92 for receiving an output signal from the inverter 89 and an output signal from the inverter 43 in the delay stage 36, an AND gate 93 for receiving output signals from the inverters 87 and 88, an AND gate 94 for receiving an output signal from the inverter 43 in the delay stage 35 and an output signal from the inverter 90, a NOR gate 95 for receiving output signals from the AND gates 91 to 94, and an inverter 96 for inverting an output signal from the NOR gate 95.
  • the logic circuit 10 outputs the clock signal CLK OUT2 having a frequency four times that of the signal CLK IN .
  • the input clock signal CLK IN a predetermined frequency and delayed outputs normally controlled to have a predetermined delay amount by a phase-locked loop as described above from the delay stages 34 to 36 are selectively supplied to the logic circuits 9 and 10. Therefore, the frequencies of the output clock signals CLK OUT1 and CLK OUT2 from the logic circuits 9 and 10 are not adversely affected by variations in manufacturing conditions or the like but can be stabilized.
  • various types of logic circuit may be provided in the output logic circuit 8 to extract an output clock signal having a frequency of a arbitrary multiple of the frequency of the signal CLK IN .
  • a logic circuit 5 having the arrangement as shown in Fig. 4 may be provided to supply the input clock signal CLK IN to the gate of an n-channel MOS transistor 29 and an output signal c from the logic circuit 5 to the gate of a p-channel MOS transistor 28, thereby operating the transistors. All the modifications of the first embodiment shown in Fig. 2 can be applied to this second embodiment.
  • Fig. 13 is a circuit diagram showing another clock signal generator.
  • An output logic circuit 8 of the clock signal generator shown in Fig. 11 has an arrangement as shown in Fig. 13.
  • the output logic circuit 8 comprises an inverter 100 for inverting an input clock signal CLK IN , an inverter 101 for inverting an output signal from an inverter 43 in a delay stage 36, a NAND gate 102 for receiving the signal CLK IN and the output signal from the inverter 43 in the delay stage 36, an inverter 103 for inverting an output signal from the NAND gate 102, a NAND gate 104 for receiving output signals from the inverters 100 and 101, and an inverter 105 for inverting an output signal from the NAND gate 104.
  • the circuit 8 outputs two-phase clock signals ⁇ 1 and ⁇ 2 having the same frequency as that of the signal CLK IN .
  • the input clock signal CLK IN having a predetermined frequency and a delayed output normally controlled to have a predetermined delay amount by a phase-locked loop from each delay stage are supplied to the output logic circuit 8. Therefore, the frequencies of the two-phase clock signals ⁇ 1 and ⁇ 2 output from the output logic circuit 8 are not adversely affected by variations in manufacture conditions or the like but stable.
  • a multi-phase clock signal of two phases or more can be extracted by increasing the number of delay stages in the delay circuit 4 and changing the arrangement of the logic circuit provided in the output logic circuit 8.
  • a logic circuit 5 having the arrangement as shown in Fig. 4 can be used to supply the input clock signal CLK IN to the gate of the n-channel MOS transistor 29 and the output signal c from the logic circuit 5 to the gate of the p-channel MOS transistor 28, thereby operating the transistors. All the modifications of the first embodiment shown in Fig. 2 can be applied to this third emhodiment.
  • Fig. 15 is a circuit diagram showing an arrangement of yet another clock signal generator. This generator, similar to the clock signal generator shown in Fig. 13, is applied for extracting a two-phase clock signal.
  • a logic circuit 12 and a delay circuit 13 for receiving an output signal ⁇ 1 from the logic circuit 12 are provided in an output logic circuit 8.
  • the logic circuit 12 is constituted by a NAND gate 106 for receiving an input clock signal CLK IN and an output signal from an inverter 43 of a delay stage 36 in the delay circuit 4, and an inverter 107 for receiving an output signal from the NAND gate 106.
  • the circuit 12 outputs the clock signal ⁇ 1 of the clock signals shown in the timing chart of Fig. 14.
  • the delay circuit 13 is constituted by four cascade-connected delay stages 111 to 114 each having the same arrangement as the delay stage in the delay circuit 4 and a delay amount controlled by an output signal d from the low-pass filter 3.
  • An output clock signal ⁇ 1 from the logic circuit 12 is supplied to the first delay stage 111 of the delay circuit 13, and the other clock signal ⁇ 2 is output from the last delay stage 114.
  • the signal ⁇ 2 of two-phase clock signals can also be extracted by delaying the clock signal ⁇ 1 by a predetermined time by the delay circuit 13 constituted by using the delay stages each having the same delay amount as that of the delay circuit 4 in a phase-locked loop.
  • the delay circuit 13 can also be used to delay a signal by a predetermined time by inputting another input signal to the circuit 13 instead of the clock signal ⁇ 1.
  • the delay circuit 13 can also be used to delay a signal by a predetermined time by inputting another input signal to the circuit 13 instead of the clock signal ⁇ 1.
  • a logic circuit 5 having the arrangement shown in Fig.
  • Fig. 16 is a circuit diagram showing an arrangement of yet another clock signal generator.
  • a ring oscillator comprising a delay circuit 14 and an inverter for feeding back an output signal from the delay circuit 14 to the input side of the circuit 14 is arranged.
  • the delay circuit 14 is constituted by cascade-connecting two delay stages 115 and 116 each having the same arrangement as the delay stage in the delay circuit 4 of the phase-locked loop and a delay amount controlled by an output signal d from the low-pass filter circuit 3.
  • each delay stage in the delay circuits 4 and 14 has a delay amount corresponding to a 1/8 period of the input clock signal CLK IN as described above.
  • Fig. 17 is a timing chart of this clock signal generator.
  • a clock signal having a frequency twice that of an input clock signal can be extracted. Also, since a delay amount of each delay stage is controlled to be predetermined by a phase-locked loop, the frequency of the output clock signal CLK OUT is adversely affected by variations in manufacturing conditions or the like but can be stabilized. Also in this embodiment, a logic circuit 5 having the arrangement shown in Fig. 4 can be provided to supply the signal CLK IN to the gate of an n-channel MOS transistor 29 and an output signal c from the logic circuit 5 to the gate of a p-channel MOS transistor 28, thereby operating the transistors. All the modifications of the circuit shown in Fig. 2 can be applied to the clock signal generator.
  • Fig. 18 is a circuit diagram showing an arrangement of a still further clock signal generator, in which the ratio of A 2 /A 1 is set to be 4, an output logic circuit 8 constituted by a delay circuit 16 including two delay stages 117 and 118 and an inverter 17 is additionally provided to the signal delay circuit according to the first embodiment including the reference current set circuit 1, the charge pump circuit 2, the low-pass filter circuit 3, and the delay circuit 4 having the three delay stages.
  • each delay stage comprises a CMOS transmission gate 123 which includes parallel-connected p- and n-channel MOS transistors 121 and 122 and receives a signal from an input node 37, an inverter 124 for inverting an output signal from the transmission gate 123, a CMOS transmission gate 127 which includes parallel-connected p- and n-channel MOS transistors 125 and 126 and receives an output signal from the inverter 124, an inverter 128 for inverting an output signal from the transmission gate 127 and outputting the inverted output signal to an output node 42, and an inverter 129 for inverting a signal from the output node 42.
  • CMOS transmission gate 123 which includes parallel-connected p- and n-channel MOS transistors 121 and 122 and receives a signal from an input node 37
  • an inverter 124 for inverting an output signal from the transmission gate 123
  • a CMOS transmission gate 127 which includes parallel-connected p- and n
  • An output signal d from the low-pass filter circuit 3 is supplied in parallel to the gates of the p-channel MOS transistor sides of the transmission gates of each delay stage in the delay circuits 4 and 16.
  • a predetermined reference voltage Vref is supplied in parallel to the gates of the n-channel MOS transistor sides of the transmission gates of each delay stage in the delay circuit 4.
  • a control voltage vcont is supplied in parallel to the gates of the n-channel MOS transistor sides of the transmission gates of each delay stage in the delay circuit 16.
  • the output logic circuit 8 operates as a ring oscillator for oscillating a signal having a frequency twice that of an input clock signal CLK IN .
  • a delay amount of a delay stage can be precisely controlled by a phase-locked loop. Therefore, a signal delay circuit capable of obtaining a stable delay time regardless of variations in manufacturing conditions can be provided.
  • the above signal delay circuit can be used to provide a clock signal generator capable of generating a clock signal having a stable frequency regardless of variations in manufacturing conditions.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
  • Dram (AREA)

Claims (15)

  1. circuit retardeur de signaux comprenant :
    un premier moyen retardeur (4), constitué par au moins un étage retardeur (34, 35, 36) ayant un retard de signal commandé sur la base d'un signal de commande (d), pour retarder un signal d'entrée (CLKIN) ayant une fréquence prédéterminée ;
    un premier circuit logique (5) pour détecter une quantité de retard de signal dudit premier moyen retardeur ; et
    un circuit de pompe à charge (2) ayant un condensateur (31), pour générer une tension continue (d) en chargeant et déchargeant ledit condensateur avec des courants d'un multiple arbitraire d'un courant de référence (Iref) sur la base du signal d'entrée (CLKIN) et d'un signal de détection (c) dudit premier circuit logique (5), et pour renvoyer la tension continue (d) audit premier moyen retardeur (4) comme signal de commande, ledit circuit de pompe à charge (2) comprenant un premier moyen de réglage (27 à 30) pour régler à une première valeur le rapport de puissance entre les courants de charge et de décharge lequel rapport de puissance coïncide avec l'inverse d'un rapport de largeurs (t1, t2) de niveaux prédéterminés du signal d'entrée et le signal de détection (c) dudit premier circuit logique (5) ;
       caractérisé en ce que ledit circuit de pompe à charge (2) comprend en outre un second moyen de réglage (144, 145) pour modifier ledit courant de charge ou ledit courant de décharge, réglant ainsi ledit rapport de puissance à une valeur différente de celle réglée par ledit premier moyen de réglage ; et un moyen de sélection (146 à 149) pour actionner respectivement de façon sélective lesdits premier et second moyens de réglage en fonction d'un premier ou d'un second signal de commande externe (S1, S2), pour sélectionner l'une ou l'autre valeur dudit rapport de puissance.
  2. Circuit selon la revendication 1, caractérisé en ce qu'un circuit de filtre passe-bas (3) est inséré entre ledit circuit de pompe à charge et ledit premier moyen retardeur.
  3. Circuit selon la revendication 1 ou 2, caractérisé en ce qu'un étage retardeur dudit premier moyen retardeur comprend :
    un noeud d'entrée (37) ;
    un premier transistor (38), raccordé à une borne de celui-ci audit noeud d'entrée, pour recevoir le signal de commande sur une grille de celui-ci ;
    un premier inverseur (39) ayant une borne d'entrée raccordée à l'autre borne dudit premier transistor ;
    un second transistor (40) ayant la même polarité que ledit premier transistor, raccordé à une borne de celui-ci sur une borne de sortie dudit premier inverseur, pour recevoir le signal de commande sur une grille de celui-ci ;
    un second inverseur (41) ayant une borne d'entrée raccordée à l'autre borne dudit second transistor ;
    un noeud de sortie (42) formé par la sortie dudit second inverseur ; et
    un troisième inverseur (43) ayant une borne d'entrée raccordée audit noeud de sortie.
  4. Circuit selon l'une quelconque des revendications précédentes, caractérisé en ce qu'un étage retardeur dudit premier moyen retardeur comprend :
    un noeud d'entrée (37) ;
    une première porte de transmission CMOS (51) raccordée à une borne de celui-ci audit noeud d'entrée et constituée par des transistors ayant des première et seconde polarités ;
    un premier inverseur (52) ayant une borne d'entrée raccordée à l'autre borne de ladite première porte de transmission ;
    une seconde porte de transmission CMOS (53) raccordée à une borne de celui-ci sur une borne de sortie dudit premier inverseur et constituée par des transistors ayant des première et seconde polarités ;
    un second inverseur (54) ayant une borne d'entrée raccordée à l'autre borne de ladite seconde porte de transmission CMOS ;
    un noeud de sortie (42) raccordé à une borne de sortie dudit second inverseur ; et
    un troisième inverseur (55) ayant une borne d'entrée raccordée audit noeud de sortie ;
    dans lequel ledit signal de commande est appliqué aux grilles desdits transistors ayant une première polarité desdites première et seconde portes de transmission CMOS, et une tension de courant continu prédéterminée (VDD) est appliquée aux grilles desdits transistors ayant la seconde polarité desdites première et seconde portes de transmission CMOS.
  5. Circuit selon l'une quelconque des revendications précédentes caractérisé en ce qu'un étage retardeur dudit premier moyen retardeur comprend :
    un noeud d'entrée (37), un noeud interne (59) et un noeud de sortie (42) ;
    des premier et second transistors (60, 61) d'une première polarité, ayant chacun une source et un drain insérés en série entre un premier potentiel de source d'alimentation (VDD) et ledit noeud interne, et ayant des grilles pour recevoir respectivement le signal de commande et un signal dudit noeud d'entrée ;
    un troisième transistor (62) d'une seconde polarité, ayant une source et un drain insérés entre ledit noeud interne et un second potentiel de source d'alimentation (GND), et une grille pour recevoir le signal dudit noeud d'entrée ;
    des quatrième et cinquième transistors (60, 61) de la première polarité, ayant chacun une source et un drain insérés en série entre le premier potentiel de source d'alimentation (VDD) et ledit noeud de sortie, et ayant des grilles pour recevoir respectivement le signal de commande et le signal dudit noeud interne ;
    un sixième transistor (62) de la seconde polarité, ayant une source et un drain entre ledit noeud de sortie et le second potentiel de source d'alimentation (GND), et une grille pour recevoir le signal dudit noeud interne ; et
    un premier inverseur (58) ayant une borne d'entrée raccordée audit noeud de sortie.
  6. Circuit selon l'une quelconque des revendications précédentes, caractérisé en ce qu'un étage retardeur dudit premier moyen retardeur comprend :
    un noeud d'entrée (37) et un noeud de sortie (42) ;
    un premier inverseur (63) ayant une borne d'entrée raccordée audit noeud d'entrée ;
    des premier et second transistors (65, 66) d'une première polarité, ayant chacun une source et un drain insérés en série entre un premier potentiel de source d'alimentation (VDD) et ledit noeud de sortie, et ayant des grilles pour recevoir respectivement le signal de commande et un signal de sortie dudit premier inverseur ; et
    un troisième transistor (67) d'une seconde polarité, ayant une source et un drain insérés entre ledit noeud de sortie et un second potentiel de source d'alimentation (GND), et une grille pour recevoir un signal de sortie dudit premier inverseur.
  7. Circuit selon l'une quelconque des revendications précédentes, caractérisé en ce que ledit circuit de pompe à charge comprend :
    un noeud de sortie (26) pour la tension continue ;
    des premier et second transistors (27, 28) d'une première polarité, insérés en série entre un premier potentiel de source d'alimentation (VDD) et ledit noeud de sortie, et ayant des grilles pour recevoir respectivement une première tension de référence prédéterminée (Vp) et le signal d'entrée (CLKIN) ayant une fréquence prédéterminée ;
    des troisième et quatrième transistors (29, 30) d'une seconde polarité, insérés en série entre ledit noeud de sortie et un second potentiel de source d'alimentation (GND) et ayant des grilles pour recevoir respectivement le signal de sortie de détection (c) dudit premier circuit logique et une seconde tension de référence prédéterminée (Vn) ; et
    ledit condensateur (31) raccordé audit noeud de sortie.
  8. Circuit selon l'une quelconque des revendications précédentes caractérisé, en ce que ledit premier circuit logique reçoit un signal de sortie d'au moins deux étages retardeurs dudit premier moyen retardeur et détecte une quantité de retard de signal de chaque étage retardeur.
  9. Circuit selon la revendication 7 ou 8, caractérisé en ce qu'il comprend en outre un générateur de tension de référence (1) pour générer les première et seconde tensions de référence (Vp, Vn) à utiliser pour régler la valeur de courant de référence dans ledit circuit de pompe à charge.
  10. Circuit selon la revendication 9, caractérisé en ce que ledit générateur de tension de référence comprend :
    des premier et second noeuds (24, 25) pour obtenir respectivement les première et seconde tensions de référence (Vp, Vn) ;
    un premier transistor (21) d'une première polarité ayant une source et un drain insérés entre un premier potentiel de source d'alimentation (VDD) et ledit premier noeud (24), et une grille raccordée audit premier noeud (24) ;
    un second transistor (23) d'une seconde polarité ayant une source et un drain insérés entre un second potentiel de source d'alimentation (GND) et ledit second noeud (25) ; et
    une résistance (22) raccordée entre lesdits premier et second noeuds.
  11. Circuit selon l'une quelconque des revendications précédentes, caractérisé en ce que ledit premier moyen de réglage de rapport de puissance (27 à 30) comprend :
    des premier et second transistors (27, 28) d'une première polarité, insérés en série entre un premier potentiel de source d'alimentation (VDD) et un noeud de sortie (26), auxquels ledit condensateur (31) est raccordé pour générer la tension continue par le circuit de pompe à charge (2), et ayant des grilles pour recevoir respectivement une première tension de référence prédéterminée (Vp) et le signal d'entrée (CLKIN) ayant une fréquence prédéterminée ; et
    des troisième et quatrième transistors (29, 30) d'une seconde polarité, insérés en série entre ledit noeud de sortie (26) et un second potentiel de source d'alimentation (GND), et ayant des grilles pour recevoir respectivement un signal obtenu en effectuant un ET logique sur le signal de sortie de détection (c) dudit premier circuit logique et dudit premier signal de commande externe (S1), et une seconde tension de référence prédéterminée (Vn) ;
    et caractérisé en outre en ce que ledit second moyen de réglage de rapport de puissance (144, 145) comprend :
    des cinquième et sixième transistors (144, 145), insérés en série entre ledit noeud de sortie (26) et le second potentiel de source d'alimentation (GND), et ayant des grilles pour recevoir respectivement un signal obtenu en effectuant un ET logique sur le signal de sortie de détection (c) à partir dudit premier circuit logique et dudit second signal de commande externe (S2), et une seconde tension de référence prédéterminée (Vn).
  12. Circuit selon l'une quelconque des revendications précédentes, caractérisé en ce qu'un convertisseur de niveau (6) pour réduire un intervalle de variation de tension d'un signal de sortie dudit circuit de pompe à charge est inséré entre ledit circuit de pompe à charge et ledit premier moyen retardeur.
  13. Circuit selon la revendication 12 caractérisé en ce que ledit convertisseur de niveau comprend :
    un premier inverseur (73) pour recevoir un signal de sortie dudit circuit de pompe à charge ; et
    une seconde mémoire tampon (76) du type à source suiveuse pour recevoir un signal de sortie dudit premier inverseur.
  14. Procédé de retardement d'un signal d'entrée comprenant :
    une application dudit signal d'entrée (CLKIN) ayant une fréquence prédéterminée à un premier moyen retardeur (4), constitué par au moins un étage retardeur (34, 35, 36) ayant un retard de signal commandé sur la base d'un signal de commande (d) ;
    une détection d'une quantité de retard de signal dudit premier moyen retardeur utilisant un premier circuit logique (5) ; et
    une génération d'une tension continue (d) en chargeant et déchargeant un condensateur (31) avec des courants d'un multiple arbitraire d'un courant de référence (Iref) sur la base du signal d'entrée (CLKIN) et d'un signal de détection (c) dudit premier circuit logique (5) ; un renvoi de la tension continue (d) audit premier moyen retardeur (4) comme signal de commande, le rapport de puissance entre les courants de charge et de décharge coïncidant avec l'inverse d'un rapport de largeurs (t1, t2) de niveaux prédéterminés du signal d'entrée et du signal de détection dudit premier circuit logique, caractérisé en commandant arbitrairement la valeur de courant de charge et de décharge selon un signal de commande externe (51, 52) afin de régler le rapport de puissance à une valeur différente.
  15. Procédé de génération d'un signal d'horloge comprenant les étapes de :
    retardement d'un signal selon le procédé de la revendication 14 pour produire un signal de sortie retardé ; et
    génération dudit signal d'horloge (CLKOUT, CLKOUT2) ayant une fréquence différente de la fréquence du signal d'entrée sur la base du signal de sortie retardé.
EP90100915A 1989-01-17 1990-01-17 Circuit retardeur de signaux utilisant un circuit pompe de charge Expired - Lifetime EP0379169B1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP801989 1989-01-17
JP8019/89 1989-01-17
JP1331131A JP2635789B2 (ja) 1989-01-17 1989-12-22 信号遅延回路及び該回路を用いたクロック信号発生回路
JP331131/89 1989-12-22

Publications (3)

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EP0379169A2 EP0379169A2 (fr) 1990-07-25
EP0379169A3 EP0379169A3 (en) 1990-11-22
EP0379169B1 true EP0379169B1 (fr) 1996-09-04

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EP90100915A Expired - Lifetime EP0379169B1 (fr) 1989-01-17 1990-01-17 Circuit retardeur de signaux utilisant un circuit pompe de charge

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US (1) US5059838A (fr)
EP (1) EP0379169B1 (fr)
JP (1) JP2635789B2 (fr)
DE (1) DE69028324T2 (fr)

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Also Published As

Publication number Publication date
US5059838A (en) 1991-10-22
JPH02276311A (ja) 1990-11-13
EP0379169A2 (fr) 1990-07-25
JP2635789B2 (ja) 1997-07-30
DE69028324D1 (de) 1996-10-10
DE69028324T2 (de) 1997-02-20
EP0379169A3 (en) 1990-11-22

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