EP0356556B1 - Multieingangs-Vier-Quadranten-Multiplizierer - Google Patents

Multieingangs-Vier-Quadranten-Multiplizierer Download PDF

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Publication number
EP0356556B1
EP0356556B1 EP88114225A EP88114225A EP0356556B1 EP 0356556 B1 EP0356556 B1 EP 0356556B1 EP 88114225 A EP88114225 A EP 88114225A EP 88114225 A EP88114225 A EP 88114225A EP 0356556 B1 EP0356556 B1 EP 0356556B1
Authority
EP
European Patent Office
Prior art keywords
transistor
emitter
terminal
case
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP88114225A
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German (de)
English (en)
French (fr)
Other versions
EP0356556A1 (de
Inventor
Richard Dipl.-Ing. Stepp
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to DE88114225T priority Critical patent/DE3885280D1/de
Application filed by Siemens AG filed Critical Siemens AG
Priority to AT88114225T priority patent/ATE96558T1/de
Priority to EP88114225A priority patent/EP0356556B1/de
Priority to ES88114225T priority patent/ES2045047T3/es
Priority to US07/393,607 priority patent/US5115409A/en
Priority to JP1222781A priority patent/JPH02113382A/ja
Priority to DK426489A priority patent/DK426489A/da
Priority to PT91582A priority patent/PT91582B/pt
Priority to FI894071A priority patent/FI894071A/fi
Publication of EP0356556A1 publication Critical patent/EP0356556A1/de
Application granted granted Critical
Publication of EP0356556B1 publication Critical patent/EP0356556B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division
    • G06G7/163—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division using a variable impedance controlled by one of the input signals, variable amplification or transfer function
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06J—HYBRID COMPUTING ARRANGEMENTS
    • G06J1/00—Hybrid computing arrangements

Definitions

  • the invention relates to a four-quadrant multiplier with more than two signal inputs for multiplying an input signal by a plurality of further input signals, at the output of which the individual multiplication results are additively linked, according to the preamble of patent claim 1.
  • Such multipliers are e.g. in the modulation of different signals on a common carrier or the detection of signals with different frequencies that are modulated on a carrier.
  • Figure 1 shows such a known circuit.
  • a first and a second transistor T1 and T2 and a third and a fourth transistor T3 and T4 each form a differential amplifier pair with directly connected emitters.
  • the collector terminal of the first transistor T1 is connected to the collector terminal of the third transistor T3 and connected via a first resistor R1 to a supply potential Uv and forms a signal output terminal + z.
  • the collector connection of the second transistor T2 is also the collector terminal of the fourth transistor T4 connected together, connected to the supply potential Uv via a second resistor R2 and forms another signal output terminal -z, which together with the signal output terminal + z can provide a symmetrical output signal.
  • the base connections of these transistors do not represent a linear signal input.
  • the base connection of the first transistor T1 is connected to the base connection of the fourth transistor T4 and connected to the collector terminal of the fifth transistor T5 and connected via a first diode D1 to a current source which, in particular, connects a third resistor R3 connected to the supply potential Uv with another terminal.
  • the base connection of the second transistor T2 is connected together with the base connection of the third transistor T3 and the collector connection of a sixth transistor T6 and connected via a second diode D2 to said third resistor R3 or said current source.
  • the emitter connections of the fifth transistor T5 and the sixth transistor T6 are either connected to one another via a resistor and each connected to the reference potential via a separate current source, or, as shown in FIG. 1, connected to one another via a fourth resistor Rx1 and a fifth resistor Rx2 , wherein the connection node of the resistors Rx1 and Rx2 is connected to the reference potential (ground) via a first constant current source I1.
  • the base terminal of the sixth transistor T6 thus forms the first input terminal + x and the base terminal of the fifth transistor T5 forms a second input terminal -x of the multiplier.
  • a symmetrical input signal can be fed in via the terminals + x and -x, the multiplier having linear transmission properties with respect to this signal input.
  • the emitter connections of the transistors T1 and T2 are connected to the collector connection of a seventh transistor T7.
  • the emitter connections of transistors T3 and T4 are connected to the collector connection of an eighth transistor T8.
  • the emitter connections of the transistors T7 and T8 are connected together via a coupling resistor Ry.
  • the emitter connection of the seventh transistor T7 is connected to the reference potential via a second constant current source I2 and the emitter connection of the eighth transistor T8 is connected to the reference potential via a third constant current source I3.
  • the base terminal of the seventh transistor T7 forms the third input terminal + y and the base terminal of the eighth transistor T8 forms the fourth input terminal -y of the multiplier.
  • a symmetrical input signal can be fed in via the terminals + y and -y, the multiplier also having linear transmission properties with respect to this signal input due to the negative feedback caused by the coupling resistance Ry.
  • Circuits of this type are particularly suitable for multiplying at least one digital input signal by another input signal.
  • a corresponding number of such known multipliers could be interconnected.
  • this interconnection of several multipliers has certain disadvantages, which have a particularly negative effect when used as a detector or modulator.
  • Transistors or diodes manufactured in one operation and on a chip are very similar, but the slightly different large signal behavior, the scattering of the amplification factors etc. of the individual transistors, especially if many transistors are connected appropriately, among other things, for different DC voltages Offsets in individual amplifier stages and also the individual signal inputs of the overall multiplier circuit are weighted differently. Since the DC voltage offset is problematic in such circuits anyway, the overlay makes itself felt several different DC voltage offsets are particularly noticeable.
  • the object of the invention is to provide a multiplier for multiplying an input signal by a plurality of further input signals, the individual multiplication results to be provided in an additively linked manner at the output, in which these disadvantages do not occur or are reduced to a non-disturbing extent.
  • Figure 2 shows the subject matter of claim 1, which is particularly suitable for processing rectangular or digital signals.
  • Figure 3 shows the subject matter of claim 2.
  • Circuit elements which fulfill the same or a similar function are provided with the same or similar reference symbols in FIG. 1, FIG. 2 and FIG. 3.
  • the particular advantage of the circuits according to the invention lies in the fact that the transistors T1, T2, T3 and T4 connected in a corresponding control circuit in the form of a Gilbert cell are designed as multi-emitter transistors for this special application.
  • the circuit complexity and the chip area requirement of circuits according to the invention is thus hardly greater than that of single-stage multipliers.
  • a multi-emitter transistor as a component of a differential amplifier is known from DE-A-3030115.
  • the input signal which is fed in at the input terminals + x / -x, is multiplicatively mixed with the input signals, which are fed in at the terminals + y1 / -y1, + y2 / -y2 etc., or multiplied in the linear control range . Since the collector currents of the transistors T1, T2, T3 and T4 each contain the sum of their emitter currents, the individual multiplication products are provided additively linked at the output terminals + z / -z.
  • the multiplication product of the input signal fed in at the input + x / -x with an input signal fed in at another signal input is added to the other multiplication products which are formed from the input signal by the input + x / -x and the input signals of the remaining signal inputs subtracted, is only due to the sign of the individual input signal.
  • the sign can be reversed by swapping the input terminals, for example + y1 with -y1.
  • the circuit shown in FIG. 3 and described in claim 2 is particularly suitable for applications in which the transmission behavior of the multiplier is to be linear with respect to the individual inputs.
  • This linear transmission behavior with respect to the inputs + y1 / -y1, + y2 / -y2, etc. is ensured in particular by the negative feedback which the coupling resistors Ry1, Ry2, ... bring about.
  • controllable current sources Is21, Is22, ... Is31, Is32, ... may be in the form of conventional constant current sources which are switched on or off depending on the signal level to be fed in in each case.
  • the collector of a transistor Tx is provided as the current input of these controllable current sources Is21, ..., the emitter of which is connected to another potential, in particular the reference potential and at the same time to the emitter of a further transistor Ty, the base connection of the transistor Tx being connected to the base connection and the collector connection of the transistor Ty is connected together and forms the control input of this current source and this control input is connected to the supply potential Uv via a resistor Rv, for example the control input of the current source constructed in this way can directly from the output of a logic gate, in particular an I2L gate G1, G2 , ... can be controlled.
  • an inverting input terminal -y1, -y2, ... can be controlled with the output signal of a logic gate G1, G2, ... and a non-inverting input terminal + y1, + y2, ... with the output signal of this logic gate G1, G2, ... which is inverse to this output signal.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Power Engineering (AREA)
  • Evolutionary Computation (AREA)
  • Automation & Control Theory (AREA)
  • Fuzzy Systems (AREA)
  • Amplitude Modulation (AREA)
  • Complex Calculations (AREA)
  • Cylinder Crankcases Of Internal Combustion Engines (AREA)
  • Earth Drilling (AREA)
  • Magnetic Resonance Imaging Apparatus (AREA)
  • Luminescent Compositions (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
  • Processing Of Color Television Signals (AREA)
  • Logic Circuits (AREA)
  • Measurement Of Velocity Or Position Using Acoustic Or Ultrasonic Waves (AREA)
  • Error Detection And Correction (AREA)
  • Devices For Checking Fares Or Tickets At Control Points (AREA)
EP88114225A 1988-08-31 1988-08-31 Multieingangs-Vier-Quadranten-Multiplizierer Expired - Lifetime EP0356556B1 (de)

Priority Applications (9)

Application Number Priority Date Filing Date Title
AT88114225T ATE96558T1 (de) 1988-08-31 1988-08-31 Multieingangs-vier-quadranten-multiplizierer.
EP88114225A EP0356556B1 (de) 1988-08-31 1988-08-31 Multieingangs-Vier-Quadranten-Multiplizierer
ES88114225T ES2045047T3 (es) 1988-08-31 1988-08-31 Multiplicador de cuatro cuadrantes de entradas multiples.
DE88114225T DE3885280D1 (de) 1988-08-31 1988-08-31 Multieingangs-Vier-Quadranten-Multiplizierer.
US07/393,607 US5115409A (en) 1988-08-31 1989-08-14 Multiple-input four-quadrant multiplier
JP1222781A JPH02113382A (ja) 1988-08-31 1989-08-28 ４象限乗算器
DK426489A DK426489A (da) 1988-08-31 1989-08-30 Multiindgangs-firekvadrant-multiplikator
PT91582A PT91582B (pt) 1988-08-31 1989-08-30 Multiplicador de quatro quadrantes com varias entradas
FI894071A FI894071A (fi) 1988-08-31 1989-08-30 Fyrkvadrantmultiplicerare med flere ingaongar.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP88114225A EP0356556B1 (de) 1988-08-31 1988-08-31 Multieingangs-Vier-Quadranten-Multiplizierer

Publications (2)

Publication Number Publication Date
EP0356556A1 EP0356556A1 (de) 1990-03-07
EP0356556B1 true EP0356556B1 (de) 1993-10-27

Family

ID=8199251

Family Applications (1)

Application Number Title Priority Date Filing Date
EP88114225A Expired - Lifetime EP0356556B1 (de) 1988-08-31 1988-08-31 Multieingangs-Vier-Quadranten-Multiplizierer

Country Status (9)

Country Link
US (1) US5115409A (da)
EP (1) EP0356556B1 (da)
JP (1) JPH02113382A (da)
AT (1) ATE96558T1 (da)
DE (1) DE3885280D1 (da)
DK (1) DK426489A (da)
ES (1) ES2045047T3 (da)
FI (1) FI894071A (da)
PT (1) PT91582B (da)

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JP2964573B2 (ja) * 1990-07-19 1999-10-18 日本電気株式会社 コスタスループ搬送波再生回路
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JP2661394B2 (ja) * 1991-04-08 1997-10-08 日本電気株式会社 掛算回路
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JP3880730B2 (ja) * 1998-08-14 2007-02-14 三菱電機株式会社 ４象限掛算回路
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US6704558B1 (en) 1999-01-22 2004-03-09 Parkervision, Inc. Image-reject down-converter and embodiments thereof, such as the family radio service
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Also Published As

Publication number Publication date
ATE96558T1 (de) 1993-11-15
EP0356556A1 (de) 1990-03-07
FI894071A0 (fi) 1989-08-30
PT91582A (pt) 1990-03-08
PT91582B (pt) 1995-07-18
ES2045047T3 (es) 1994-01-16
FI894071A (fi) 1990-03-01
DE3885280D1 (de) 1993-12-02
DK426489D0 (da) 1989-08-30
JPH02113382A (ja) 1990-04-25
US5115409A (en) 1992-05-19
DK426489A (da) 1990-03-01

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