EP0320329A2 - Indicateur d'inactivité de processeur de signal numérique en temps réel - Google Patents

Indicateur d'inactivité de processeur de signal numérique en temps réel Download PDF

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Publication number
EP0320329A2
EP0320329A2 EP88402945A EP88402945A EP0320329A2 EP 0320329 A2 EP0320329 A2 EP 0320329A2 EP 88402945 A EP88402945 A EP 88402945A EP 88402945 A EP88402945 A EP 88402945A EP 0320329 A2 EP0320329 A2 EP 0320329A2
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EP
European Patent Office
Prior art keywords
processor
idle
data output
state
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP88402945A
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German (de)
English (en)
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EP0320329A3 (fr
Inventor
Matthew J.J. Vea
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nortel Networks Ltd
Original Assignee
Northern Telecom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Northern Telecom Ltd filed Critical Northern Telecom Ltd
Publication of EP0320329A2 publication Critical patent/EP0320329A2/fr
Publication of EP0320329A3 publication Critical patent/EP0320329A3/fr
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
    • G06F11/3419—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment by assessing time
    • G06F11/3423—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment by assessing time where the assessed time is active or idle time

Definitions

  • This invention relates to arrangements which measure the loading of a digital signal processor.
  • Digital signal processors e.g., microprocessors
  • Such processors can be used to perform a variety of functions.
  • the flexibility provided by a processor is often advantageously used to augment the functions provided by a system, or to perform those functions using complex algorithms.
  • the same processor used to perform the filtering can also be used to perform other related (and even unrelated) functions. For example, it may be desirable to use the processor to generate signalling tones for various applications, to provide system status information (e.g., to illuminate indicators or drive alphanumeric displays), to receive and process user commands, or the like.
  • the processor can be used to perform far more complex filtering and other functions than could be performed cost effectively with analog circuitry.
  • the processor is capable of executing an instruction every microsecond (10 ⁇ 6 seconds) and the incoming signal to be filtered is sampled once every millisecond (10 ⁇ 3 seconds).
  • Processor loading would then be approximately 50% (or perhaps slightly above 50% due to additional overhead tasks the processor must perform). If the incoming signal sampling rate is increased to one sample every 0.5 milliseconds, the processor loading will increase to around 100%.
  • Diagnostic programs which run concurrently with a processor's normal programming in order to measure processor loading are generally known.
  • This type of diagnostic program may be called by an operating system program (if one is provided), or alternatively, may be interrupt driven and called periodically (e.g., whenever a timer times out).
  • the diagnostic program may measure various parameters of processor loading (e.g., count processor cycles, and/or read the contents of processor work areas such as status register, stack contents, and the like) and, based on these (and other) parameters, calculate an indication of instantaneous or average loading. A history of such indications may be stored and analyzed to provide a measure of processor loading under various operating conditions.
  • diagnostic programs are generally complex and typically themselves add significantly to processor loading -- causing the indications they provide to be inaccurate in some circumstances and adding to processor loading during measurements.
  • a program which determines processor loading by counting processor cycles may underestimate the loading of a very busy processor because the processor may have insufficient resources to increment the cycle counter.
  • a further shortcoming of such diagnostic programs is that they attempt to estimate how much of the time a processor is busy -- whereas in most cases a more relevant inquiry is how much time the processor is not busy (and is therefore available to perform additional tasks).
  • the present invention provides these and other advantageous features by including diagnostic instructions in the processor "idle loop.”
  • a processor does not cease performing instructions when it is not busy, but instead jumps or "traps" to a so-called “idle loop" whenever it is idle.
  • the idle loop generally consists of instructions which perform no useful function (e.g., "no operation,” delay and/or jump instructions).
  • the processor When the processor must perform a function, it receives an "interrupt" -- at which time it ceases performing instructions in the idle loop and begins performing other, useful program control instructions. The next time the processor has no further tasks to perform, it once again returns to its idle loop.
  • the present invention includes instructions in the processor idle loop which control the processor (or external circuitry associated with the processor) to measure the amount (or percentage) of time the processor operates in the idle loop.
  • instructions in the processor idle loop control the processor to alternate a processor data output between output states.
  • the processor data output alternates between states whenever the processor is idle, and remains in the same state when the processor is performing useful tasks.
  • a frequency counter or other indicating device e.g., a light emitting diode
  • responsive to the rate of processor data output state change may be used to directly indicate the amount of time the processor is idle relative to the total amount of processing time.
  • the processor performs the idle loop instructions only when it has nothing else to do
  • the additional idle loop instructions add nothing to processor loading and the load detecting arrangement accordingly is completely transparent to the operation of the processor.
  • the idle loop instructions directly measure the amount of time the processor spends in an idle state relative to the total amount of processing time -- and therefore provide an extremely useful, direct indication of spare processing capacity.
  • FIGURE 1 is a schematic block diagram of the presently preferred exemplary embodiment of a digital signal processing system 10 in accordance with the present invention.
  • System 10 includes a central processing unit ("CPU") or processor 12.
  • Processor 12 may, for example, be a conventional microprocessor including a read only memory program store 12a, internal registers and an arithmetic logic unit, etc. -- or virtually any other type of device which processes digital signals.
  • a conventional clock signal generator 13 produces a periodically-alternating digital clock synchronization signal which drives processor 12. The frequency (that is -- the period) of this clock signal determines the time it takes for the processor 12 to execute each of its program control instructions.
  • processor 12 may be connected to a variety of associated conventional external circuits which perform various desired functions. For example, if processor 12 is to be used to provide digital filtering, it may be connected to the output of an analog-to-digital converter or other source of digitized signals (not shown). Processor 12 may also be connected to display devices, input/output peripheral devices, or virtually any of the thousands of different devices designed to be interfaced with a processor (all as is well known to those skilled in this art).
  • processor 12 includes at least one unused data output connection P1 which is connected to the input of a conventional input/output (I/O) register 14.
  • I/O register 14 is sensitive to the "edges" (transitions) of the P1 output of processor 12 and produces an output signal "BIT" which changes state in response to those edges.
  • register 14 buffers the signal outputted at the processor P1 data output, but does not alter the frequency of that signal (and may but need not necessarily synchronize the signal to the processor clock).
  • the register 14 "BIT" output is connected to the input of a frequency counter 16 operating as an event counter with a fixed gate time (of, e.g., 10 seconds).
  • the "BIT" signal output of register 14 is also connected to a visual indicating circuit 18 (which can conveniently be provided on the same board as processor 12) providing a rough visual indication of processor idle percentage.
  • Indicating circuit 18 in the preferred embodiment includes an exclusive OR (“XOR”) gate 20 the inputs of which are connected across a resistor 22.
  • the "BIT" signal is connected to a first input of XOR gate 20, and a second input of the XOR gate is connected through a capacitor 24 to ground potential.
  • This input configuration of XOR gate 20 causes the XOR gate to produce a pulse whenever a transition occurs in the "BIT" output signal (since the XOR gate first input immediately changes levels to track a level change of the "BIT” signal, but the gate second input changes state only after a delay determined by the RC time constant of resistor 22 and capacitor 24).
  • the output of XOR gate 20 is connected through a current limiting series resistor 26 to the anode of a light emitting diode (LED) 28 -- the LED cathode being connected to ground potential.
  • An optional driver/buffer amplifier 30 may be used to connect the output of XOR gate 20 to the frequency counter 16 input in lieu of a direct connection between the counter input and the register 14 "BIT" signal output.
  • frequency counter 16 is only connected when an exact load measurement is desired, while indicating circuit 18 is continuously connected to I/O register 14 so as to provide a constant visual indication of processor idle percentage.
  • FIGURE 2 is a schematic flowchart of exemplary program control steps performed by processor 12 whenever the processor is in an idle state.
  • processor 12 executes a section of code beginning at a predetermined address (of its associated read only memory program store 12a) whenever it is at idle and is not required to perform useful tasks.
  • Program control instructions specifying the tasks shown in the FIGURE 2 flowchart are loaded into the program store 12a beginning at that predetermined address and are therefore executed whenever processor 12 is at idle.
  • Processor 12 is "interrupt driven” in the preferred embodiment, meaning that it begins executing program control instructions stored in a portion of program store 12a other than that portion storing the instructions executed during idle in response to the occurrence of an external event (e.g., receipt of input data to be processed).
  • an external event e.g., receipt of input data to be processed.
  • a device external to processor 12 e.g., a conventional I/O controller not shown
  • IRQ processor interrupt request
  • the presence of an active signal level on this interrupt request input causes the microprocessor to cease executing the "idle” routine and to "trap" to an interrupt handler routine stored in a different portion of program store 12a.
  • the interrupt handler routine either itself performs desired processing (e.g., to process the input data which caused an I/O interrupt to be generated) or alternatively, transfers program control to additional routines (also stored in program store 12a) which perform the desired processing.
  • processor 12 When processing is completed, processor 12 once again returns to executing the idle routine.
  • the FIGURE 2 idle routine is very short in the preferred embodiment.
  • a first step 50 writes a logic level one to processor data output connection P1.
  • a second step 52 writes a logic level zero to the processor data output connection P1. The routine then jumps back to the first step 50 to repeat steps 50, 52.
  • processor data output P1 to "toggle” (that is -- alternate between binary values 0 and 1) at a rate proportional to the processor clock rate whenever the processor 12 is idling, and causes data output P1 to remain constant when the processor is performing useful tasks.
  • processor 12 has a one megahertz clock frequency, executes the "set” and “reset” commands each in one cycle time (one microsecond), and executes the "jump" command in two cycle times (two microseconds).
  • the total time required to execute the "idle loop" consisting of these three instructions one time is four microseconds, and a single loop execution will cause data output P1 to alternate once between logic level 0 and logic level 1 (e.g., from 0 to 1 to 0, or from 1 to 0 to 1) -- resulting in a signal of one-quarter the processor clock frequency being generated whenever (and only when) the processor has nothing to do and is idling.
  • logic level 0 and logic level 1 e.g., from 0 to 1 to 0, or from 1 to 0 to 1
  • the signal present on the processor P1 output does not have a 50% duty cycle in the preferred embodiment even when processor 12 is 100% idling and the idle endless loop steps shown in FIGURE 2 are performed continuously. This is because the P1 output state remains constant during the time processor 12 executes the "jump" instruction.
  • the P1 output rises to logic level 1 only while processor 12 executes the "reset” instruction (that is, during the processor cycle immediately after the "set” instruction has been performed).
  • the P1 output then falls to logic level 0 immediately after the "reset” instruction executes -- and remains at logic level 0 during the time the "jump” instruction is executed as well as during the time the "set” instruction is performed. It is for this reason that frequency counter 16 (and indicating circuit 18 ) is sensitive to transitions in the "BIT" signal rather than to some other characteristic of that signal.
  • Frequency counter 16 in the preferred embodiment directly indicates the percentage of time processor 12 is idle relative to the total processing time by counting edges of the signal "BIT" produced by I/O register 14. If the processor is 100% idle, then edges (e.g., leading edges) will occur at the rate of 1/T where T is the time required by processor 12 to execute the idle loop instructions once (e.g., 4 microseconds in the example given above -- which equals the time required to perform a set bit instruction + the time required to perform a reset bit instruction + the time required to perform a jump instruction in the preferred embodiment). As the processor 12 does more and more real work, it spends less time executing the idle loop instructions -- and the edges occur proportionately less often in direct ratio to the amount of idle time which remains.
  • T is the time required by processor 12 to execute the idle loop instructions once (e.g., 4 microseconds in the example given above -- which equals the time required to perform a set bit instruction + the time required to perform a reset bit instruction + the time required to perform a jump instruction in the preferred embodiment
  • frequency counter 16 receives one pulse (edge) every 4 microseconds when processor 12 is 100% idle (as described in the example above).
  • frequency counter 16 has a gate time of 10 seconds (selected to provide a desired degree of averaging over time). With processor 12 100% idle, frequency counter 16 will count 2.5 x 106 pulses (edges) over the ten second gate time (one pulse every 4 microseconds means 250,000 pulses every second, or 2.5 million pulses every ten seconds). Note that it is helpful for this calculation to know (at least approximately) the relationship between the processor clock frequency and the gate time, as well as the number of clock cycles required to execute the idle loop in its entirety.
  • a waveform of the "BIT" signal for 100% idling of processor 12 is shown in FIGURE 3A.
  • frequency counter 16 counts 1.25 x 106 pulses (edges) during its ten second gate time. This count indicates that over the ten second gate time, processor 12 was 50% idle on the average. As is shown in FIGURE 3B, this 50% idling condition does not halve the instantaneous frequency of the "BIT" signal. Rather, the "BIT" signal is generated at substantially the same frequency whenever processor 12 is idling in the preferred embodiment. However, processor 12 ceases to produce the "BIT" signal altogether during times when it is performing real work (i.e., useful tasks) rather than idling. When the frequency of the "BIT" signal is averaged (integrated) over a time period which is long relative to the time between processor clock pulses, the result is a highly accurate indication of average processor idle percentage.
  • LED 28 will obviously not provide as accurate an estimate of processor idle time as that provided by frequency counter 16. However, the LED 28 does provide an indicator which is also very helpful. If LED 28 is fully lit, processor 12 is nearly 100% idle (the LED will actually have an on-off duty cycle of about 50% under this condition, but the alternations are so rapid as to be undetectable by the human eye). If LED 28 is dark or nearly dark, processor 12 is 0% idle. If LED 28 is at half brightness compared to the 100% condition, processor 12 is operating at 50% idle.
  • Such a detector may compare the ratio of the processor clock frequency to the frequency of the "BIT" signal to provide an indication of the percentage of processor time spent idling.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
EP19880402945 1987-12-08 1988-11-24 Indicateur d'inactivité de processeur de signal numérique en temps réel Withdrawn EP0320329A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US130153 1987-12-08
US07/130,153 US4924428A (en) 1987-12-08 1987-12-08 Real time digital signal processor idle indicator

Publications (2)

Publication Number Publication Date
EP0320329A2 true EP0320329A2 (fr) 1989-06-14
EP0320329A3 EP0320329A3 (fr) 1990-12-05

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US (1) US4924428A (fr)
EP (1) EP0320329A3 (fr)
JP (1) JPH01303536A (fr)
CN (1) CN1014101B (fr)
CA (1) CA1297988C (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0762286A1 (fr) * 1995-08-24 1997-03-12 Sun Microsystems, Inc. Mesure de l'utilisation directe et indirecte d'une unité centrale de traitement
EP0729131A3 (fr) * 1994-12-02 1999-01-13 Sony Corporation Source sonore électronique ayant des émissions parasites diminuées
DE19757876A1 (de) * 1997-12-24 1999-07-08 Bosch Gmbh Robert Verfahren zur Ermittlung der Auslastung eines Rechengeräts
EP1376314A1 (fr) * 2002-06-28 2004-01-02 Kabushiki Kaisha Toshiba Méthode et appareil électronique de contrôle de fréquence d'horloge
GB2393292A (en) * 2002-07-23 2004-03-24 Hewlett Packard Development Co Hardware based processor utilization system
US7143411B2 (en) * 2002-03-15 2006-11-28 Hewlett-Packard Development Company, L.P. Capping processor utilization

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US5072376A (en) * 1988-06-10 1991-12-10 Amdahl Corporation Measuring utilization of processor shared by multiple system control programs
US5222239A (en) * 1989-07-28 1993-06-22 Prof. Michael H. Davis Process and apparatus for reducing power usage microprocessor devices operating from stored energy sources
US6158012A (en) * 1989-10-30 2000-12-05 Texas Instruments Incorporated Real-time power conservation and thermal management for computers
US5218704A (en) * 1989-10-30 1993-06-08 Texas Instruments Real-time power conservation for portable computers
US5517629A (en) * 1992-08-26 1996-05-14 Boland; R. Nick K. Methods for analyzing computer program performance
US6895520B1 (en) * 2001-03-02 2005-05-17 Advanced Micro Devices, Inc. Performance and power optimization via block oriented performance measurement and control
US7487504B2 (en) * 2002-02-06 2009-02-03 International Business Machines Corporation Thread dispatch for multiprocessor computer systems
CN100337210C (zh) * 2003-03-27 2007-09-12 华为技术有限公司 实时监测处理器运算负荷的方法
US7272751B2 (en) * 2004-01-15 2007-09-18 International Business Machines Corporation Error detection during processor idle cycles
US7761874B2 (en) * 2004-08-13 2010-07-20 Intel Corporation Managing processing system power and performance based on utilization trends
JP2020046752A (ja) * 2018-09-14 2020-03-26 キオクシア株式会社 記憶装置及び情報処理システム
CN111954337B (zh) * 2019-05-16 2022-11-15 安沛科技股份有限公司 用于单线串接发光二极管驱动电路的控制方法

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JPS6027960A (ja) * 1983-07-27 1985-02-13 Hitachi Ltd プロセツサ使用率測定方法
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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0729131A3 (fr) * 1994-12-02 1999-01-13 Sony Corporation Source sonore électronique ayant des émissions parasites diminuées
EP0762286A1 (fr) * 1995-08-24 1997-03-12 Sun Microsystems, Inc. Mesure de l'utilisation directe et indirecte d'une unité centrale de traitement
US5797115A (en) * 1995-08-24 1998-08-18 Fuller; Billy Measuring direct and indirect usage of a central processing unit
DE19757876A1 (de) * 1997-12-24 1999-07-08 Bosch Gmbh Robert Verfahren zur Ermittlung der Auslastung eines Rechengeräts
DE19757876C2 (de) * 1997-12-24 2002-06-20 Bosch Gmbh Robert Verfahren zur Ermittlung der Auslastung eines Rechengeräts
US7143411B2 (en) * 2002-03-15 2006-11-28 Hewlett-Packard Development Company, L.P. Capping processor utilization
EP1376314A1 (fr) * 2002-06-28 2004-01-02 Kabushiki Kaisha Toshiba Méthode et appareil électronique de contrôle de fréquence d'horloge
US7228445B2 (en) 2002-06-28 2007-06-05 Kabushiki Kaisha Toshiba Clock frequency control method and electronic apparatus
GB2393292A (en) * 2002-07-23 2004-03-24 Hewlett Packard Development Co Hardware based processor utilization system
US6816809B2 (en) 2002-07-23 2004-11-09 Hewlett-Packard Development Company, L.P. Hardware based utilization metering
GB2393292B (en) * 2002-07-23 2005-11-30 Hewlett Packard Development Co Hardware based utilization metering
US8463578B2 (en) 2002-07-23 2013-06-11 Hewlett-Packard Development Company, L.P. Hardware based utilization metering

Also Published As

Publication number Publication date
CN1014101B (zh) 1991-09-25
JPH01303536A (ja) 1989-12-07
EP0320329A3 (fr) 1990-12-05
CA1297988C (fr) 1992-03-24
CN1033890A (zh) 1989-07-12
US4924428A (en) 1990-05-08

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