EP0278438A2 - Dispositif pour enregistrement multiples dans un instrument de musique électronique - Google Patents

Dispositif pour enregistrement multiples dans un instrument de musique électronique Download PDF

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Publication number
EP0278438A2
EP0278438A2 EP88101717A EP88101717A EP0278438A2 EP 0278438 A2 EP0278438 A2 EP 0278438A2 EP 88101717 A EP88101717 A EP 88101717A EP 88101717 A EP88101717 A EP 88101717A EP 0278438 A2 EP0278438 A2 EP 0278438A2
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EP
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Prior art keywords
recording
data
performance information
performance
information
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EP88101717A
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German (de)
English (en)
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EP0278438B1 (fr
EP0278438A3 (en
Inventor
Kazuhisa C/O Yamaha Corporation Okamura
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Yamaha Corp
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Yamaha Corp
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Priority claimed from JP62024867A external-priority patent/JPH0797270B2/ja
Priority claimed from JP62024866A external-priority patent/JP2570718B2/ja
Priority claimed from JP62024865A external-priority patent/JPH0797269B2/ja
Application filed by Yamaha Corp filed Critical Yamaha Corp
Publication of EP0278438A2 publication Critical patent/EP0278438A2/fr
Publication of EP0278438A3 publication Critical patent/EP0278438A3/en
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    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10H—ELECTROPHONIC MUSICAL INSTRUMENTS; INSTRUMENTS IN WHICH THE TONES ARE GENERATED BY ELECTROMECHANICAL MEANS OR ELECTRONIC GENERATORS, OR IN WHICH THE TONES ARE SYNTHESISED FROM A DATA STORE
    • G10H1/00—Details of electrophonic musical instruments
    • G10H1/18—Selecting circuits
    • G10H1/26—Selecting circuits for automatically producing a series of tones
    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10H—ELECTROPHONIC MUSICAL INSTRUMENTS; INSTRUMENTS IN WHICH THE TONES ARE GENERATED BY ELECTROMECHANICAL MEANS OR ELECTRONIC GENERATORS, OR IN WHICH THE TONES ARE SYNTHESISED FROM A DATA STORE
    • G10H1/00—Details of electrophonic musical instruments
    • G10H1/0033—Recording/reproducing or transmission of music for electrophonic musical instruments

Definitions

  • the present invention generally relates to a recording apparatus for recording musical tones generated by an electronic musical instrument which is played based on performance information inputted from a keyboard or a computer, and more particularly to a multi-recording apparatus capable of multi-recording inputted musical tones in addition to pre-recorded musical tones.
  • an automatic performance apparatus as disclosed in Japanese Patent Application Laid-Open No. 58- 211191 is known as a conventional performance recording and reproducing apparatus.
  • This conventional apparatus provides a performance data memory for storing key data representative of the depressed keys, key event timing data representative of key-on and key-off timings of each key and tone generating channel data representative of a channel of a tone generating circuit, whereby a musical tone having a different tone color can be recorded on and reproduced from each channel.
  • the above conventional apparatus is merely a performance recording apparatus, hence, the conventional apparatus is disadvantageous in that the conventional apparatus can not record new musical tones on a pre-recorded channel while reproducing the pre-recorded musical tones. More specifically, the conventional apparatus can record performance information on plural recording channels based on a time-division system, and the conventional apparatus can simultaneously reproduce the recorded performance information from such plural recording channels.
  • the conventional apparatus can not perform a real multi-recording. More specifically, the conventional apparatus can not record newly inputted information on the pre-recorded channel while reproducing pre-recorded information from such pre-recorded channel.
  • By increasing a channel number it is possible to obtain an advantage similar to that of the multi-recording.
  • the information of the pre-recorded channel is read from a desirable bank of a memory, and then the read information is reformed with the inputted performance data.
  • Such reformed information is temporarily written into the non-recorded channel, and then such reformed information is transferred to the original bank at a time when a recording mode is completed.
  • timing data after the above-­mentioned reformation are calculated out based on a clock value at every time when each event data are written in. Therefore, if an event number is increased or writing timings are delayed due to processes for inputted data or switching operations, a time interval among pre-recorded event information must be extended. As a result, a performance period of whole musical tune must be changed.
  • the conventional apparatus does not output the inputted performance information but generates musical tones corresponding to the inputted performance information by an input unit such as a keyboard performance unit in a recording period. Hence, the conventional apparatus can not reproduce the musical tones similar to the recorded musical tones.
  • the conventional apparatus when a recording is completed while a player keeps a key depressing in the recording period, the conventional apparatus must keep a musical tone corresponding to the depressed key generating at a time when a performance is completed in a reproducing period. Similarly, when a reproducing is completed while a reproduced musical tone is kept generating, such reproduced musical tone must be kept generating.
  • a multi-recording apparatus of an electronic musical instrument comprising (a) memory means for recording performance information and generation timing information together, the performance information representing musical tones generated by playing external performance means, the generation timing information representing a generation timing when the performance information is generated; (b) measuring means for measuring a timing when the performance information is newly inputted from the external performance means as first generation timing when the inputted performance information is generated; (c) reproducing control means for reproducing the performance information pre-recorded in the memory means in accordance with the generation timing information; (d) extracting means for extracting second generation timing information from reproduced performance information; and (e) recording control means for simultaneously recording both of the inputted performance information and the reproduced performance information with third generation timing information in the memory means, the third generation timing information for both of the inputted and reproduced performance information being calculated out so that each generation timing information of each reproduced performance information can be equal to the second generation timing information extracted by the extracting means, whereby musical tones newly inputted from the external performance means are over-
  • a multi-recording apparatus of an electronic musical instrument comprising: (a) a plurality of input channels each inputting performance information, the performance information being identical to event data representing events of depressed or released keys and generation timings of the events; (b) memory means for recording the inputted performance information by every input channel; (c) setting means for selectively permitting recording and reproducing of each input channel in the memory means, the setting means selectively setting one of a recording mode, a reproducing mode and a stop mode; (d) recording control means for reading first performance information from a first input channel which is permitted to be recorded in accordance with clocks pre-stored in the memory means, the recording control means over-recording the read first performance information with newly inputted second performance information on the first input channel in the recording mode; (e) first output control means for selecting the second performance information from a plurality of inputted performance information and outputting the selected second performance information to be recorded on the first input channel within the plurality of input channels in the recording mode; (f) second
  • a multi-recording apparatus of an electronic musical instrument comprising: (a) memory means for recording event data as performance information, the event data representing events of depressed or released keys and generation timings of the events; (b) setting means for selectively setting one of a recording mode, a reproducing mode and a stop mode at least; (c) first storing means for storing first information representative of depressing states of keys which are designated by the performance data inputted from external performance means; (d) recording control means for recording the inputted performance information in the memory means in the recording mode, the recording control means detecting depressed keys based on contents of the first information stored in the first storing means so as to generate and record first releasing information of the depressed keys in the memory means when the recording mode is changed to the stop mode; (e) reading means for reading the performance data from the memory means in accordance with clocks; (f) second storing means for storing second information representative of the depressing states designated by the read performance information; and (g) output control means for out
  • FIG. 1 is a block diagram showing a hardware construction of an embodiment of the multi-recording apparatus of an electronic musical instrument.
  • This multi-recording apparatus shown in Fig. 1 is a so-­called event type recording apparatus which records key-event data and timing data together.
  • the key event data represents depressing and releasing of keys in the keyboard of the electronic musical instrument
  • the timing data represents timings (or time intervals) for generating the key events.
  • the this apparatus reproduces the musical tones from the recorded key event data based on the time intervals represented by the timing data so as to output such reproduced musical tones.
  • the recording is performed based on the key event data inputted from performance information generating means such as the keyboard and the computer.
  • the reproduced key event data are transferred to the computer, a tone source and the like.
  • this apparatus can combine the input data and the reproduced data together so as to generate new recording data and then record such new recording data on an original track (or a channel) from which the reproducing data are read.
  • This apparatus provides eight input terminals for inputting the key event data and eight output terminals for outputting the key event data.
  • Each terminal provides sixteen channels each according to a Musical Instrument Digital Interface (MIDI) standard.
  • MIDI Musical Instrument Digital Interface
  • 128 input units such as the keyboards of the electronic musical instruments
  • 128 output units such as tone sources of the electronic musical instruments
  • each track can be assigned with desirable one input channel and one output channel.
  • Each track can be recorded with data representative of thirty two keys which are simultaneously depressed.
  • this apparatus can be normally connected with 128 equivalent musical instruments, and then this apparatus can select sixty four equivalent musical instruments from 128 equivalent musical instruments so as to record and reproduce the performance played by use of the selected sixty four equivalent musical instrument.
  • a central processing unit (CPU) 10 is provided in order to control operations of whole multi-recording apparatus.
  • This CPU 10 is connected with a program memory 14, registers 16, a sequence memory 18, an input unit 20, an output unit 22, switches 24 and a tempo generator 26 via a bi-­directional bus line 12.
  • the program memory 14 is constructed by a read only memory (ROM) and the like, and this program memory 14 pre-­stores control programs for controlling the CPU 10.
  • ROM read only memory
  • the registers 16 temporarily stores several data which are generated when the CPU 10 executes the above-mentioned control programs. Each of the registers 16 is arranged at a predetermined area within a random access memory (RAM).
  • RAM random access memory
  • the registers 16 provided in this multi-recording apparatus can be described in an alphabet order as follows. In the following thirty one registers, each numeral designates each register and contents of data thereof.
  • the sequence memory 18 is constructed by the RAM so as to record the performance information such as the key codes, for example. As shown in Fig. 7, this sequence memory 18 stores data having a word length of three bytes such as "key-on" data, "key-off” data and “time interval” data; "track change” data having a word length of two bytes; and "end mark” data having a word length of one byte.
  • the first byte within each of the above-mentioned data designates an identifier mark representative of a data kind thereof.
  • the "end mark” is one byte data which are not added with a parameter term and which only represent an identifier mark F2 H .
  • data added with the suffix " H " will represent data of hexadecimal digit.
  • the first byte represents an identifier mark F4 H
  • the second byte represents upper seven bits of the time interval data
  • the third byte represents lower seven bits of the time interval data.
  • the first byte represents an identifier mark FF H and the second byte represents two byte data having track data.
  • Fig. 2 is a front view showing an appearance of an operation panel of this multi-recording apparatus.
  • This operation panel shown in Fig. 2 provides switches 30, 32, 34 and 36 for moving a cursor, an increment (INC) switch 38, a decrement (DEC) switch 40, a PLAY switch 42, a RECORD switch 44, a STOP switch 46 and other operating switches 48 including tempo setting switch.
  • the switches 30, 32, 34 and 36 are provided in order to designate the register TBL (0 to 63, 1 to 5) for setting input/output information of the registers 16.
  • the INC switch 38 and the DEC switch 40 are provided in order to change data stored in the register TBL (CSX, CSY) designated by the cursors CSX and CSY.
  • the PLAY switch 42, the RECORD switch 44 and the STOP switch 46 are provided in order to select desirable performance mode of this multi-recording apparatus.
  • These switches 30 to 48 constitutes the switches 24 shown in Fig. 1.
  • the input unit 20 shown in Fig. 1 consists of eight input terminals Ti1 to Ti8, input buffers INBUF0 to INBUF7, an OR gate 62, an encoder 64 and input interrupt number (INIRQNO) register 66.
  • the input buffers INBUF0 to INBUF7 are constituted by first-in-first-out (FIFO) registers which temporarily store the performance information inputted via the input terminals Ti1 to Ti8 and then sequentially output each bit data of the performance information in accordance with an inputting order.
  • the OR gate 62 detects the inputted performance information and then generates an input interrupt signal INPUTIRQ when the performance information is inputted via one of the input terminals Ti1 to Ti8.
  • the encoder 64 detects one or some numbers of the input buffers which store the inputted performance information within the input buffers INBUF0 to INBUF7.
  • the register 66 temporarily stores such detected input buffer numbers until the inputted performance information is read out from the input buffers.
  • the output unit 22 provides the bi-­directional bus line 12 and output buffers OUTBUF0 to OUTBUF7 connected between the bus line 12 and eight output terminals To1 to To8.
  • the tempo generator 26 consists of a clock setting unit 70 for generating a clock CL having a frequency corresponding to set tempo value, a 8-bit increment counter 72 for counting the clock CL, a NOR gate 74, a counter timer for the recording (hereinafter, referred to as a recording timer RECTIMER), registers PLYTMH and PLYTML, a decrement counter 76, a NOR gate 78, a register 80, an inverter 82 and an AND gate 84.
  • the NOR gate 74 outputs a recording interrupt signal RECIRQ at every time when the count value of the counter 72 becomes equal to a value "0", i.e., data value (00 H ).
  • the recording timer RECTIMER latches the count value of the counter 72.
  • time interval data are read from the sequence memory 18, such time interval data are divided into upper data of upper seven bits and lower data of lower seven bits.
  • the register PLYTMH stores such upper data
  • the register PLYTML stores such lower data.
  • the decrement counter 76 counts down the clock CL.
  • the NOR gate 78 outputs the reproducing interrupt signal PLAYIRQ when the count value of the counter 76 becomes equal to the value "0".
  • the value "1" is set in the register 80 when the reproducing interrupt signal PLAYIRQ is masked in the stop mode.
  • the inverter 82 and the AND gate 84 inhibits the reproducing interrupt signal PLAYIRQ from being outputted.
  • Fig. 6A is a diagram showing the register TBL(x, y) for setting the input/output states of the registers 16 as a table.
  • TRACK NO.” the number of the recording tracks which are set in the sequence memory 18 are written, and this "TRACK NO.” is indicated by the value of the cursor CSX in an actual process.
  • a third column "OUTPUT" the output channels of the data read from the tracks are written.
  • processing contents of the tracks are written.
  • Figs. 6B and 6C shows the processing contents of each track mode.
  • the input data are written into such track corresponding to the track mode of "2(rec)" when the performance mode is set to the recording mode (i.e., JOB equals to "2"), and the internal data of such track are outputted to the output terminal when the performance mode is set to the reproducing or recording mode (i.e., JOB equals to "1" or "2").
  • a first step 100 of the main process shown in Fig. 8 the CPU 10 starts to operate in accordance with the control programs stored in the program memory 12.
  • the CPU 10 initializes the registers 16. More specifically, in the step 101, the CPU 10 sets the output key code buffer OKCBUF (0 to 63, 0 to 31), the register TBL (0 to 63, 0 to 31) for setting the input/­output staes and a reproducing interrupt masking register PIRQMSK, and the CPU 10 also clears the performance mode register JOB. In this case, it is possible to set a predetermined preset value (read from the ROM or an external memory) to these registers. In the step 102, the external memory and the like set the head address SONGTOP and the last address SONGEND of the sequence performance data.
  • the CPU 10 calls and executes each subroutine of an INC/DEC switching process (in a step 110), an UP/DOWN switching process (in a step 130), a LEFT/RIGHT switching process (in a step 140), a PLAY switch-on process (in a step 150), a REC switch-on process (in a step 160) and a STOP switch-on process (in a step 170), and then the CPU 10 executes the other processes (in a step 190). Thereafter, the CPU 10 repeatedly executes the series of the processes in the above-mentioned steps 110 to 190.
  • the INC switch 38 and the DEC switch 40 shown in Fig. 2 are used for changing the input/output states of the register TBL (csx, csy).
  • step 111 the CPU 10 checks whether either the INC switch 38 or the DEC switch 40 is turned on or not.
  • the present process returns to the main process (shown in Fig. 8).
  • the present process advances to a next step 112 wherein the CPU 10 checks the values of the performance mode register JOB and the cursor Y-coordinate CSY.
  • the present process returns to the main process (shown in Fig. 8).
  • the input/output channels are inhibited from being changed in the reproducing or recording cycle.
  • the present process advances to a next step 113 wherein the CPU 10 checks the contents of the cursor Y-coordinate CSY and the input/output information stored in the register TBL(csx, csy).
  • the present process advances to a step 115.
  • the present process advances to a step 114.
  • the INC switch 38 When the INC switch 38 is turned on, the content of the input/output information stored in the register TBL(csx, csy) (hereinafter, simply referred to as content or value of the register TBL(csx, csy)) is increased in the step 114. However, when the DEC switch 40 is turned on, the content of the register TBL(csx, csy) is decreased in the step 114. After executing the process in the step 114, the present process will return to the main process.
  • the value of the register TBL(csx, csy) is increased or decreased in the following ranges in accordance with the value of CSY:
  • the track CSX the track mode of the track having the track number CSX
  • the key-off process is executed on such depressed key in steps 115 to 126.
  • the value "0" is set to the control variable i in the step 115, and then the CPU 10 checks whether the key code is stored in the input key code buffer IKCBUF(csx, i) of the track CSX or not. If the key code is not stored in the input key code buffer IKCBUF(csx, i), the processes in the steps 117 to 124 are not executed but the present process directly advances to the step 125.
  • the key-off data of such stored key code are set to the input data buffers IN1 to IN3 in the step 117, and then the CPU 10 clears the buffer IKCBUF(csx, i) in the step 118.
  • data of 40 H are normally set to the input data buffer IN3 as touch information of the key-off.
  • the CPU 10 reads out data representative of the output terminal of the track CSX and data representative of the MIDI channel from the input/output information register TBL, and then the CPU 10 transfers such two data to the output terminal register OUTTRM and the output channel register OUTCH respectively.
  • the key-off data stored in the input data buffers IN1 to IN3 are converted into data OUTCH only having the MIDI channel data, and then such converted data OUTCH are stored in the output data buffers OUT1 to OUT3 in the step 120.
  • the CPU 10 confirms the performance mode in the step 122.
  • the key-off data set in the input data buffers IN1 to IN3 are written into the sequence memory 18 under the designation of the writing pointer in the step 123.
  • the value of the writing pointer is counted up by "3" in the step 124, and then the present process advances to the next step 125.
  • the processes in the steps 123 and 124 are skipped and the present process directly advances to the step 125.
  • the present process advances to the step 114 wherein the value of the register TBL(csx, csy) is increased or decreased when the switch 38 or 40 is turned on as described before. Thereafter, the present process returns to the main process (shown in Fig. 8) again.
  • the UP switch 34 and the DOWN switch 36 are provided for moving the cursor X-coordinate CSX up and down on the input/output state table shown in Fig. 6A.
  • a step 131 checks the UP switch 34 and the DOWN switch 36.
  • the value of the cursor X-coordinate CSX is increased or decreased in a value range between 0 to 63 when either the switch 34 or 36 is turned on.
  • the present process directly returns to the main process (shown in Fig. 8) from the step 131.
  • the LEFT switch 30 and the RIGHT switch 32 are provided for moving the cursor Y-coordinate CSY right and left on the input/output state table shown in Fig. 6A.
  • the CPU checks the LEFT switch 30 and the RIGHT switch 32 in a step 141.
  • the switch 30 or 32 is turned on, the value of the cursor Y-coordinate CSY is increased or decreased in a value range between 1 to 5 in a step 142.
  • the present process directly returns to the main process (shown in Fig. 8) from the step 141.
  • the CPU 10 judges whether the PLAY switch 42 is turned on or not in a step 151. If the PLAY switch 42 is not turned on, the present process directly returns to the main process (shown in Fig. 8). If the PLAY switch 42 is turned on, the present process advances to a next step 152 wherein the value "1" is set to the performance mode register JOB. In a next step 153, the CPU 10 executes a song start process of a step 200 (which will be described in Fig. 14). Thereafter, the present process returns to the main process again.
  • the CPU 10 judges whether the RECORD switch 44 is turned on or not in a step 161. If the RECORD switch 44 is not turned on, the present process directly returns to the main process. If the RECORD switch 44 is turned on, the present process advances to a next step 162 wherein the value "2" is set to the performance mode register JOB. In a next step 163, the CPU 10 executes the song start process of the step 200 shown in Fig. 14. Thereafter, the present process returns to the main process again.
  • the registers used for the reproducing and the recording are preset at first, and thereafter, the identifier mark at the first byte of the sequence performance data is read from the sequence memory 18. Based on such read identifier mark, the CPU 10 reads several data such as the key-on data, the key-off data, the track change data, the time interval data and the end mark data, and then the CPU 10 executes the processes based on such read data. The above data reading operation of the CPU 10 is repeatedly executed until the time interval data or the end mark data are read.
  • the reading pointer RPT is preset to the head address SONGTOP of the sequence performance data
  • the writing pointer WPT is preset to an address next to the last address SONGEND of the sequence performance data.
  • the value of the writing pointer WPT is stored as a new head address of the sequence performance data.
  • the CPU 10 clears the reproducing interrupt mask PIRQMSK to thereby enable the reproducing interrupt PLAYIRQ in a step 202.
  • the output value of the recording timer RECTIMER (shown in Fig. 5) is stored in the recording time register RECCNT.
  • the CPU 10 clears the lapsed time register LNSAM.
  • the CPU 10 reads one byte data the address of which is designated by the reading pointer RPT, and then such read one byte data are stored in the flag FLG in a step 205.
  • the identifier mark representing the data kind thereof is positioned at the first byte of the sequence performance data stored in the sequence memory 18 as shown in Fig. 7.
  • the CPU 10 judges the contents of data stored in the flag FLG.
  • the present process selectively branches to one of the data reading processes of the track change data (in a step 210), the key-on event data (in a step 220), the key-off event data (in a step 240), the time interval data (in a step 260) and the end mark data (in a step 270).
  • the present process After executing each of the data reading processes of the track change data (in the step 210), the key-on event data (in the step 220) and the key-off event data (in the step 240) and other processes (in a step 280), the present process returns to the step 205 wherein the next data reading process is executed.
  • the present process returns to the main process (shown in Fig. 8) again.
  • the head data of the sequence performance data are normally set by track change data (FF H ).
  • step 206 shown in Figs. 14 and 23 if the CPU 10 judges that the identifier mark is represented by the data FF H , the CPU 10 executes the track change process in the step 210 shown in Fig. 15.
  • the track change data of two bytes are read from the sequence memory 18.
  • First and second bytes of the track change data are respectively stored in the reading data buffers RD1 and RD2, and the reading pointer RBT is counted up by two so that the next reading address will be designated in steps 211 and 212.
  • the present reading track stored in the register TRKRD (hereinafter, simply referred to as the present reading track TRKRD) is compared with the writing track TRKWT (in steps 213 and 214).
  • the present process returns to the step 205 (shown in Figs. 14 and 23). If the present reading track TRKRD is not identical to the writing track TRKWT, the track change data of two bytes stored in the buffers RD1 and RD2 are written in the sequence memory 18 based on the address designated by the writing pointer WPT (in a step 215), and the writing pointer WPT is counted up by two (in a step 216) so that the next writing address will be designated. Next, the writing track number TRKWT is changed to a number TRKRD in a step 217. Thereafter, the present process returns to the original step 205 (shown in Figs. 14 and 23).
  • Fig. 16 based on the value of the reading pointer RPT, key-on data of three bytes are read from the sequence memory 18. Each one byte of such read key-on data is stored in each of the reading data buffers RD1 to RD3, and then the reading pointer RPT is counted up by three in steps 221 and 222.
  • the key-on data read from the buffers RD1 to RD3 are written into the sequence memory 18 in a step 223.
  • the CPU 10 judges whether the track mode TBL(TRKRD, 5) of the present reading track is the stop mode or not in steps 224 and 225. If the track mode is the stop mode, the processes of the following steps 226 to 229 will be unnecessary. Hence, the present process returns to the original step 205 shown in Figs. 14 and 23.
  • the CPU 10 reads the output terminal data TBL(TRKRD, 3) and the output MIDI channel TBL(TRKRD, 4) to which the data read from the buffers RD1 to RD3 are to be outputted from the input/output information register.
  • Such read output terminal data and the output MIDI channel are respectively stored in the registers OUTTRM and OUTCH in a step 226.
  • new key-on data are produced by replacing the input MIDI channel X H by the output MIDI channel stored in the register OUCH within the key-on data read from the buffers RD1 to RD3, and such new key-on data are stored in the output data buffers OUT1 to OUT3, the output data of which are transmitted to the output terminal register OUTTRM in steps 227 and 228.
  • step 206 shown in Figs. 14 and 23 an identifier mark 8X H is stored in the flat FLG, the CPU 10 executes the key-off event process of the step 240 shown in Fig. 17.
  • Fig. 17 the procedures in steps 241 to 248 are similar to those in the steps 221 to 228 shown in Fig. 16, except that the key-off event data are processed instead of the key-on event data, hence, description thereof will be omitted.
  • the time interval data of three bytes are read out based on the value of the reading pointer RPT, and then each one byte of the read time interval data is stored in each of the reading data buffers RD1 to RD3 in step 261.
  • the value of the reading pointer RPT is counted up by three so that the next reading address will be designated.
  • the read time intervals stored in the buffers RD2 and RD3 are respectively set to the reproducing timer registers PLYTMH and PLYTML (shown in Fig. 5)in a step 263.
  • Such time intervals stored in the buffers RD2 and RD3 are represented by two byte data, one byte of which consists of seven bits.
  • Such two byte data are converted into data of fourteen bits, which are store in the remaining time register LNRESTW in a step 264. Thereafter, the present process returns to the original step 205 shown in Figs. 14 and 23.
  • the prsent process advances to the end mark process (shown in Fig. 18) via the step 206.
  • the end mark is represented by one byte data.
  • the value "1" is set to the reproducing interrupt mask register PIRQMSK so as to inhibit the reproducing interrupt (i.e., the reading of the sequence performance data) from being executed in a step 276. Thereafter, the present process returns to the original step 205 shown in Figs. 14 and 23.
  • the performance mode designates the recording, the reproducing is only inhibited from being executed so that the recording will be continuously executed until the STOP switch 46 (shown in Fig, 2) is turned on.
  • the CPU 10 judges whether the STOP switch 46 (shown in Fig. 2) is turned on or not in step 171. If the STOP switch 46 is not turned on, the present process directly returns to the main process. On the other hand, if the STOP switch 46 is turned on, the CPU 10 executes the all key-off process of a step 300 shown in Fig. 21.
  • the key-off process is executed on the key code corresponding to the reproduced musical tone which is generated when the STOP switch 46 is turned on in the reproducing or recording mode.
  • each of the sixty four tracks provides thirty two output key code buffers.
  • the value "0" is set to the control variable for designating the track in a step 301, and the CPU 10 checks the track mode TBL(i, 5) of the track having the track number i (hereinafter, simply referred to as the track i) in a step 302.
  • the value "0" is set to a control variable j for designating the buffer in a step 303, and the CPU 10 judges whether the key code is stored in the output key code buffer OKCBUF(i, j) or not in a step 304.
  • the CPU 10 If the key code is stored in the buffer OKCBUF(i, j), the CPU 10 reads out output terminal data TBL(i, 3) and output MIDI channel TBL(i, 4) of the track i which are respectively stored in the registers OUTTRM and OUTCH in a step 305. In a next step 306, the CPU 10 produces key-off data having an output MIDI channel stored in the register OUTCH and a key code OKCBUF(i, j), and such key-off data are stored in the output data buffers OUT1 to OUT3.
  • the CPU 10 clears the buffer OKCBUF(i, j) in a step 307, and the key-off data stored in the buffers OUT1 to OUT3 are transferred to the output terminal register OUTTRM in a step 308. Thereafter, the control variable j is increased by one in a step 309, and the CPU 10 judges whether the searching is completely executed on all of the output key code buffers of the corresponding track or not in a step 310. If such searching is not completed, the present process returns to the step 304, whereby the searching will be executed on the next output key code buffer of the corresponding track.
  • the searching is completed, the control variable i is increased by one in a step 311, and then the CPU 10 judges whether the searching is completely executed on all of the sixy four tracks or not in a step 312. If such searching is not completed, the present process returns to the step 302, whereby the key code searching will be repeatedly executed on the next track.
  • the CPU 10 executes a key-off write process of a step 320 (shown in Fig. 22). Thereafter, the present process advances to a step 173 in the STOP switch-on process (shown in Fig. 20).
  • the key-off write process is executed when the STOP switch 46 (shown in Fig. 2) is turned on in the recording mode. More specifically, in the key-off write process, the key-off data of such depressing key are generated and then written in the sequence memory 18. More concretely, the CPU 10 scans the 2048 input key code buffers in order to search the input key code buffers which store the key codes. With respect to such key codes, the key-off data are generated and then written in the sequence memory 18.
  • step 332 If such track mode is not the recording mode, there are no keys depressed for writing the key-on and key-off data, so that the processes in steps 324 to 331 are skipped and then the present process advances to a step 332 from the step 323. If such track mode is the recording mode, the value "0" is set to the control variable j in the step 324, and the CPU 10 judges whether the key code is stored in the input key code buffer IKCBUF(i, j) or not in the step 325. If the key code is not stored in such input key code buffer, the processes in the steps 326 to 329 are skipped and then the present process advances to the step 330 from the step 325.
  • the key-off data of such key code is produced and then stored in the reading data buffers RD1 to RD3 in the step 326.
  • the CPU 10 clears the buffer IKCBUF(i, j). Based on the value of the writing pointer WPT, such key-off data stored in the buffers RD1 to RD3 are written into the sequence memory 18. Then, the writing pointer WPT is counted up by three so that the next writing address will be designated in the step 329. Thereafter, the control variable j is increased by one in the step 330, and the CPU 10 judges whether the searching is completely executed on all buffers of the track i or not in the step 331.
  • the present proces returns to the step 325 wherein the CPU 10 judges whether the key code is stored in the next buffer IKCBUF(i, j) or not. Meanwhile, if the searching is completely executed on all of the thirty two buffers of the track i, the present process advances to the next step 332 wherein the control variable i is increased by one. Next, the CPU 10 judges whether the searching is completely executed on the depressing keys in all of the sixty four tracks and whether the key-off data are completely written with respect to such searched keys or not in the step 333.
  • the present process returns to the step 323, whereby the above-mentioned processes in the steps 324 to 332 are repeatedly executed. If the CPU 10 judges that the searching and the key-off data writing is completed, the present process returns to the all key-off process (shown in Fig. 21) and further returns to the STOP switch-on process (shown in Fig. 20).
  • the value "0" is set to the performance mode register JOB in a step 173.
  • the CPU checks whether the value of the reproducing interrupt mask register PIRQMSK equals to the value "1" or not. If such value equals to "1", the sequence performance data are reproduced and then completely transferred to a new performance data area before the STOP switch 46 is turned on (as shown in the step 276 of Fig. 19). If such value equals to "0", there remain the sequence performance data which have not been transferred to the new performance data area yet. In this case, the remained sequence performance data are added to the last of the new sequence performance data.
  • the writing track number TRKWT is compared with the reading track number TRKRD in a step 175. If these two track numbers are different to each other, the track change data (of two bytes) for the reading track are written in the sequence memory 18 based on the value of the writing pointer WPT in steps 176 to 177. After the pointer WPT is counted up by two so that the next writing address is designated in a step 178, the present process advances to a step 179. On the other hand, if the writing track number TRKWT coincides with the reading track number TRKRD, the present process directly advances to the step 179 from the step 175.
  • step 179 data stored in the old performance data area having an address designated by the reading pointer RPT are repeatedly transferred to the new performance data area having an address designated by the writing pointer WPT in steps 180 and 181. If the end mark is detected in the step 179, the present process advances to a step 182 wherein such end mark F2 H is written in the sequence memory 18 based on the value of the writing pointer WPT. After the last address WPT of the sequence performance data is written in the register SONGEND in a next step 183, the present process returns to the main process (shown in Fig. 8).
  • the time interval data read from the sequence memory 18 are preset in the decrement counter 76 (shown in Fig. 5) within the tempo generator 26 in the step 263 shown in Fig. 18.
  • the decrement counter 76 counts down the clock CL so that the count value thereof becomes equal to O H
  • the tempo generator 26 generates the reproducing interrupt signal PLAYIRQ.
  • the CPU 10 executes the reproducing timer interrupt process of the step 400 (shown in Fig. 23).
  • the event data are read by every time interval (or every event timing) stored in the sequence memory 18 in the multi-recording apparatus according to the present embodiment.
  • the CPU 10 discriminates the performance mode JOB in a step 401 shown in Fig. 23.
  • the stop mode the performance mode is not read out.
  • the interrupt process is released and then the present process returns to the original process.
  • the performance mode is identical to one of the modes other than the stop mode (i.e., JOB does not equal to 0)
  • a value of (LNREST - LNSAM) is added to the value of the writing timing register RECCNT.
  • the value of LNSAM represents the lapsed time after inputting such key event data.
  • the CPU 10 clears the register LNSAM in a step 403, and then the remained time LNREST is set to the time interval register LEN in step 404. Thereafter, time interva data of three bytes are written into the sequence memory 18 based on the value of the writing pointer WPT in a step 405.
  • time interval data consist of the identifier mark F4 H , data LEN H7bit representative of the upper seven bits of the register LEN and data LEN L7bit representative of the lower seven bits of the register LEN. Further, the pointer WPT is counted up by three so that the next writing address will be designated in a step 406.
  • a next step 407 the writing track number TRKWT is compared with the reading track number TRKRD. If these two track numbers are different to each other, the writing track number is changed to thereby coincide with the reading track number. More specifically, the reading track number TRKRD is stored in the register TRKWT in a step 408, and the sequence memory 18 is written by track change data of two bytes consisting of the identifier mark FF H and a new track number stored in the register TRKWT in a step 409. Thereafter, the pointer WPT is counted up by two so that the next writing address will be designated in a step 410. If the writing track number is identical to the reading track number in the step 407, the processes in the steps 408 to 410 are skipped.
  • the CPU 10 reads out the event data at the present timing, the time interval data until the next event or the end mark in the next steps.
  • the processes in these next steps in the reproducing timer interrupt process shown in Fig. 23 are identical to those in the song start process shown in Fig. 14, hence, description thereof will be omitted.
  • the following interrupt process of a step 500 shown in Fig. 24 is executed based on the recording interrupt signal RECIRQ generated at every time when the increment counter 72 (shown in Fig. 5) within the tempo generator 26 counts 256 pulses of the clock CL.
  • the CPU 10 checks the performance mode JOB in a step 501.
  • the recording timer interrupt is necessary only in the recording mode. Hence, if the performance mode is not the recording mode (i.e., JOB does not equal to 2), the recording timer interrupt is immediately released.
  • the register LNSAM stores the lapsed time which is lapsed after inputting the preceding key event data in a step 502. In other words, the register LNSAM stores the above lapsed time at every time when the increment counter 72 (shown in Fig. 5) overflows.
  • the term RECCNT is used for calculating a time until the increment counter 72 overflows at first after inputting the key event data. After such calculation, the term RECCNT is cleared in a step 503.
  • the CPU 10 judges whether the lapsed time stored in the register LNSAM exceeds over data value of 3FFF H or not.
  • the decrement counter 76 shown in Fig. 5 for measuring the time interval is constructed by a 14-bit counter in the multi-recording apparatus according to the present embodiment.
  • the time interval exceeds over the data value of 3FFF H (i.e., the maximum value of the 14-bit data)
  • such time interval is divided into a plurality of time interval data each having a value smaller than the data value of 3FFF H .
  • the interrupt is directly released.
  • the sequence memory 18 is written by data of three bytes representative of the time interval 3FFF H based on the value of the pointer WPT. Such data of three bytes consist of F4 H , 7F H and 7F H . Finally, the writing pointer WPT is counted up by three so that the next writing address will be designated in a step 508, and then the present process returns to the original process.
  • the CPU 10 reads out the input terminal number n the input terminal of which is inputted with data from the input interrupt number register INIRQNO, and such read input terminal number n is stored in the input terminal register INTRM in a step 601.
  • the CPU 10 reads out key event data of three bytes from the register INBUFn, and each one byte of such key event data is stored in each of the buffers IN1 to IN3 in a step 602.
  • the MIDI channel included in the identifier mark stored in the buffer IN1 is stored in the register INCH
  • the key code stored in the buffer IN2 is stored in the register KC
  • the touch information stored in the buffer IN3 is stored in the regiser TCH respectively in steps 603 and 604.
  • the CPU 10 scans the input/output state tables shown in Figs. 6A to 6C so as to search certain recording tracks within the recording tracks having the track numbers 0 to 63.
  • the recording tracks are searched from the track number 0.
  • the present process advances to a step 611 (shown in Fig. 25B) from the step 606.
  • the detected track number i is stored in the register TRKIN.
  • the CPU 10 reads out and stores the output terminal TBL(TRKIN, 3) and the output MIDI channel TBL(TRKIN, 4) of the above track i in the registers OUTTRM and OUTCH respectively in a step 612.
  • the output data stored in the buffers OUT1 to OUT3 are produced in a step 613.
  • the CPU 10 executes the input key code (buffer) process (shown in Fig. 26) in a step 620.
  • the CPU 10 confirms the performance mode JOB in the step 625.
  • the CPU 10 immediately releases the interrupt, and the present process returns to the original process.
  • the present process advances to a step 631 (shown in Fig. 25C) wherein the writing timing of the preceding key event data stored in the register RECCNT is written into the register OLDRCNT.
  • the register RECCNT is written by the present time represented by the writing counter timer RECTIMER (shown in Fig. 5) in a step 632.
  • the CPU 10 calculates out and stores a value of [LNSAM + (RECCNT - OLDRCNT)] in the time interval register LEN in a step 633.
  • the CPU 10 calculates out and stores a value of (LNREST - LEN) in the remained time register LNREST in a step 634.
  • the CPU 10 clears the register LNSAM in a step 635.
  • the CPU 10 writes the time interval data of three bytes into the sequence memory 18 based on the value of the writing pointer WPT in a step 636.
  • the pointer WPT is counted up by three so that the next data writing address will designated in a step 637.
  • the writing track number TRKIN of the input data is compared with the present writing track number TRKWT.
  • the writing track number TRKIN of the input data is different from the present writing track number TRKWT, the writing track number TRKWT is changed identical to the writing track number TRKIN in a step 639.
  • track change data of two bytes consisting of data values of FF H and TRKWT
  • the pointer WPT is counted up by two so that the next writing address will be designated.
  • the present process advances to a step 642 wherein the input data of three bytes stored in the buffers IN1 to IN3 are written into the sequence memory 18 based on the value of the writing pointer WPT. Thereafter, the pointer WPT is counted up by three so that the next writing address will be designated in a step 643. Then, the CPU 10 releases the interrupt, and the present process will return to the original process.
  • Fig. 27 shows an operation example of the multi-recording according to the present embodiment.
  • the input data consisting of key event data K A and K B are mixed with reproduced data (i.e., old sequence data (a)) consisting of key event data K1, K2, K3 and K4 so as to produce new sequence data (b), and such new sequence data are multi-­recorded.
  • reproduced data i.e., old sequence data (a)
  • key event data K1, K2, K3 and K4 so as to produce new sequence data (b)
  • Such operation shown in Fig. 27 will be described by indicating the variation of the data stored in several registers.
  • the present process advances to the song start process (shown in Fig. 14) via the record switch-on process (shown in Fig. 13).
  • the value "0" of the writing timer RECTIMER is stored in the writing timing register RECCNT in the step 203, and the CPU 10 clears the lapsed time register LNSAM in the step 204.
  • the present process advances to the key-on or key-off event process (shown in Fig. 16 or 17). In such event process, the key event data K1 are read from the old sequence data area in the step 221, and such key event data K1 are written in the new sequence data area in the step 223.
  • the present process returns to the song start process wherein the present process advances to the time interval data process (shown in Fig. 18), whereby the time interval data having a data value "8" are set to each of the reproducing timer PLAYTIMER and the remained time register LNREST in the steps 263 and 264.
  • the time interval data process shown in Fig. 18
  • the time interval data having a data value "8" are set to each of the reproducing timer PLAYTIMER and the remained time register LNREST in the steps 263 and 264.
  • the CPU 10 executes the input interrupt process (shown in Fig. 25), wherein the key event data K A are read out in the step 602, and the old data having the value "0" stored in the writing timing register RECCNT are once saved in the old writing timing register OLDRCNT and then renewed by the value "5" of the writing timer RECTIMER in the steps 631 and 632.
  • the CPU 10 clears the lapsed time register LNSAM in the step 635, the CPU 10 writes the time interval data LEN and the input key event data K A into the new sequence data area in the steps 636 and 642.
  • the CPU 10 executes the reproducing interrupt process (shown in Fig. 23).
  • the present process advances to the key event process (shown in Fig.
  • the present process returns to the step 205 (shown in Fig. 23) and then advances to the time interval data process (shown in Fig. 18), wherein the time interval data having the value "5" is set to each of the reproducing timer PLAYTIMER and the remained time register LNREST in the steps 263 and 264.
  • the present process returns to the step 205 (shown in Fig. 23) and then advances to the time interval data process (shown in Fig. 18), wherein the time interval data having the value "250" is set to each of the reproducing timer PLAYTIMER and the remained time register LNREST in the steps 263 and 264.
  • This process of the key event data K B is executed similar to the process of the key event data K A described before. More specifically, the key event data K B are read out in the step 602, and the old data having the value "0" stored in the writing timing register RECCNT are once saved in the old writing timing register OLDRCNT and then renewed by the value "1" of the writing timer RECTIMER in the steps 631 and 632.
  • the present process returns to the step 205 (shown in Fig. 23) and then advances to the time interval data process (shown in Fig. 18), wherein the time interval data having the value "10" is set to each of the reproducing timer PLAYTIMER and the remained time register LNREST in the steps 263 and 264.
  • the timing information is calculated out based on the old timing data when the reproduced musical tones are to be recorded. Hence, it is possible to avoid the extension of the performance time due to the multi-recording which is occurred in the case where the values of the recording timer at the recording are used as the timing data.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Acoustics & Sound (AREA)
  • Multimedia (AREA)
  • Electrophonic Musical Instruments (AREA)
EP88101717A 1987-02-06 1988-02-05 Dispositif pour enregistrement multiples dans un instrument de musique électronique Expired - Lifetime EP0278438B1 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP62024867A JPH0797270B2 (ja) 1987-02-06 1987-02-06 演奏記録再生装置
JP24865/87 1987-02-06
JP24867/87 1987-02-06
JP62024866A JP2570718B2 (ja) 1987-02-06 1987-02-06 演奏記録再生装置
JP62024865A JPH0797269B2 (ja) 1987-02-06 1987-02-06 演奏記録再生装置
JP24866/87 1987-02-06

Publications (3)

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EP0278438A2 true EP0278438A2 (fr) 1988-08-17
EP0278438A3 EP0278438A3 (en) 1990-05-16
EP0278438B1 EP0278438B1 (fr) 1995-11-02

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US (1) US4899632A (fr)
EP (1) EP0278438B1 (fr)
DE (1) DE3854624T2 (fr)
HK (1) HK188096A (fr)

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WO1994024661A1 (fr) * 1993-04-09 1994-10-27 Franklin Eventoff Systeme pour instrument de musique assiste de notes
FR2752323A1 (fr) * 1996-08-12 1998-02-13 Perille Emmanuel Procede et dispositif pour l'enregistrement en boucles cycliques de plusieurs sequences phoniques

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JPH02208697A (ja) * 1989-02-08 1990-08-20 Victor Co Of Japan Ltd Ｍｉｄｉ信号誤動作防止方式及びｍｉｄｉ信号記録再生装置
JPH02311898A (ja) * 1989-05-29 1990-12-27 Brother Ind Ltd 演奏記録再生装置
US5326930A (en) * 1989-10-11 1994-07-05 Yamaha Corporation Musical playing data processor
JP2780403B2 (ja) * 1989-12-21 1998-07-30 ブラザー工業株式会社 演奏記録装置
JP2927889B2 (ja) * 1990-05-31 1999-07-28 ヤマハ 株式会社 電子楽器
JP2596206B2 (ja) * 1990-10-08 1997-04-02 ヤマハ株式会社 演奏データ記録再生装置および演奏データ記録再生方法
JP2620724B2 (ja) * 1990-10-23 1997-06-18 株式会社河合楽器製作所 演奏情報の記録装置
JP2904088B2 (ja) * 1995-12-21 1999-06-14 ヤマハ株式会社 楽音生成方法および装置
JP3277844B2 (ja) * 1997-04-16 2002-04-22 ヤマハ株式会社 自動演奏装置
JP3846526B2 (ja) 1999-06-10 2006-11-15 ヤマハ株式会社 インターフェース装置及び設定装置
US7563975B2 (en) * 2005-09-14 2009-07-21 Mattel, Inc. Music production system

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WO1994024661A1 (fr) * 1993-04-09 1994-10-27 Franklin Eventoff Systeme pour instrument de musique assiste de notes
FR2752323A1 (fr) * 1996-08-12 1998-02-13 Perille Emmanuel Procede et dispositif pour l'enregistrement en boucles cycliques de plusieurs sequences phoniques
WO1998007140A1 (fr) * 1996-08-12 1998-02-19 Emmanuel Perille Procede et dispositif pour l'enregistrement en boucles cycliques de plusieurs sequences phoniques

Also Published As

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DE3854624D1 (de) 1995-12-07
US4899632A (en) 1990-02-13
DE3854624T2 (de) 1996-03-28
EP0278438B1 (fr) 1995-11-02
HK188096A (en) 1996-10-18
EP0278438A3 (en) 1990-05-16

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