EP0271166B1 - Digitale Schaltungsanordnung zur Verringerung des Quantisierungsrauschens - Google Patents

Digitale Schaltungsanordnung zur Verringerung des Quantisierungsrauschens Download PDF

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Publication number
EP0271166B1
EP0271166B1 EP87202447A EP87202447A EP0271166B1 EP 0271166 B1 EP0271166 B1 EP 0271166B1 EP 87202447 A EP87202447 A EP 87202447A EP 87202447 A EP87202447 A EP 87202447A EP 0271166 B1 EP0271166 B1 EP 0271166B1
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EP
European Patent Office
Prior art keywords
output
input
output signal
coupled
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP87202447A
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German (de)
English (en)
French (fr)
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EP0271166A3 (de
EP0271166A2 (de
Inventor
Werner Bradinal
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Patentverwaltung GmbH
Philips Gloeilampenfabrieken NV
Koninklijke Philips Electronics NV
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Publication date
Application filed by Philips Patentverwaltung GmbH, Philips Gloeilampenfabrieken NV, Koninklijke Philips Electronics NV filed Critical Philips Patentverwaltung GmbH
Priority to AT87202447T priority Critical patent/ATE103435T1/de
Publication of EP0271166A2 publication Critical patent/EP0271166A2/de
Publication of EP0271166A3 publication Critical patent/EP0271166A3/de
Application granted granted Critical
Publication of EP0271166B1 publication Critical patent/EP0271166B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3002—Conversion to or from differential modulation
    • H03M7/3004—Digital delta-sigma modulation
    • H03M7/3015—Structural details of digital delta-sigma modulators
    • H03M7/3031—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path
    • H03M7/3042—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path the modulator being of the error feedback type, i.e. having loop filter stages in the feedback path only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3002—Conversion to or from differential modulation
    • H03M7/3004—Digital delta-sigma modulation
    • H03M7/3015—Structural details of digital delta-sigma modulators
    • H03M7/302—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M7/3024—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M7/3026—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one

Definitions

  • the invention relates to a digital circuit arrangement with an interpolation filter for oversampling a digital input signal which is present as a result of amplitude-discrete samples with a certain sampling frequency, with a noise shaper which contains a superposition stage, the output of which is connected to a quantizer, the first input of which is connected to the interpolation filter and whose second input is coupled to a second-order filter arrangement provided in a feedback loop for filtering a quantization error signal from the quantizer, and to a digital-to-analog converter coupled to an output of the quantizer.
  • Such a digital circuit arrangement is known from DE-PS 30 21 012.
  • the sampled values of the digital input signal are fed to an interpolation filter, which is implemented by a register, at a specific sampling frequency.
  • the output of the register is connected to a noise shaper, which contains a quantizer, two superposition stages and a filter.
  • the output signal of the filter is subtracted from the output signal of the register in the first superposition stage.
  • the output signal of the first superposition stage is fed to the quantizer, which is a linear quantizer.
  • the quantization jumps and the distances between the individual quantization jumps are equal in amount.
  • the quantization error signal is between the output signals of the quantizer and the first superposition stage formed, which is fed to the filter arrangement.
  • the samples of the quantization error signal are written into the filter arrangement with a higher sampling frequency than the samples of the input signal into the register.
  • a digital-to-analog converter is connected downstream of the noise shaping device, the analog output signal of which is fed to a low-pass filter, which suppresses the periodic spectra of the useful signal and carries out averaging over time.
  • the last read sample value is available, which is further processed at a higher frequency in the downstream noise generator.
  • oversampling is realized with this interpolation filter.
  • a digital circuit arrangement which uses an interpolation filter that writes the samples of the input signal with a sampling frequency of 44.1 kHz and with a sampling frequency of 176 , 4 kHz reads.
  • This interpolation filter carries out oversampling by a factor of 4 and low-pass filtering to suppress the periodic spectra of the useful signal.
  • the interpolation filter is followed by a noise shaper, the output signal of which is fed to a digital-to-analog converter.
  • the noise generator includes a first order filter.
  • the analog signal resulting from the digital-to-analog conversion of the quantized digital signal contains a through quantization noise caused by quantization.
  • the digital signal fed to the interpolation filter and the noise shaping device is further quantized in these two circuits by reducing the word width, which results in additional quantization noise.
  • This additional quantization noise, which arises in the noise shaper, is lower than a quantization noise, which is formed in a conventional quantization circuit without oversampling by quantization.
  • the size of the quantization noise reduction is determined by the choice of the filter.
  • the power of the quantization noise is partly shifted from the useful signal frequency range to a higher frequency range.
  • the size of the reduction in the quantization noise in the useful frequency range depends on the order of the filter.
  • the filter should be an optimal filter of a certain order, for which the power density spectrum of the quantization noise is minimal.
  • the implementation effort increases with the order of the filter. A good compromise between the implementation effort and the size of the reduction in the quantization noise results in a second-order filter.
  • EP-A-241 077 which represents a state of the art according to Article 54
  • EPC for the designated contracting states BE, DE, FR, GB, IT and NL
  • a limiter is provided which limits the quantization error signal supplied to the filter input.
  • the invention has for its object to design a digital circuit arrangement of the type mentioned in such a way that no instability occurs.
  • the object is achieved in that a limiter is connected in the feedback loop.
  • a limiter is connected into the feedback loop in the digital circuit arrangement, as a result of which the circuit remains stable even at values of the amount of the input signal which are close to the lower or upper maximum quantization values.
  • the limitation does not start until the sum of the amount of the output signal of the superposition stage and half the amount of a quantization jump is greater than the maximum amount of the output signal of the quantizer.
  • the amount of a quantization jump is the distance between two possible output values of the quantizer. This limitation does not necessarily apply exactly when the sum is just greater than the maximum amount of the output signal of the quantizer.
  • the upper or lower limit threshold must be determined so that none at high input signals Instability occurs, ie the exact limit threshold values have to be determined by a practical examination.
  • the filter arrangement can be connected in the noise generator on the one hand so that first the difference between the output signals of the superposition stage and the quantizer is formed and then the quantization error signal is fed to the filter arrangement, and on the other hand the output signal of the superposition stage and the output signal first in the filter arrangement of the quantizer are filtered and then the difference is formed between the filtered output signals of the superposition stage and the quantizer.
  • the limiter can be connected between the output of the superposition stage and the quantizer. There is also the possibility that the limiter is connected directly after the overlay stage. However, these two options are not claimed. There is also the option of switching the limiter directly before the second input of the superposition stage.
  • a fourth possibility is that the limiter is connected in front of the filter arrangement and the quantization error signal is fed to the limiter.
  • the quantization error signal can also be formed by an allocator (PROM), which assigns a specific value of the quantization error signal to a value of the output signal of the superposition stage.
  • the digital circuit arrangement according to the invention is developed in such a way that the limiter is connected upstream of the filter arrangement, it is provided that the arrangement contains a subtractor for generating the quantization error signal, the first input of which is connected to the output of the superposition stage, the second input of which is connected to the output of the quantizer and the latter Output is coupled to an input of the limiter, the output of which is coupled to an input of the filter arrangement, the output of which is coupled to the second input of the superposition stage.
  • the filter arrangement contains a first register, the input of which is coupled to the limiter and the output of which is coupled to an amplifier and a second register, and that the filter arrangement contains a further subtractor, the first input of which is connected to the second register , the second input of which is coupled to the amplifier and the output of which is coupled to the output of the filter arrangement.
  • the quantizer In order to make the digital-to-analog converter very simple, it is provided that the quantizer generates a 1-bit signal which assumes a first state when the output signal of the superposition stage is positive and which assumes a second state when the output signal of the Overlay level is negative. After the digital-to-analog conversion, the analog signal is fed to an integrator for time averaging. The oversampling must be greater when a 1-bit quantizer output signal is generated than with a multi-bit quantizer output signal, so that the same proportion of the power density spectrum of the quantization noise results in the useful frequency range.
  • the output signal of the quantizer can take two values. Depending on its resolution, the output signal of the interpolation filter can have different values between these two possible quantization values. Practical studies have shown that the limitation must not start until the amount of the difference between the output value of the interpolation filter and the output value of the quantizer is less than half the amount of an output value of the quantizer.
  • an interpolation filter 1 is supplied with a digital input signal which is present as a result of amplitude-discrete samples with a sampling frequency F1 determined by a clock signal.
  • the additional sampling values that arise during the oversampling are formed by interpolation in the interpolation filter 1.
  • the word width of the input or output signal of the interpolation filter 1 is L bits.
  • the output signal of the interpolation filter 1 is fed to a noise shaper 2 ("noise shaper").
  • a superposition stage 3 contained in the noise generator 2 adds the output signal of the interpolation filter 1 the output signal of a second-order filter arrangement 4.
  • the word width of the digital output signal of the filter arrangement 4 is M bits, where M> L. This results in an output signal A of superposition stage 3 with a word length of M bits.
  • This output signal A of the superposition stage 3 is fed on the one hand to a first input 5 of a subtractor 6 and on the other hand to a linear quantizer 7.
  • the quantizer 7 generates an output signal B with a word length of K bits, where K ⁇ M.
  • a linear quantizer is defined in that its quantization jumps, that is the amount between two successive values of the digital output signal B, and the distances between the individual quantization jumps are the same.
  • 2a shows the transmission characteristic of a linear quantizer which generates an output signal B with a word length of 2 bits.
  • the output signal B of the quantizer 7 forms the output signal of the noise shaper 2 and is fed to a digital-to-analog converter 8. Furthermore, the output signal B of the quantizer 7 is fed to the second input 9 of the subtractor 6.
  • the subtractor 6 forms an output signal C in which the output signal B of the quantizer 7 is subtracted from the output signal A of the superposition stage 3.
  • the output signal B of the quantizer 7 is linked to the output signal A of the superposition stage 3 in the subtractor 6 so that the maximum or minimum value of the output signal B is greater than or equal to or less than or equal to the maximum or minimum value of the output signal of the interpolation filter 1 .
  • the digital output signal C (quantization error signal) of the subtractor 6 has a word length of M bits.
  • Fig. 2b is the transmission characteristic, which is the dependency of the output signal C of the subtractor 6 from the output signal A of the superposition stage 3 is shown.
  • the output signal C of the subtractor 6 is fed to a limiter 10, which is also contained in the noise shaper 2.
  • the transmission characteristic which shows the dependence of the output signal D on the input signal C of the limiter 10 is shown in FIG. 2c. 2d shows the transmission characteristic which shows the dependence of the output signal D of the limiter 10 on the output signal A of the superposition stage 3.
  • the output of the limiter 10 is connected to a register 12 contained in the filter arrangement 4.
  • the output of register 12 is connected to an amplifier 13 and to another register 14.
  • the output of the amplifier 13, which has a gain factor of 2 is connected to a first input 15 of a subtractor 16.
  • the output of the register 14 is coupled to the second input 18 of the subtractor 16.
  • the output signal of the subtractor 16, which also represents the output signal of the filter arrangement 4 is formed by subtracting the output signal of the register 14 from the output signal of the amplifier 13.
  • the two registers 12 and 14 and the digital-to-analog converter 8 each receive a clock signal with a frequency F2.
  • the digitization of analog signals has the effect that not the respective instantaneous value, but rather a discrete amplitude value of a signal is transmitted, which can differ from the analog value by a maximum of half a quantization level.
  • This error which cannot be suppressed in principle, manifests itself as background noise and is described as Called quantization noise.
  • the circuit arrangement shown in FIG. 1 reduces the further quantization noise which arises when the word width is reduced in the noise shaping device.
  • the power density spectrum of this quantization noise is evenly distributed over the entire frequency range of interest, since the successive errors between the input value and the quantized output value are uncorrelated, ie the quantization noise is white noise.
  • the further quantization noise in the frequency range of interest is further reduced by redistributing the power density spectrum, i.e. the power density spectrum in the low frequency range is reduced and increased in the higher frequency range.
  • the quantization error of the output signal B of the quantizer 7 is namely calculated in the subtractor 6. This quantization error is superimposed on the input signal of the noise shaping device 2 as a correction value via the limiter 10 and the filter arrangement 4. With a suitable choice of the filter, the power density spectrum decreases at low frequencies and increases at higher ones.
  • the filter arrangement 4 is a second-order transversal filter which is constructed in such a way that the power density spectrum of the quantization noise in the useful frequency range can be minimized.
  • the output signal of the interpolation filter 1 which has been oversampled 256 times, is superimposed with a word width of 16 bits on the output signal of the filter arrangement 4 with a word width of 21 bits in the superposition stage 3. (The least significant bit of the output signal of the filter arrangement 4 and the least significant bit of the output signal of the interpolation filter 1 have the same significance.)
  • the output signal A of the superimposition stage 3 with a word length of 21 bits is supplied on the one hand to the quantizer 7 and on the other hand to the subtractor 6.
  • the quantizer 7 outputs an output signal B with two possible values.
  • the output signal B assumes a first state when the output signal of the Superposition stage 3 is positive and a second state when the output signal of the superposition stage is negative.
  • the output signal B which is forwarded to the digital-to-analog converter 8, not shown here, has a word width of 1 bit, while the output signal E of the quantizer 7, which is fed to the subtractor 6, has a word length of 21 bits.
  • the transmission characteristic of the quantizer 7 is shown in Fig. 4a.
  • the maximum signal value occurring in the noise shaping device 2 is set at 16 and the minimum value at -16.
  • the output signals B and E assume the value +1 for a positive digital signal A and the value -1 for a negative digital signal A.
  • the output signal E of the quantizer 7 is subtracted from the output signal A of the superposition stage 3.
  • the difference signal C at the output of the subtractor 6 is fed to the limiter 10.
  • the transmission characteristic, which represents the dependency of the difference signal C on the output signal A of the superimposition stage 3, is shown in FIG. 4b.
  • the transfer characteristic of the limiter 10 is shown in Fig. 4c.
  • the upper and lower limiting threshold values are +12 and -12, respectively.
  • the transmission characteristic, which shows the output signal D of the limiter 10 as a function of the output signal A of the superposition stage 3, is shown in FIG. 4d.
  • the output of the limiter 10 is connected to the filter arrangement 4.
  • the output signal B of the quantizer 7 is fed to the digital-to-analog converter 8, which is not shown here, and which generates an analog signal from the 1-bit signal, which is fed to an integrator, not shown here, which generates an analog signal which time average of the output signal of the digital-to-analog converter corresponds.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Analogue/Digital Conversion (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Communication Control (AREA)
  • Noise Elimination (AREA)
EP87202447A 1986-12-10 1987-12-08 Digitale Schaltungsanordnung zur Verringerung des Quantisierungsrauschens Expired - Lifetime EP0271166B1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT87202447T ATE103435T1 (de) 1986-12-10 1987-12-08 Digitale schaltungsanordnung zur verringerung des quantisierungsrauschens.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19863642168 DE3642168A1 (de) 1986-12-10 1986-12-10 Digitale schaltungsanordnung zur verringerung des quantisierungsrauschens
DE3642168 1986-12-10

Publications (3)

Publication Number Publication Date
EP0271166A2 EP0271166A2 (de) 1988-06-15
EP0271166A3 EP0271166A3 (de) 1991-06-26
EP0271166B1 true EP0271166B1 (de) 1994-03-23

Family

ID=6315880

Family Applications (1)

Application Number Title Priority Date Filing Date
EP87202447A Expired - Lifetime EP0271166B1 (de) 1986-12-10 1987-12-08 Digitale Schaltungsanordnung zur Verringerung des Quantisierungsrauschens

Country Status (7)

Country Link
US (1) US4859883A (ja)
EP (1) EP0271166B1 (ja)
JP (1) JP2613900B2 (ja)
KR (1) KR960006644B1 (ja)
AT (1) ATE103435T1 (ja)
BR (1) BR8706707A (ja)
DE (2) DE3642168A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5999347A (en) * 1993-06-29 1999-12-07 Sony Corporation Method and apparatus for higher resolution audio signal transmitting

Families Citing this family (13)

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Publication number Priority date Publication date Assignee Title
DE3744132A1 (de) * 1987-12-24 1989-07-06 Asea Brown Boveri Verfahren und schaltung zur unterdrueckung des quantisierungsrauschens
GB8829063D0 (en) * 1988-12-13 1989-01-25 British Telecomm Predictive coding and decoding
NL8901142A (nl) * 1989-05-08 1990-12-03 Philips Nv Inrichting voor het uitlezen van een op een registratiedrager aangebracht informatiepatroon, alsmede een signaalverwerkingsschakeling voor toepassing in een dergelijke inrichting.
US5057785A (en) * 1990-01-23 1991-10-15 International Business Machines Corporation Method and circuitry to suppress additive disturbances in data channels
GB9103777D0 (en) * 1991-02-22 1991-04-10 B & W Loudspeakers Analogue and digital convertors
US5602874A (en) * 1994-12-29 1997-02-11 Motorola, Inc. Method and apparatus for reducing quantization noise
DE19509117C2 (de) * 1995-03-17 1997-02-27 Bosch Gmbh Robert Verfahren zur Überwachung der Übertragungsqualität digitalisierter Signale
US5708389A (en) * 1996-03-15 1998-01-13 Lucent Technologies Inc. Integrated circuit employing quantized feedback
DE19912447C2 (de) * 1999-03-19 2002-02-28 Micronas Gmbh Anordnung zum Erzeugen eines in seiner Bitbreite begrenzten digitalen Signals und Digital/Analog-Umsetzer mit vergrößertem Wertebereich
WO2003096542A1 (fr) * 2002-05-09 2003-11-20 Neuro Solution Corp. Convertisseur numerique-analogique
EP1712004A2 (en) * 2004-01-28 2006-10-18 Koninklijke Philips Electronics N.V. A da-converter system and a method for converting a multi-bit digital signal to an analog signal
US6956513B1 (en) * 2004-10-22 2005-10-18 Broadcom Corporation Error feedback structure for delta-sigma modulators with improved stability
CN109690955A (zh) * 2017-06-15 2019-04-26 深圳市汇顶科技股份有限公司 噪声整形电路与三角积分数模转换器

Citations (1)

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EP0241077A1 (en) * 1986-04-04 1987-10-14 Koninklijke Philips Electronics N.V. Encoding device

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US4109110A (en) * 1975-02-20 1978-08-22 International Standard Electric Corporation Digital-to-analog converter
NL173339C (nl) * 1978-11-30 1984-01-02 Philips Nv Digitaal-analoog omzetter.
DE3021012C2 (de) * 1980-06-03 1985-08-22 ANT Nachrichtentechnik GmbH, 7150 Backnang Verallgemeinertes interpolativers Verfahren zur Digital-Analog-Umsetzung von PCM Signalen
GB8427325D0 (en) * 1984-10-29 1984-12-05 Plessey Co Plc Digital to analogue conversion

Patent Citations (1)

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Publication number Priority date Publication date Assignee Title
EP0241077A1 (en) * 1986-04-04 1987-10-14 Koninklijke Philips Electronics N.V. Encoding device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5999347A (en) * 1993-06-29 1999-12-07 Sony Corporation Method and apparatus for higher resolution audio signal transmitting
US6166873A (en) * 1993-06-29 2000-12-26 Sony Corporation Audio signal transmitting apparatus and the method thereof

Also Published As

Publication number Publication date
EP0271166A3 (de) 1991-06-26
DE3789426D1 (de) 1994-04-28
KR880008521A (ko) 1988-08-31
EP0271166A2 (de) 1988-06-15
ATE103435T1 (de) 1994-04-15
JP2613900B2 (ja) 1997-05-28
US4859883A (en) 1989-08-22
BR8706707A (pt) 1988-07-19
KR960006644B1 (en) 1996-05-22
JPS63161713A (ja) 1988-07-05
DE3642168A1 (de) 1988-06-16

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