EP0262478B1 - Procédé de synchronisation de trames d'un central d'un réseau de télécommunication à multiplexage temporel MIC - Google Patents

Procédé de synchronisation de trames d'un central d'un réseau de télécommunication à multiplexage temporel MIC Download PDF

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Publication number
EP0262478B1
EP0262478B1 EP87113202A EP87113202A EP0262478B1 EP 0262478 B1 EP0262478 B1 EP 0262478B1 EP 87113202 A EP87113202 A EP 87113202A EP 87113202 A EP87113202 A EP 87113202A EP 0262478 B1 EP0262478 B1 EP 0262478B1
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EP
European Patent Office
Prior art keywords
frame
bit
bits
bit position
frame start
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP87113202A
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German (de)
English (en)
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EP0262478A1 (fr
Inventor
Bernd Dipl.-Ing. Schuster
Horst Dipl.-Phys. Martin
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Siemens AG
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Siemens AG
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Application filed by Siemens AG filed Critical Siemens AG
Priority to AT87113202T priority Critical patent/ATE66556T1/de
Publication of EP0262478A1 publication Critical patent/EP0262478A1/fr
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Publication of EP0262478B1 publication Critical patent/EP0262478B1/fr
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H04J3/0605—Special codes used as synchronising signal

Definitions

  • the invention relates to a method for frame synchronization of the switching center of a PCM time-division multiplex telecommunication system, according to which the beginning of the frame of the time frame capturing the information channels from the serial data stream arriving at the switching center is determined by monitoring for the periodic occurrence of a frame start word, which is formed by overframing from pulse frame starts transmitted start bits is formed.
  • a known method according to patent application GB 2 048 617 A for frame synchronization of a digital communication system consists in comparing the incoming bits of a frame length one after the other with a synchronization bit of a synchronization pattern which has a specific numerical order within the synchronization pattern. At those bit positions where the comparison results in an overlap between data bits and synchronization bits, the respective data bit of the next frame is compared with a synchronization bit of the next higher order, while at those bit positions where there is no match, the comparison again with the synchronization bit of the lowest order is started. The procedure mentioned is continued until a bit position is compared with a data bit with the highest-ranking synchronization bit of the synchronization pattern and there is agreement, whereupon the actual frame synchronization takes place at this bit position.
  • the frame synchronization i.e. the time assignment of the operation of the receiving devices of the switching center to the beginning of the pulse frame is as quick as possible. It must be prevented that a frame start word simulated by voice data leads to such a synchronization, which in this case is incorrect.
  • the object of the invention is to provide a synchronization method which meets these requirements and which can also be implemented with the aid of a circuit arrangement which is of compact design and in particular can be implemented using integrated circuit technology.
  • this object is achieved with a method of the type mentioned at the outset, which is characterized in that the monitoring includes the bits of as many frames forming a frame group as there are between two successive bits of a valid frame start word within the serial data stream that for each bit position of such a frame group under Inclusion of the bits of so many equivalent bit positions of several successive frame groups that, based on the given binary value combination of the frame start word, it can be decided whether these bits are suitable as part of a frame start word or not, depending on the bit combination present, it is either determined that this bit position is not the beginning of the frame and a corresponding marking is carried out or the binary value to be expected on this bit position in the subsequent frame group is determined and compared with the actually occurring binary value that this procedure is repeated with respect to the bit positions not yet provided with such a marking until the latter Marking only one bit position is not affected, and that this procedure is repeated for this bit position, which has not been marked as the last, preferably several times before the receiving device of the switching center on this bit position le is
  • a correct frame start word is found by a recursive procedure which, as will be explained below, can be implemented with the aid of a FIFO memory.
  • Yet another embodiment of the invention relates to the special case that initially several bit positions over a longer period of time than for a frame start are designated in question. One of these bit positions at the beginning of the frame is then declared in a kind of continuous synchronization and another check is made as to whether this beginning of the frame is valid. If this is not the case, this bit position is marked and a new synchronization attempt is made with a further one of these not yet marked bit positions. The process is repeated until the correct beginning of the frame has finally been found.
  • Another embodiment of the invention aims at a circuit arrangement for carrying out the method according to the invention, which meets the aforementioned requirements for a compact implementation in the form of an integrated circuit.
  • a scan pulse frame of a PCM time-division multiplex telecommunications system is shown in line a) in FIG. It takes 125 ⁇ s and includes time spans for 24 voice channels, each containing eight bits to represent a voice sample and possibly also for signaling.
  • Line b) of FIG. 1 shows an overframe which comprises 24 such frames shown in line a).
  • the strongly drawn vertical lines illustrate bit time periods which contain information other than speech information corresponding to the time period for the frame start bit fb in line a).
  • a frame start word is formed with the frame start bits repeating all four pulse frames within the 24 frame, which in the specific case has the binary word combination 001011.
  • the object of the method according to the invention is to recognize the frame start word from a data stream arriving at a switching center of a PCM time-division multiplex telecommunication system, which occurs in pulse frames in the manner described, in order to be able to synchronize the switching center with the frame start. From the state of asynchronism, such a synchronization process begins at any point within such a data stream. Because of the repetition of frame start bits every four frames, the content of four such frames must therefore be included in the monitoring.
  • FIG. 2 first explains the processes that take place in connection with a single bit position when the data stream is checked.
  • three memories ZO to Z2 are therefore provided, in which bits of a specific bit position are assumed at intervals of four pulse frames and are entered one after the other. If bits of these binary values are read out of the memories ZO to Z2 when the subsequent route clock ST occurs, they arrive at a network N, in which, on the one hand, a corresponding link is established on the basis of the determined binary value combination of a correct frame start word to determine whether the received bit combination is a is a valid bit combination, in which case a corresponding signal is emitted at the output BG and, on the other hand, it is determined which binary value the next bit of a valid frame start word should have.
  • a signal of this binary value is sent as a reference signal via the output R of the network to one input of an equivalent circuit AE, to the other input of which the bits occurring in the data stream arrive. If the bit position under consideration assumes the expected binary value four pulse frames later, the equivalence circuit releases the coincidence elements KO to K2 together with the validity signal supplied by the output BG of the network N. The result of this is that, on the one hand, the current bit can now reach the memory Z2 via the coincidence element K2, on the other hand, the previous content of the memory Z2 via the coincidence element K1 into the memory Z1 and the previous content of the memory Z1 via the coincidence element KO into the The contents of the memory Z0 are lost. The processes described are now repeated with the current contents of the memories Z0 to Z2.
  • a blocking signal for the coincidence elements KO to K2 is output via the output BG of the network, which causes the binary value combination 000 to be written into the memories ZO to Z2, ensuring that this combination is independent of subsequent bits this bit position is retained, which means that this bit position is definitely excluded as the start of the frame.
  • FIG. 3 A circuit arrangement as shown in FIG. 3 can be used for the actual implementation.
  • This arrangement has according to the three memories ZO to Z2 acc. 2 shows three shift register memories Sch 0 to Sch 2, each of which has as many levels as there are bit positions in the considered time window of four pulse frames.
  • these shift registers are divided into two parts, each having 2 ⁇ 193 stages, which means that this circuit arrangement is not only suitable for the conditions explained, in which the bits of the frame start word are repeated every four pulse frames, but also when Check for frame start words whose bits repeat every two pulse frames.
  • the outputs of the shift registers according to FIG. 3 are routed to an assigned input of a network N and to an input of the respectively associated coincidence element KO to K2.
  • the outputs of the two parts of the shift register are combined via multiplexers MUX, which pass either output signals from one or the other half on the basis of a "mode" control signal.
  • the arrangement and function of the equivalent circuit AE is the same as in the arrangement according to. Fig. 2.
  • the entire circuit arrangement is under the control of a frame counter RZ.
  • circuit arrangement acc. 3 there are practically 772 circuit arrangements as shown in FIG. 2, the individual bit positions being checked within a time window of four pulse frames or 772 bits each offset by one bit by the binary values of these bit positions being successively applied under the influence of the path clock the shift register is pushed to the end and then receives the appropriate treatment.
  • bit stream checked in this way actually contains a frame start word, in the course of the recursive process described, only one bit position will ultimately remain which is not marked as a bit position which is invalid for a frame start word. This one bit position is then, as already explained, checked several times for its validity and then declared as the start of the frame, whereupon the circuit arrangement emits a synchronization signal FL for synchronizing the receiving device of the switching center to the start of the frame.
  • the three shift registers are reloaded with the bits from 3 ⁇ 4 frames as at the beginning of the procedure, whereupon the checking phase for finding a frame identification word starts again.
  • bit positions at the beginning of the frame can be declared and a synchronization can be carried out. The correctness of this bit position will then checked using another facility. If it is not confirmed, the relevant bit position is marked and a synchronization attempt is made with another of the considered bit positions until finally the one that actually represents the beginning of the frame is found among these remaining bit positions.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Enzymes And Modification Thereof (AREA)
  • Medicines Containing Antibodies Or Antigens For Use As Internal Diagnostic Agents (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Selective Calling Equipment (AREA)

Claims (4)

  1. Procédé pour réaliser la synchronisation de trame du central d'un système de télécommunication MIC à multiplexage temporel, selon lequel on détermine le début de la trame temporelle englobant les canaux d'informations à partir du flux en série de données, qui arrive dans le central, au moyen du contrôle de l'apparition périodique d'un mot de début de trame, qui est formé lors de la formation d'une trame de rang supérieur, respectivement à partir de bits de départ émis au début des trames, caractérisé par le fait que, lors du contrôle, on insère les bits d'autant de trames formant un groupe de trames, qu'il en existe entre deux bits successifs d'un mot de début de trame valable dans le flux de données en série, que pour chaque position binaire d'un tel groupe de trames, et moyennant l'insertion des bits d'un nombre de positions binaires de même rang de plusieurs groupes successifs de trames, sur la base de la combinaison indiquée des valeurs binaires du mot de début de trame, on peut déterminer si ces bits font partie ou non d'un mot de début de trame, et si en fonction de la combinaison binaire présente, on peut déterminer que cette position binaire n'est pas le début de la trame et qu'on réalise un marquage correspondant, ou bien on détermine la valeur binaire à laquelle on doit s'attendre dans cette position binaire dans le groupe suivant de trames et on la compare à la valeur binaire effectivement apparue, qu'on répète cette procédure rapportée aux positions binaires non encore pourvues d'un tel marquage, jusqu'à ce que seule encore une position binaire ne soit pas concernée par ce marquage, et qu'on répète de préférence encore une fois cette procédure pour cette position binaire non marquée comme étant la dernière, avant que le dispositif de réception du central soit synchronisé sur cette position binaire en tant que début de trame.
  2. Procédé suivant la revendication 1, caractérisé par le fait que dans la mesure où, lors de ladite procédure, toutes les positions binaires ont été affectées d'une marque, cette procédure est à nouveau déclenchée, auquel cas on contrôle des parties du flux de données qui n'étaient pas encore incluses auparavant.
  3. Procédé suivant la revendication 1, caractérisé par le fait que dans la mesure où plusieurs positions binaires subsistent sans marquage pendant des intervalles de temps assez longs, on réalise tout d'abord la synchronisation sur l'une de ces positions binaires en tant que début de trame, puis on contrôle par ailleurs la validité de cette position binaire, que, dans la mesure où cette position binaire s'avère non valable, on lui affecte une marque et on réalise à nouveau la synchronisation sur une autre position binaire non pourvue d'une marque, et qu'on répète ce processus jusqu'à ce que l'on ait trouvé une position binaire valable en tant que début de trame.
  4. Montage pour la mise en oeuvre du procédé suivant l'une des revendications précédentes, caractérisé par un nombre, identique au nombre des groupes de trames pris en compte, de registres à décalage (SCH0 à SCh2), dans lesquels le transfert s'effectue à la cadence de sections (ST) du flux de données (PCM-D) arrivant, et comportant un nombre d'étages identique au nombre des bits d'un groupe de trames, registres à décalage dans lesquels successivement les bits du flux de données d'arrivée (PCM-D) sont envoyés en tant qu'information d'entrée au premier registre à décalage (Sch2) et les bits lus à partir du dernier étage du registre à décalage (Sch2, Sch1) respectivement précédent dans la série, sont envoyés aux autres registres à décalage en tant qu'information d'entrée, et par un réseau combinatoire (N), auquel les bits lus dans les derniers étages de registres à décalage (Sch0 à Sch2) sont envoyés en tant que grandeur d'entrée, et qui, à partir de là, en fonction de la combinaison donnée des valeurs binaires d'un mot de début de trame, délivre un bit de référence (R) possédant la valeur binaire, à laquelle on doit s'attendre, du bit immédiatement suivant du mot de début de trame, dans la mesure où la combinaison de valeurs binaires des grandeurs d'entrée est utilisée comme partie constitutive du mot de début de trame et, lorsque ce n'est pas le cas, délivre un signal d'effacement (BG), et par un circuit coïncidant (AE), qui compare ledit bit de référence (R) au bit respectivement actuel du flux de données (PCM-D), et par un circuit à coïncidence respectif (K0 à K2), qui est associé aux registres à décalage (SCH0 à SCH2) et auquel sont envoyés le signal d'effacement (BG), le signal de sortie du circuit à équivalence (AE) et les bits du flux de données (PCM-D) et dont le signal de sortie constitue le signal d'entrée du registre à décalage associé, ainsi que par un compteur (RZ) servant à réaliser la commande en temps opportun du réseau (M).
EP87113202A 1986-09-29 1987-09-09 Procédé de synchronisation de trames d'un central d'un réseau de télécommunication à multiplexage temporel MIC Expired - Lifetime EP0262478B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT87113202T ATE66556T1 (de) 1986-09-29 1987-09-09 Verfahren zur rahmensynchronisierung der vermittlungsstelle eines pcm-zeitmultiplexfernmeldesystems.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3633062 1986-09-29
DE3633062 1986-09-29

Publications (2)

Publication Number Publication Date
EP0262478A1 EP0262478A1 (fr) 1988-04-06
EP0262478B1 true EP0262478B1 (fr) 1991-08-21

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EP87113202A Expired - Lifetime EP0262478B1 (fr) 1986-09-29 1987-09-09 Procédé de synchronisation de trames d'un central d'un réseau de télécommunication à multiplexage temporel MIC

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US (1) US4864565A (fr)
EP (1) EP0262478B1 (fr)
AT (1) ATE66556T1 (fr)
BR (1) BR8704991A (fr)
DE (1) DE3772313D1 (fr)
DK (1) DK167791B1 (fr)
FI (1) FI88838C (fr)
PT (1) PT85806B (fr)

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DE4341798C1 (de) * 1993-12-08 1995-08-10 Telefunken Microelectron Verfahren zur Datenübertragung
US5557614A (en) * 1993-12-22 1996-09-17 Vlsi Technology, Inc. Method and apparatus for framing data in a digital transmission line
SE503920C2 (sv) * 1994-10-03 1996-09-30 Ericsson Telefon Ab L M Sätt att synkronisera signaler och anordning härför
GB2337861B (en) * 1995-06-02 2000-02-23 Dsc Communications Integrated directional antenna
GB2301752B (en) * 1995-06-02 2000-03-29 Dsc Communications Control message transmission in telecommunications systems
US5696766A (en) * 1995-06-02 1997-12-09 Dsc Communications Corporation Apparatus and method of synchronizing a transmitter in a subscriber terminal of a wireless telecommunications system
GB2301751B (en) * 1995-06-02 2000-02-09 Dsc Communications Control message transmission in telecommunications systems
US5742595A (en) * 1995-06-02 1998-04-21 Dsc Communications Corporation Processing CDMA signals
GB2301717B (en) * 1995-06-02 1999-08-11 Dsc Communications Network controller for monitoring the status of a network
US5915216A (en) * 1995-06-02 1999-06-22 Dsc Communications Corporation Apparatus and method of transmitting and receiving information in a wireless telecommunications system
GB2301735B (en) * 1995-06-02 1999-07-28 Dsc Communications Message handling in a telecommunications network
GB2301741A (en) * 1995-06-02 1996-12-11 Dsc Communications Establishing a Downlink Communication Path in a Wireless Communications System
US5745496A (en) * 1995-06-02 1998-04-28 Dsc Communications Corporation Apparatus and method of establishing a downlink communication path in a wireless telecommunications system
US5809093A (en) * 1995-06-02 1998-09-15 Dsc Communications Corporation Apparatus and method of frame aligning information in a wireless telecommunications system
FI107673B (fi) 1999-09-28 2001-09-14 Nokia Multimedia Network Termi Menetelmä ja järjestelmä digitaaliseen signaaliin synkronoitumiseksi ja synkronoinnin säilyttämiseksi
US6438039B1 (en) * 2001-07-03 2002-08-20 Macronix International Co., Ltd. Erasing device and method for flash memory

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Also Published As

Publication number Publication date
DE3772313D1 (de) 1991-09-26
FI874251A (fi) 1988-03-30
PT85806B (pt) 1993-12-31
PT85806A (pt) 1988-10-14
EP0262478A1 (fr) 1988-04-06
DK508487A (da) 1988-03-30
FI88838C (fi) 1993-07-12
FI874251A0 (fi) 1987-09-28
FI88838B (fi) 1993-03-31
BR8704991A (pt) 1988-05-17
DK167791B1 (da) 1993-12-13
US4864565A (en) 1989-09-05
DK508487D0 (da) 1987-09-28
ATE66556T1 (de) 1991-09-15

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