EP0257061A1 - Dispositif a processeur multiple - Google Patents

Dispositif a processeur multiple

Info

Publication number
EP0257061A1
EP0257061A1 EP19870901191 EP87901191A EP0257061A1 EP 0257061 A1 EP0257061 A1 EP 0257061A1 EP 19870901191 EP19870901191 EP 19870901191 EP 87901191 A EP87901191 A EP 87901191A EP 0257061 A1 EP0257061 A1 EP 0257061A1
Authority
EP
European Patent Office
Prior art keywords
data
bus
transfer
processor
request signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19870901191
Other languages
German (de)
English (en)
Inventor
Thomas Neal Berarducci
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Eastman Kodak Co
Original Assignee
Eastman Kodak Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eastman Kodak Co filed Critical Eastman Kodak Co
Publication of EP0257061A1 publication Critical patent/EP0257061A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining

Definitions

  • a multi-processor apparatus includes a plurality of processors for processing digital data and is especially suitable for use in processing digital image signals. Two or more processors can operate on data at the same time, thereby increasing data throughput.
  • a multi-processor apparatus is often suitable for use.
  • One particular application where multi-processor apparatus is used is in digital image processing.
  • Digital image processing is used to perform image enhancement processing on a digital image to produce an enhanced digital image.
  • This enhanced digital image is read out from memory and provided to a high speed "scan" printer.
  • Large amounts of data must be processed.
  • multi-processor apparatus having an array of processors is used. These processors are often microcomputers. Because of the amount of data involved and the need for increased throughput, the use of multi-processor apparatus is becoming more frequent.
  • FIG. 1 A typical prior art multi-processor apparatus architecture is shown in Fig. 1. It operates by sharing a single bus between processors and a single large main memory (data memory). Each processor makes a request to gain control of the bus when it needs access to a location in the main memory. During each data transaction all other processors which are not busy processing data must wait for the bus to again become free. An arbitor circuit (not shown) establishes the order in which the processors can gain access to the bus. Throughput (data transfer rate) increases as the number of processors is increased. This increase in throughput continues only up to a point. Thereafter, an increase in the number of processors actually decreases the throughput. Disclosure of the Invention
  • the object of this invention is to provide a parallel processor apparatus with increased throughput.
  • apparatus for processing digital image signals characterized by: an array of separately addressable memory units, each including input and output data storage means; an array of processors each including input and output data storage means; first data transfer means including a first data bus, and means for transferring data from output data storage means of a selected processor via the first data bus to the input data storage means of a selected memory unit; and second data transfer means including a second dnta bus, and means independent of said first transferring means for transferring data from output data storage means of a selected memory unit via the second data bus to an input data storage means of a selected processing unit.
  • Each data bus is used only for the short duration required to transfer data between data storage means.
  • each memory bus is controlled by separate arbitor circuits.
  • Each arbitor circuit is independent of the other circuit.
  • Fig. 1 is a block diagram of a conventional prior art digital image processing apparatus
  • Fig. 2 shows in block form the elements of digital image processing apparatus in accordance with the invention
  • Fig. 3 is a block diagram of portions of the apparatus of Fig. 2 which illustrate the transfer of data from an output buffer of a selected processor to an input buffer of a selected memory unit; and Fig. 4 is a schematic diagram of the arbitor circuit for BUS I. Modes of Carrying Out the Invention
  • the apparatus 10 includes an array 12 having a plurality (n) of processors 14 and an array 16 having a plurality (m) of memory units 18. At this point it will be noted that the number n does not necessarily equal the number m. All processors 14 must be able to access any one of the memory units 18. Associated with each processor 14 is an input latch 20 and an output buffer 22. Each memory unit 18 includes an input latch 26 and an output buffer 28. Buffers and latches are data storage devices. A buffer is a device that transmits the signal at its input to its output.
  • a latch is a device that stores the signal at its input in response to a clock signal.
  • These buffers and latches include tri-state logic devices. Tri-state logic devices or gates are commonly used in the interconnection to a common bus. When a control line is enabled, the tri-state devices are coupled to the bus. When the control line is disabled, the tri-state devices act as a high-output impedance and are decoupled from the bus.
  • BUS I is a unidirectional bus and is associated with the output buffers 22 of the processors and the input latches 26 of the memory units.
  • An arbitor circuit 30 controls the transfer of data on BUS I from processors to memory units and an arbitor circuit 32 controls the transfer of data from memory units 18 to the processors 14.
  • a high-level grant request signal is provided to arbitor circuit 30.
  • the arbitor circuit 30, as will be described later, is arranged so that each processor has almost equal priority to gain access to BUS I.
  • Arbitor circuit 30 arbitrates among all processors producing grant request signals and in accordance with a predetermined order sequentially transfers data between the output buffer 22 of each selected processor and the input latch 26 of the corresponding memory unit.
  • the arbitor 32 functions independently of the circuit 30 and controls the flow of data from the output buffer 28 of a selected memory unit via BUS II to the input latch 20 of a selected processor 14.
  • BUS II is a unidirectional bus and is associated with the input latches 20 of the processors 14 and the output buffers 28 of the memory units 18.
  • the arrangement of two unidirectional buses allows full duplex operation, that is, at any given time a processor can be transferring data to a memory unit while at the same time, a memory unit can be transferring data to another processor.
  • Each bus is used only for the short time required to transfer data between data storage means.
  • Each bus is operated independently of the other bus. By means of this arrangement, throughput can be significantly increased.
  • a digital image corresponding to a light image must be stored in the memory planes 24 of the memory units 18.
  • the digital pixel value stored at each memory location in a memory plane 24 represents brightness or a gray scale level.
  • each digital image pixel can have 24 bits; 8 bits gray scale for red, 8 bits gray scale for green and 8 bits gray scale for blue.
  • One of the processors can be dedicated to receive digital image data and deliver them to memory plane locations.
  • Image sensors (not shown) operated by their own microcomputer produce analog signals corresponding to a color component of a light image. These image sensors can be, for example, CCD image area sensors.
  • a conventional digitizer digitizes these analog signals and applies them to the dedicated processor.
  • This processor gains access to BUS I, and applies image pixel data and an address onto BUS I.
  • This address includes not only the particular memory unit to be accessed but also the memory location in the memory plane of such unit where the digital image pixel data are to be stored.
  • the purpose of the array of digital image processors 14 is to produce an enhanced digital image.
  • a printer 50 responds to this enhanced digital image on a digital pixel by digital pixel basis to produce an output print which is more suitable for viewing than if image processing had not taken place.
  • Digital image processing is well known and often is used in eccordance with grain supression algorithms, edge enhancement algorithms and tone scale algorithms. Examples of such digital image processing algorithms are set forth in commonly assigned U.S. Patent Nos. 4,399,461, 4,442,454, and 4,446,484.
  • the printer 50 can be provided by a laser printer. Image processing algorithms, as well as other process control algorithms, necessary to control the processors are provided in memories (not shown) associated with each processor.
  • an enhanced digital pixel is delivered to a particular one of the memory units 18.
  • This memory unit causes enhanced digital pixels to be sequentially delivered to printer 50.
  • FIG. 3 there is shown an output buffer 22 of a selected processor 14 and an input latch 26 of a selected memory unit 18.
  • the processor 14 for this output buffer has already produced a high-level grant signal on a Grant Request lead and provided it as an input to arbitor circuit 30.
  • the selected processor has provided an address as an input to its output buffer 22.
  • the selected processor 14 also provides its own return address as an input to buffer 22 so that the selected memory unit 18 will know the processor return address. This return address is sometimes referred to as a "packet return address.”
  • a grant signal is produced by the circuit 30.
  • the grant signal is provided to the output buffer 22 of the requesting processor 14.
  • Data are then applied on BUS I from buffer 22 and delivered to all the input latches of the memory units 18.
  • the desired memory unit is decoded by decode logic 33 from the address. If the unit is not busy, the grant signal is gated to that memory unit. In this way, these data are only entered into the latch of the addressed or selected memory unit.
  • the busy signal is produced by logic associated with a memory unit and indicates that it is unable to accept data.
  • the arbitor circuit 30 will assume the grant request has been serviced and continue to service all the other grant request signals.
  • the unserviced processor will continue to produce a grant request signal. Thereafter circuit 30 will repeat the process discussed above and will service this processor if the addressed memory unit is not busy. The operation of circuit 30 will be described in detail later with reference to Fig. 4. Decode logic circuitry is not needed for the
  • BUS II arbitor The reason for this is that when a processor requests data, it will remain idle until data is delivered to it from a memory unit.
  • a low level signal to the output buffer of the selected processor is an enabling signal to tri-state logic in such a buffer causing data to be transferred to BUS I.
  • the small circle at the input of the buffer 22 indicates it responds to a low level signal.
  • the small triangle or wedge in the latch 26 indicates that it is enabled by a positive going edge signal.
  • the tri-state logic in the output buffer has applied the memory address, data and processor address onto BUS I. Thereafter, a rising edge is applied by circuit 30 through the decoding logic 33 to the selected input latch 26. All data on BUS I are latched into such selected input latch 26.
  • Fig. 2 we will for the sake of explanation assume that the addressed memory unit has been instructed to deliver data from an addressed memory location in memory plane 24 to output latch 26. After such data are stored in latch 26, logic associated with the memory plane produces a high-level grant request signal and the output buffer is loaded with data from the memory location and the processor address. When the grant request to arbitor circuit 32 is honored, these data and the processor address are applied from the output buffer onto BUS II. Since the desired processor is not busy but waiting for data, the data are then delivered to the input latch 20 of the processor indicated by the packet return address via similar decoding logic as described above. This processor having received data, then performs an appropriate operation in accordance with a stored algorithm in a stored program.
  • Fig. 4 a schematic diagram of arbitor circuit 30 is shown.
  • the first bank 78 receives the grant request signals and the second bank 79 produces the grant signals.
  • Each flip/flop has terminals marked PR (preset) and CL (clear) respectively.
  • PR preset
  • CL low level signal
  • a NOR gate will produce a high level output (logic "1") only if all inputs are low. If even only one input is high, it will produce a low level output (logic "0").
  • the circuit 30 has six separate grant lines, one for each processor 14.
  • Clock signal ⁇ from a stable clock circuit passes through the AND gate 84 and is delivered to the clock input terminal of each flip/flop in the bank 78.
  • Q 1 .
  • a high-level input is thereby provided to NOR gates 86 (b-f) and 82.
  • NOR gate 82 switches and provides a low-level output to AND gate 84 which inhibits further clock signals from passing into the clock inputs of the flip/flops 80(a-f).
  • flip/flop 80a changes state, it provides a low-level input to the D terminal of a flip/flop 90a in bank 79.
  • Flip/flop 80a immediately changes state and in response to this change, NOR gate 82 produces a positive high-level signal to AND gate 84 permitting clock signals to be provided to the clock input terminal of each flip/flop in bank 78. The state of flip/flop 80a will cause flip/flop 90a to change its state, back to its initial state, at the next clock edge.
  • This falling edge causes the transfer of data from the buffer 22 of the selected processor onto BUS I. It also provides a feedback signal to the CL terminal of flip/flop 80b which changes state, causing NOR gate 86b to produce a low-level output. The state of flip/flop 80b will cause flip/flop 90b to change its state, back to its initial state, at the next clock edge latching the data on BUS I into the selected memory unit, if the memory unit is not busy. It should be noted that NOR gate 82 still produces a low-level output. However, the change of state of flip/flop 80b causes NOR gate 86f to provide a high-level signal to flip/flop 90f.
  • flip/flop 90b On the next rising edge of the clock, flip/flop 90b changes state as discussed above and flip/flop 90f changes state.
  • the grant signal on the Grant 6 lead changes from a high to a low level.
  • processor 6 is now connected to BUS I.
  • a feedback signal from flip/flop 90f clears flip/flop 80f which through NOR gate 86f sets up flip/flop 90f to change state at the next clock edge.
  • NOR gate 82 now enables AND gate 84 and the next set of request signals are ready to be latched into bank 78 on the next rising edge of signal ⁇ .
  • Arbitor circuit 32 is identical in construction to circuit 30 and so this circuit need not be shown in detail. Both of these arbitor circuits provide close to equal priority to processors and memory units in gaining access to their data buses, when viewed over several cycles of access.
  • Multi-Processor apparatus can be used for efficiently forming a digital image from a photographic negative. Such a digital image can be used in an output laser printer which makes prints.
  • An advantage of this invention is the provision of an efficient arbitor circuit which controls access to a bus and provides substantially equal priority in gaining access to a bus to all requesting units.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)

Abstract

Dispositif à processeur multiple comprenant un réseau d'unités de mémoire (18) adressables séparément et un réseau de processeurs (14) adressables séparément. Un premier bus unidirectionnel (BUS I) assure le transfert des données d'un processeur sélectionné à une unité de mémoires sélectionnées. Un deuxième bus de données unidirectionnel (BUS II) assure le transfert de données d'une unité de mémoire sélectionnée à un processeur sélectionné. Des circuits d'arbitrage (30, 32) assure la régulation du flux de données vers lesdits bus de données.
EP19870901191 1986-02-10 1987-01-27 Dispositif a processeur multiple Withdrawn EP0257061A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US82756586A 1986-02-10 1986-02-10
US827565 1986-02-10

Publications (1)

Publication Number Publication Date
EP0257061A1 true EP0257061A1 (fr) 1988-03-02

Family

ID=25249547

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19870901191 Withdrawn EP0257061A1 (fr) 1986-02-10 1987-01-27 Dispositif a processeur multiple

Country Status (3)

Country Link
EP (1) EP0257061A1 (fr)
JP (1) JPS63502535A (fr)
WO (1) WO1987004826A1 (fr)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5029018A (en) * 1987-11-18 1991-07-02 Nissan Motor Company, Limited Structure of image processing system
US5153936A (en) * 1988-06-27 1992-10-06 International Business Machines Corporation Dual density digital image system
US5058185A (en) * 1988-06-27 1991-10-15 International Business Machines Corporation Object management and delivery system having multiple object-resolution capability
US5131085A (en) * 1989-12-04 1992-07-14 International Business Machines Corporation High performance shared main storage interface
US6928500B1 (en) 1990-06-29 2005-08-09 Hewlett-Packard Development Company, L.P. High speed bus system that incorporates uni-directional point-to-point buses
AU636739B2 (en) * 1990-06-29 1993-05-06 Digital Equipment Corporation High speed bus system
JPH04137166A (ja) * 1990-09-28 1992-05-12 Matsushita Electric Ind Co Ltd メモリバス制御プロセッサ
US5267047A (en) * 1991-04-30 1993-11-30 International Business Machines Corporation Apparatus and method of operation for a facsimilie subsystem in an image archiving system
US5732164A (en) * 1991-05-23 1998-03-24 Fujitsu Limited Parallel video processor apparatus
JP3040529B2 (ja) * 1991-05-23 2000-05-15 富士通株式会社 動画像処理装置
US5148112A (en) * 1991-06-28 1992-09-15 Digital Equipment Corporation Efficient arbiter
JP2906792B2 (ja) * 1991-11-15 1999-06-21 日本電気株式会社 ディジタルプロセッサ及びその制御方法
DE4344157A1 (de) * 1993-12-23 1995-06-29 Philips Patentverwaltung Funkgerät
GB2285524B (en) * 1994-01-11 1998-02-04 Advanced Risc Mach Ltd Data memory and processor bus
US6160560A (en) * 1998-08-10 2000-12-12 Diamond Multimedia Systems, Inc. Graphic request management system

Family Cites Families (4)

* Cited by examiner, † Cited by third party
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US4037210A (en) * 1973-08-30 1977-07-19 Burroughs Corporation Computer-peripheral interface
US4263649A (en) * 1979-01-05 1981-04-21 Mohawk Data Sciences Corp. Computer system with two busses
US4384323A (en) * 1980-02-25 1983-05-17 Bell Telephone Laboratories, Incorporated Store group bus allocation system
US4837785A (en) * 1983-06-14 1989-06-06 Aptec Computer Systems, Inc. Data transfer system and method of operation thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8704826A1 *

Also Published As

Publication number Publication date
WO1987004826A1 (fr) 1987-08-13
JPS63502535A (ja) 1988-09-22

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