EP0239059A2 - Logische Schaltung - Google Patents

Logische Schaltung Download PDF

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Publication number
EP0239059A2
EP0239059A2 EP87104268A EP87104268A EP0239059A2 EP 0239059 A2 EP0239059 A2 EP 0239059A2 EP 87104268 A EP87104268 A EP 87104268A EP 87104268 A EP87104268 A EP 87104268A EP 0239059 A2 EP0239059 A2 EP 0239059A2
Authority
EP
European Patent Office
Prior art keywords
logical
transistors
circuit
type
output signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP87104268A
Other languages
English (en)
French (fr)
Other versions
EP0239059A3 (en
EP0239059B1 (de
Inventor
Hiroyuki Hara
Yasuhiro Sugimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
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Toshiba Corp
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Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of EP0239059A2 publication Critical patent/EP0239059A2/de
Publication of EP0239059A3 publication Critical patent/EP0239059A3/en
Application granted granted Critical
Publication of EP0239059B1 publication Critical patent/EP0239059B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]

Definitions

  • the present invention relates to improved logical circuits having a high speed, current driving capability by the use of CMOS transistors and bipolar transistors.
  • Fig. l shows a logical circuit consisting of CMOS transistors i.e., two-input NAND circuit, which is comprised of a NAND operational portion l and two inverter circuits 3 and 5 connected in series.
  • the NAND operational portion l consists of a pair of P-channel MOS transistor (which is referred to as PMOS transistor hereafter respectively) 7 and N-channel MOS transistors (which is referred to hereafter as NMOS transistor, respectively) 9 and ll, and PMOS transistor l3 and NMOS transistors l5 and l7 which are connected between power supply V DD and ground and which perform the NAND logical operation of the input signals applied to the input terminals A and B.
  • the inverter circuit 5 constitutes an output stage of the NAND operational portion l and it produces the result of the operation performed in the NAND operational portion l from the output terminal C after amplifying it.
  • the current driving performance is increased by making the size of the MOS transistors in the output stage large in accordance with the conditions of the load capacity, so as to perform the high speed operation in the NAND circuit according to the prior art.
  • this kind of the approach according to the prior art results in a large size of the circuit and this becomes an obstacle, particular in view of realization of less miniaturization in the integrated circuits.
  • the NAND circuit is constructed only by the bipolar transistors, the current driving performance can be increased, to be sure. However, a current tends to flow through the circuit even in the steady state, thus increasing the power consumption.
  • the power consumption may be reduced in a sense by constructing the logical circuit by the use of only the CMOS transistors, it becomes difficult to obtain a large current driving performance from the miniaturized circuits.
  • a logical circuit which comprises: a logical operational portion consisting of first and second type MOS transistors for performing a logical operation of input signals; an output control portion having an inverter for inverting an output signal from the operational portion and the remaining circuit portion comprising a first bipolar transistor connected between power supply and the ground and conductively controlled by the output signal from the inverter circuit, a first-type first MOS transistor conductively controlled by the output signal from the logical operational portion, a first-type second MOS transistor connected between an output terminal and the ground and conductively controlled by the emitter potential of the bipolar transistor, a first-type third MOS transistor conductively controlled by the output signal from the inverter circuit and a first-type fourth MOS transistor conductively controlled by the output signal from the logical operational portion, the first-type third and fourth MOS transistors being connected in series between the output terminal and the ground; and an output portion consisting of a second bipolar transistor conductively controlled by the output signal from the logical operational
  • a logical circuit which comprises: a logical operational portion consisting of first and second type MOS transistors for performing a logical operation of input signals; an output control portion having an inverter circuit portion for inverting an output signal from the operational portion and the remaining circuit portion comprising a first bipolar transistor connected between power supply and the ground and conductively controlled by the output signal from the logical operational portion, a first-type first MOS transistor conductively controlled by the output signal from the logical operational portion, a first-type second MOS transistor connected between the power supply and the ground and conductively controlled by the emitter potential of the first bipolar transistor, a first-type third MOS transistor conductively controlled by the output signal from the inverter circuit and a first-type fourth MOS transistor conductively controlled by the output signal from the operational portion, first-type third and fourth MOS transistors being connected in series between the output terminal and the ground; an output portion consisting of a second bipolar transistor conductively controlled by the output signal from the inverter circuit
  • Fig. 2 shows one embodiment of the logical NAND circuit according to the present invention which comprises a NAND operational portion 2l, an output portion 23, and an output control portion 25.
  • the NAND operational portion 2l is comprises of the PMOS transistors 27 and 29 and the NMOS transistors 3l and 33.
  • the PMOS transistors 27 and 29 have its gate terminal or electrode connected to each of the input terminals IN l and IN 2 through each of resistors R, R for input protection, its source electrode connected to the power supply V DD and its drain electrode connected to each other, respectively.
  • the NMOS transistors have its gate electrode connected to each of the input terminals IN 2 through each of the resistors R, R for the input protection, and each of the NMOS transistors is connected in series to each other, between the drain electrode of the PMOS transistor 27 and the ground.
  • the NAND operational portion 2l performs logical NAND operation of the input signals applied to the input terminals IN l and IN 2 and produces the result of the operation at the output terminal 35.
  • the output portion 23 comprises two NPN-type bipolar transistors 27 and 39 (which is referred to as Bi-NPN transistor hereafter, respectively) connected to in a totem pole manner.
  • the Bi-NPN transistor 37 has its base electrode connected to the output terminal 35 of the NAND operational circuit, its collector electrode connected to the power supply V DD , and its emitter connected to the output terminal OUT to be connected to a load, not shown here, respectively.
  • the Bi-NPN transistor 39 has its collector connected to the output terminal OUT and its emitter connected to the ground, respectively.
  • the output control portion 25 comprises an inverter circuit 4l, a Bi-NPN transistor 43 and four NMOS transistors 45, 47, 49, and 5l.
  • the inverter circuit 4l is connected in series between the power supply V DD and the ground and it comprises the PMOS transistor 53 and the NMOS transistor 55 which have its gate electrode connected to the output terminal 35, respectively.
  • the Bi-NPN transistor 43 has its base terminal connected to the drain electrode of the PMOS transistor 53 and its collector terminal connected to the power supply V DD .
  • the NMOS transistor 45 has its gate terminal connected to the output terminal 35, its drain electrode connected to the emitter electrode of the Bi-NPN transistor 43 and its source electrode connected to the ground.
  • the NMOS transistor 47 has its gate electrode connected to the emitter of the Bi-NPN transistor 43, its drain electrode connected to the output terminal OUT, and its source electrode connected to the ground, respectively.
  • the NMOS transistor 47 is provided so as to permit the output terminal OUT to be the ground potential in a low level condition of the output terminal OUT by flowing a current from the output terminal OUT to the ground.
  • the NMOS transistor 47 is not necessarily required to be large and it depends upon its application. In other words, the size of the NMOS transistor 47 is normally made large in order to increase the current IoL, but it is basically for permitting the output signal to be the ground level as its function.
  • the NMOS transistor 49 has its gate electrode connected to the base terminal of the Bi-NPN transistor 43, its drain electrode connected to the output terminal OUT, and its source electrode connected to the base terminal of the Bi-NPN transistor 39.
  • the NMOS transistor 5l has its gate electrode connected to the output terminal 35, its drain electrode connected to the base terminal of the Bi-NPN transistor 39 and its source electrode connected to the ground.
  • the output control portion 25 thus constructed functions to control the ON and OFF conditions of Bi-NPN transistor 39 and the NMOS transistor 47 in accordance with the signal applied from the output terminal 35.
  • the PMOS transistors 27 and 29 are rendered non-conductive while the NMOS transistors 3l and 33 are rendered conductive.
  • the output terminal 35 becomes a low level condition and this in turn renders the Bi-NPN transistor 37 non-conductive, as well as rendering the MOS transistors 45 and 5l non-conductive.
  • the PMOS transistor 53 constituting the inverter circuit 4l is rendered conductive while the NMOS transistor 55 is rendered non-conductive. Consequently, the base terminal of the Bi-NPN transistor 43 becomes a high level condition and the Bi-NPN transistors 43 and 47 as well as the Bi-NPN transistor 47 are rendered conductive.
  • the gate electrode of the NMOS transistor 49 becomes high level condition and it is rendered conductive.
  • a current flows from a load to be connected to the output terminal OUT to the base terminal of the Bi-NPN transistor 39, thus rendering it conductive.
  • the Bi-NPN 37 is rendered conductive. This in turn renders the NMOS transistors 45 and 5l conductive and the gate electrode of the NMOS transistor 47 as well as the gate electrode of the Bi-NPN transistor 39 becomes low level condition respectively, while the NMOS transistor 47 and Bi-NPN transistor 39 are rendered non-conductive.
  • a current flows from the power supply V DD to the load to be connected to the output terminal OUT, so that the potential at the output terminal OUT is increased up to near the power supply voltage and the potential at the output terminal OUT becomes high level condition.
  • a low level input signal is applied to either one of the input terminals IN l and IN 2
  • a high level output signal is produced at the output terminal OUT. Accordingly, the NAND operation can be performed in this circuit.
  • Fig. 3 shows the result of simulation of response between the input signal and the output signal obtained from the NAND circuit shown in Fig. 2.
  • the time T1 during which the input signal is increased to l/2 potential of the input amplitude and the output signal is decreased to l/2 potential of the output amplitude is 3.0 nsec and the time T2 during which the input signal is decreased to l/2 potential of the input amplitude and the output signal is increased to l/2 potential of the output amplitude is 3.5 nsec. This means that a high speed NAND operations can be performed.
  • Figs. 4 and 5 show respectively the current driving performance of the NAND circuit of Fig. 2.
  • Fig. 5 shows the characteristic of high level voltage VoH vs. high level current IoH. It will be appreciated from this characteristic that the current IoH becomes l00 mA when the voltage VoH is 2.8 V. This shows that a sufficient value can be obtained both in the voltage and current of IoL and VoL, thus realizing the high current driving performance.
  • power consumption can be reduced, as well.
  • Fig. 6 shows another embodiment of the NAND circuit according to the present invention.
  • the inverter circuit 4l consisting of the CMOS transistors is connected to between the output terminal 35 of the NAND operational portion 2l and the base terminal of the Bi-NPN transistor 37 which constitutes the output portion 23 while the output terminal 35 is directly connected to the base terminal of the Bi-NPN transistor l3, so as to perform AND operation.
  • the same NAND function as that of Fig. 2 can be realized as a whole by this circuit.
  • same reference numerals are attached to the same constructing elements as those of the first embodiment shown in Fig. 2.
  • the logical NAND operation of the input signals is performed in the NAND circuit constructed in such a manner that the output stage is constructed by bipolar transistors, and conductive and non-conductive conditions of the bipolar transistors are controlled in accordance with the result of the operation in the logical operational portion which consists of CMOS transistors, a high current driving performance can be obtained without making the circuit construction large, yet with reduced power consumption.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
EP87104268A 1986-03-22 1987-03-23 Logische Schaltung Expired - Lifetime EP0239059B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62009/86 1986-03-22
JP61062009A JPS62221219A (ja) 1986-03-22 1986-03-22 論理回路

Publications (3)

Publication Number Publication Date
EP0239059A2 true EP0239059A2 (de) 1987-09-30
EP0239059A3 EP0239059A3 (en) 1988-02-03
EP0239059B1 EP0239059B1 (de) 1992-06-17

Family

ID=13187725

Family Applications (1)

Application Number Title Priority Date Filing Date
EP87104268A Expired - Lifetime EP0239059B1 (de) 1986-03-22 1987-03-23 Logische Schaltung

Country Status (5)

Country Link
US (1) US4733110A (de)
EP (1) EP0239059B1 (de)
JP (1) JPS62221219A (de)
KR (1) KR900003070B1 (de)
DE (1) DE3779784T2 (de)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3909282A1 (de) * 1989-03-21 1990-10-11 Fraunhofer Ges Forschung Fet-ttl-interfaceschaltung
EP0398808A2 (de) * 1989-05-17 1990-11-22 Fujitsu Limited Pegelkonverterschaltkreis zur Umsetzung von ELC-Signalen in TTL-Pegelsignale
DE3941840A1 (de) * 1989-03-21 1991-01-24 Fraunhofer Ges Forschung Schaltung
EP0421448A2 (de) * 1989-10-06 1991-04-10 Kabushiki Kaisha Toshiba Ausgangsschaltung mit bipolaren Transistoren im Ausgang, zur Verwendung in einem MOS-IC

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6382122A (ja) * 1986-09-26 1988-04-12 Toshiba Corp 論理回路
JPS63164612A (ja) * 1986-12-26 1988-07-08 Hitachi Ltd 演算回路
JPS63193720A (ja) * 1987-02-06 1988-08-11 Toshiba Corp 論理回路
JPS63209220A (ja) * 1987-02-26 1988-08-30 Toshiba Corp インバ−タ回路
JPH0611111B2 (ja) * 1987-03-27 1994-02-09 株式会社東芝 ＢｉＭＯＳ論理回路
JPH01129451A (ja) * 1987-11-16 1989-05-22 Fujitsu Ltd 半導体装置
JP2593894B2 (ja) * 1987-11-16 1997-03-26 富士通株式会社 半導体記憶装置
US4794280A (en) * 1988-02-16 1988-12-27 Texas Instruments Incorporated Darlington bicmos driver circuit
US5030860A (en) * 1988-02-16 1991-07-09 Texas Instruments Incorporated Darlington BiCMOS driver circuit
US4883979A (en) * 1988-02-16 1989-11-28 Texas Instruments Incorporated Darlington BiCMOS driver circuit
US4871928A (en) * 1988-08-23 1989-10-03 Motorola Inc. BICMOS driver circuit with complementary outputs
US4956567A (en) * 1989-02-13 1990-09-11 Texas Instruments Incorporated Temperature compensated bias circuit
JPH02214219A (ja) * 1989-02-14 1990-08-27 Nec Corp バイポーラｍｏｓ３値出力バッファ
US5030856A (en) * 1989-05-04 1991-07-09 International Business Machines Corporation Receiver and level converter circuit with dual feedback
EP0403075B1 (de) * 1989-05-15 1996-04-17 Texas Instruments Incorporated BICMOS-Hochleistungsschaltkreis mit voller Ausgangsspannungsschwingung
US5022010A (en) * 1989-10-30 1991-06-04 International Business Machines Corporation Word decoder for a memory array
EP0426597B1 (de) * 1989-10-30 1995-11-08 International Business Machines Corporation Bitdekodierungsschema für Speichermatrizen
JPH03169273A (ja) * 1989-11-22 1991-07-22 Mitsubishi Electric Corp スイッチングデバイス駆動回路
US5250856A (en) * 1989-12-28 1993-10-05 North American Philips Corp. Differential input buffer-inverters and gates
JP2740769B2 (ja) * 1990-08-23 1998-04-15 株式会社東芝 可変分周回路
DE69126832T2 (de) * 1990-08-29 1997-11-20 Nec Corp BiCMOS logische Schaltung
US5132567A (en) * 1991-04-18 1992-07-21 International Business Machines Corporation Low threshold BiCMOS circuit
US5191240A (en) * 1991-06-05 1993-03-02 International Business Machines Corporation Bicmos driver circuits with improved low output level

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4301383A (en) * 1979-10-05 1981-11-17 Harris Corporation Complementary IGFET buffer with improved bipolar output
EP0099100A1 (de) * 1982-07-12 1984-01-25 Hitachi, Ltd. Gateschaltung mit Feldeffekt- und Bipolartransistoren
EP0132822A2 (de) * 1983-07-25 1985-02-13 Hitachi, Ltd. Zusammengesetzte Schaltung aus bipolaren und Feldeffekt-Transistoren
EP0196113A2 (de) * 1985-03-29 1986-10-01 Kabushiki Kaisha Toshiba Tri-state-Pufferschaltung
EP0212004A2 (de) * 1985-07-01 1987-03-04 Kabushiki Kaisha Toshiba Halbleiter-Inverterschaltung mit Bipolartransistor zur schnellen Verarbeitung von Ein-/Ausgangssignalen

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4253033A (en) * 1979-04-27 1981-02-24 National Semiconductor Corporation Wide bandwidth CMOS class A amplifier
KR910008521B1 (ko) * 1983-01-31 1991-10-18 가부시기가이샤 히다찌세이사꾸쇼 반도체집적회로
JPS59205828A (ja) * 1983-05-10 1984-11-21 Nec Corp 出力回路
JPS6090427A (ja) * 1983-10-24 1985-05-21 Nec Corp 出力回路
JPS60177723A (ja) * 1984-02-24 1985-09-11 Hitachi Ltd 出力回路
US4678940A (en) * 1986-01-08 1987-07-07 Advanced Micro Devices, Inc. TTL compatible merged bipolar/CMOS output buffer circuits

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4301383A (en) * 1979-10-05 1981-11-17 Harris Corporation Complementary IGFET buffer with improved bipolar output
EP0099100A1 (de) * 1982-07-12 1984-01-25 Hitachi, Ltd. Gateschaltung mit Feldeffekt- und Bipolartransistoren
EP0132822A2 (de) * 1983-07-25 1985-02-13 Hitachi, Ltd. Zusammengesetzte Schaltung aus bipolaren und Feldeffekt-Transistoren
EP0196113A2 (de) * 1985-03-29 1986-10-01 Kabushiki Kaisha Toshiba Tri-state-Pufferschaltung
EP0212004A2 (de) * 1985-07-01 1987-03-04 Kabushiki Kaisha Toshiba Halbleiter-Inverterschaltung mit Bipolartransistor zur schnellen Verarbeitung von Ein-/Ausgangssignalen

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3909282A1 (de) * 1989-03-21 1990-10-11 Fraunhofer Ges Forschung Fet-ttl-interfaceschaltung
DE3941840A1 (de) * 1989-03-21 1991-01-24 Fraunhofer Ges Forschung Schaltung
EP0398808A2 (de) * 1989-05-17 1990-11-22 Fujitsu Limited Pegelkonverterschaltkreis zur Umsetzung von ELC-Signalen in TTL-Pegelsignale
EP0398808A3 (de) * 1989-05-17 1991-07-03 Fujitsu Limited Pegelkonverterschaltkreis zur Umsetzung von ELC-Signalen in TTL-Pegelsignale
US5138199A (en) * 1989-05-17 1992-08-11 Fujitsu Limited Level conversion circuit for converting ecl-level signal into ttl-level signal
EP0421448A2 (de) * 1989-10-06 1991-04-10 Kabushiki Kaisha Toshiba Ausgangsschaltung mit bipolaren Transistoren im Ausgang, zur Verwendung in einem MOS-IC
EP0421448A3 (en) * 1989-10-06 1991-08-14 Kabushiki Kaisha Toshiba Signal output circuit having bipolar transistors at output, for use in a mos semiconductor integrated circuit

Also Published As

Publication number Publication date
US4733110A (en) 1988-03-22
JPS62221219A (ja) 1987-09-29
KR900003070B1 (ko) 1990-05-07
EP0239059A3 (en) 1988-02-03
EP0239059B1 (de) 1992-06-17
KR870009553A (ko) 1987-10-27
DE3779784D1 (de) 1992-07-23
DE3779784T2 (de) 1992-12-24

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