EP0237086A1 - Circuit de miroir de courant - Google Patents

Circuit de miroir de courant Download PDF

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Publication number
EP0237086A1
EP0237086A1 EP87200162A EP87200162A EP0237086A1 EP 0237086 A1 EP0237086 A1 EP 0237086A1 EP 87200162 A EP87200162 A EP 87200162A EP 87200162 A EP87200162 A EP 87200162A EP 0237086 A1 EP0237086 A1 EP 0237086A1
Authority
EP
European Patent Office
Prior art keywords
transistor
base
emitter
current
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP87200162A
Other languages
German (de)
English (en)
Other versions
EP0237086B1 (fr
Inventor
Karl-Heinz Matthies
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Intellectual Property and Standards GmbH
Koninklijke Philips NV
Original Assignee
Philips Patentverwaltung GmbH
Philips Gloeilampenfabrieken NV
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Patentverwaltung GmbH, Philips Gloeilampenfabrieken NV, Koninklijke Philips Electronics NV filed Critical Philips Patentverwaltung GmbH
Publication of EP0237086A1 publication Critical patent/EP0237086A1/fr
Application granted granted Critical
Publication of EP0237086B1 publication Critical patent/EP0237086B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/265—Current mirrors using bipolar transistors only

Definitions

  • the invention relates to a current mirror circuit having a first transistor, whose emitter is coupled to a voltage source and whose collector and base are coupled to a node for supplying an input current, and to at least one second transistor, whose emitter is connected to the voltage source and whose base the base of the first transistor is coupled and the collector of which forms the output for outputting an output current.
  • Such a current mirror circuit is e.g. from the book by Jovan Antula, circuits for microelectronics, Oldenbourg-Verlag, l984, pages 56 to 59, known.
  • the function of a current mirror circuit is to generate an output current that is in a fixed ratio to the input current.
  • a current mirror circuit is known to have a low input resistance and a high output resistance. The output current changes very little under load. Furthermore, such a circuit is largely independent of temperature influences.
  • the input current is approximately equal to the output current at high DC amplification factors.
  • the symmetry error of the current mirror circuit which is caused by the base currents of the two transistors, is almost negligible at high DC amplification factors.
  • Current mirror circuits are mainly used in integrated circuits.
  • the following problem can occur when using PNP transistors.
  • the current gain depends largely on the emitter area of a PNP transistor.
  • a change in the emitter area means a change in the current gain.
  • sample variations can occur that the symmetry errors can no longer be neglected.
  • the invention has for its object to design a circuit arrangement of the type mentioned in such a way that the symmetry errors are reduced.
  • a compensation circuit constructed with further transistors supplies the node with a compensation current which essentially corresponds to the sum of the base currents of the first and second transistors.
  • the compensation circuit compensates for the symmetry error caused by the base currents of the two current mirror transistors.
  • the emitter of the first transistor is coupled to the voltage source via a first resistor, and the emitter of the second transistor via a second resistor, which has almost the same value as the first.
  • the first and second resistors prevent different base-emitter voltages of the two current mirror transistors caused by scatter from changing the function of the current mirror circuit.
  • a third resistor is arranged between the base of the first transistor and the node. With the help of this third resistor it is achieved that a pulse is transmitted essentially undistorted via the current mirror circuit.
  • the third resistor should have essentially the same value as the first resistor.
  • the first and second transistors are each PNP transistors and that the compensation current generated by the compensation circuit, which contains further PNP transistors, in the same way from the emitter area of the PNP transistors in the compensation circuit depends on the sum of the base currents of the first and second transistor on their emitter area.
  • a compensation current is generated in the compensation circuit, the size of which depends on the emitter area of the PNP transistors used in the compensation circuit.
  • the scattering of the emitter surface between different specimens that occurs during the manufacture of integrated circuits causes one in each case another DC gain factor, since the DC gain factor depends on the emitter area of a transistor.
  • the compensation current and the sum of the base currents of the first and second PNP transistors are determined by the emitter area of the transistors.
  • a third PNP transistor the base of which is coupled to the node and the emitter of which is connected to the voltage source, its collector current via an emitter-base path of a fourth PNP transistor, the collector of which a reference potential, feeds an inverting amplifier which supplies the node with a current from its output which is substantially equal to the sum of the base currents of the first, second and third PNP transistors.
  • the emitter of the third transistor can be coupled to the voltage source via a fourth resistor.
  • the current at the output of the amplifier corresponds to the base current of the first, second and third PNP transistors.
  • the emitter area of the third and fourth PNP- Transistor has a constant ratio to the emitter area of the first and second PNP transistor.
  • the fourth resistor and the DC gain factor of the amplifier must be chosen so that the amplifier delivers a current that is the sum of the base currents of the first, second and third Transistor corresponds.
  • the value of the fourth resistor can now be chosen so that it is substantially equal to twice the value of the first resistor and the DC amplification factor of the inverting amplifier so that it has a value of 3.
  • the base current of the third PNP transistor is approximately as large as half the total current of the base currents of the first and second PNP transistors.
  • the inverting amplifier contains a first NPN transistor, the collector and base of which are coupled to the base of the fourth PNP transistor and the emitter of which is coupled to the reference potential, and a second NPN transistor, the emitter area of which is substantially equal to three times the emitter area of the first NPN transistor and its base is coupled to the base of the first NPN transistor and its emitter is coupled to the reference potential and its collector is coupled to the node.
  • the amplifier is designed here as a simple current mirror circuit made of NPN transistors, which generally have such a high amplification that the symmetry errors caused by the base currents are barely noticeable.
  • the input current Ye flows to a node 1, which connects the compensation circuit 2 and the collector of a first PNP transistor 3, the base of a second PNP transistor 4 and a connection of a resistor 5.
  • the other connection of the resistor 5 is connected to the base of the transistor 3.
  • the emitter of transistor 3 is connected via a resistor 6 and the emitter of transistor 4 via a resistor 7 to a voltage source Ub.
  • the output current Ya is the current Mirror circuit is supplied by the collector of transistor 4.
  • the resistors 6 and 7 should be chosen so that a voltage drops across them, which is greater than a third of the base-emitter voltage of the transistor 3 or 4.
  • Resistors 6 and 7 prevent different base-emitter voltages of transistor 3 and 4 from changing the function of the current mirror circuit.
  • the base of a PNP transistor 8 is connected to the node 1, the emitter of which is connected to the voltage source Ub via a resistor 9 and the collector of which is connected to the emitter of a PNP transistor 12.
  • the collector of transistor l2 is grounded and its base is connected to the base and collector of an NPN transistor l0.
  • the emitter of this transistor l0 like the emitter of an NPN transistor ll, is grounded, the base of which is connected to the base of transistor l0 and the collector of which is connected to node l.
  • the transistors l0 and ll form a simple current mirror circuit in which only very small negligible symmetry errors occur, since the direct current gain of an NPN transistor is usually very high.
  • the emitter area of transistor 8 or transistor l2 is equal to half the emitter area of transistor 3 or transistor 4.
  • the emitter area of transistor ll is equal to three times the emitter area of transistor l0.
  • the emitter area of the NPN transistor 10 can, for example, equal one sixth and the emitters area of NPN transistor ll be equal to half the emitter area of transistor 3 or transistor 4.
  • the inverting amplifier formed from the NPN transistors l0 and ll has a direct current amplification factor of 3.
  • the value of the resistor 9 is equal to twice the value of the resistor 6 or the resistor 7.
  • an output current is to be generated which is in a fixed ratio to the input current, e.g. a ratio of one.
  • the current mirror circuit has a symmetry error which is caused by the two base currents of the transistors 3 and 4.
  • a compensation current is generated which counteracts the sum of the base currents of the transistors 3 and 4. This compensation current is approximately equal to twice the base current of transistor 8.
  • Such a current mirror circuit is generally used in an integrated circuit.
  • the emitter areas of the transistors can be different in the different examples of the integrated circuit. These emitter areas do not change relative to each other, only the absolute size of the emitter area of a transistor can change. Since the direct current gain of the transistors is dependent on the emitter area, different examples of the current mirror circuit also have different direct current gains. With a change in the direct current gain, there is also a change in the base currents of the transistors 3 and 4. Since the emitter areas of the transistors 8, 9, 10 and 11 also change, their direct current gain and thus the compensation current also change. The current mirror circuit according to the invention can therefore also be used if the direct current gains are very small, since the symmetry errors which would have an effect in the known current mirror circuit are compensated for.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)
EP87200162A 1986-02-07 1987-02-03 Circuit de miroir de courant Expired - Lifetime EP0237086B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19863603799 DE3603799A1 (de) 1986-02-07 1986-02-07 Stromspiegelschaltung
DE3603799 1986-02-07

Publications (2)

Publication Number Publication Date
EP0237086A1 true EP0237086A1 (fr) 1987-09-16
EP0237086B1 EP0237086B1 (fr) 1991-07-10

Family

ID=6293591

Family Applications (1)

Application Number Title Priority Date Filing Date
EP87200162A Expired - Lifetime EP0237086B1 (fr) 1986-02-07 1987-02-03 Circuit de miroir de courant

Country Status (4)

Country Link
US (1) US4779061A (fr)
EP (1) EP0237086B1 (fr)
JP (1) JP2542605B2 (fr)
DE (2) DE3603799A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013039948A1 (fr) 2011-09-12 2013-03-21 Merial Limited Compositions antiparasitaires comprenant un agent actif d'isoxazoline, procédés et utilisations associés

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4853610A (en) * 1988-12-05 1989-08-01 Harris Semiconductor Patents, Inc. Precision temperature-stable current sources/sinks
US4975632A (en) * 1989-03-29 1990-12-04 Texas Instruments Incorporated Stable bias current source
US5089769A (en) * 1990-11-01 1992-02-18 Motorola Inc. Precision current mirror
US5287231A (en) * 1992-10-06 1994-02-15 Vtc Inc. Write circuit having current mirrors between predriver and write driver circuits for maximum head voltage swing
DE4443469C2 (de) * 1994-12-07 1997-10-23 Telefunken Microelectron Schaltungsanordnung mit einem Bipolartransistor
US5864231A (en) * 1995-06-02 1999-01-26 Intel Corporation Self-compensating geometry-adjusted current mirroring circuitry
DE60140428D1 (de) * 2001-04-30 2009-12-24 Avago Tech Fiber Ip Sg Pte Ltd Stromversorgung und Verfahren zur Stromversorgung eines Diodenlasertreibers

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4103249A (en) * 1977-10-31 1978-07-25 Gte Sylvania Incorporated Pnp current mirror
EP0103768A1 (fr) * 1982-08-24 1984-03-28 Siemens Aktiengesellschaft Circuit à miroir de courant
US4525683A (en) * 1983-12-05 1985-06-25 Motorola, Inc. Current mirror having base current error cancellation circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1042763B (it) * 1975-09-23 1980-01-30 Ates Componenti Elettron Circuita specchio di correnti compensato in temperatura
JPS5922112A (ja) * 1982-07-28 1984-02-04 Toshiba Corp 電流源回路
JPS59108411A (ja) * 1982-12-13 1984-06-22 Mitsubishi Electric Corp 電流源回路
US4525682A (en) * 1984-02-07 1985-06-25 Zenith Electronics Corporation Biased current mirror having minimum switching delay

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4103249A (en) * 1977-10-31 1978-07-25 Gte Sylvania Incorporated Pnp current mirror
EP0103768A1 (fr) * 1982-08-24 1984-03-28 Siemens Aktiengesellschaft Circuit à miroir de courant
US4525683A (en) * 1983-12-05 1985-06-25 Motorola, Inc. Current mirror having base current error cancellation circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013039948A1 (fr) 2011-09-12 2013-03-21 Merial Limited Compositions antiparasitaires comprenant un agent actif d'isoxazoline, procédés et utilisations associés

Also Published As

Publication number Publication date
DE3771237D1 (de) 1991-08-14
DE3603799A1 (de) 1987-08-13
US4779061A (en) 1988-10-18
JPS62230106A (ja) 1987-10-08
JP2542605B2 (ja) 1996-10-09
EP0237086B1 (fr) 1991-07-10

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