EP0178424B1 - Multiplieur numérique sémisystolique à structure cellulaire - Google Patents

Multiplieur numérique sémisystolique à structure cellulaire Download PDF

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Publication number
EP0178424B1
EP0178424B1 EP85110468A EP85110468A EP0178424B1 EP 0178424 B1 EP0178424 B1 EP 0178424B1 EP 85110468 A EP85110468 A EP 85110468A EP 85110468 A EP85110468 A EP 85110468A EP 0178424 B1 EP0178424 B1 EP 0178424B1
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EP
European Patent Office
Prior art keywords
cells
row
cell
bits
partial product
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EP85110468A
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German (de)
English (en)
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EP0178424A3 (en
EP0178424A2 (fr
Inventor
Tobias Dipl.-Ing. Noll
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Siemens AG
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Siemens AG
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Priority to AT85110468T priority Critical patent/ATE60675T1/de
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5306—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products
    • G06F7/5312—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products using carry save adders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/388—Skewing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3884—Pipelining

Definitions

  • the invention relates to a cell-structured digital multiplier with a semi-systolic structure according to the preamble of claim 1.
  • a multiplier of this kind is from the IEEE Journal of Solid-State Circuits Vol. SC-18 (1983) No. 3, pages 280 to 285, in particular FIG. 7 and from IEEE Transactions on Computers Vol. C-27 (1978), pages 855-865, in particular FIG. 7 (b).
  • the disadvantage here is that the second input lines, via which a multiplier bit is supplied to all cells of a row, must be provided with driver circuits, particularly in the case of multiplicands with large word widths, the running times of which together with the running times of the parts of the between the driver circuits and the relevant cells second input lines delay the supply of the multiplier bit. This results in a significant increase in the stage delay that elapses between the output of the sum and carry signals at the outputs of the shift register stages of one line and the output of corresponding signals at the outputs of the shift register stages of the next line.
  • a fully systolic multiplier device in which each individual cell is divided into a first sub-cell which contains a partial product-forming link and a second sub-cell which contains the full adder. Both sub-cells are connected to one another by a connecting line connected, which is connected to the output of the logic element and to an input of the full adder. A shift register stage is inserted into this connecting line and is used for the temporary storage of the partial product formed in the link.
  • the multiplier bits are fed to all cells of a row one after the other, one after the other, at a time interval of one or more clock pulse periods.
  • the invention has for its object to provide a cell-structured multiplier of the type indicated, in which the said delay in the Feeding the multiplier bits does not adversely affect the step delay. This is achieved according to the invention by designing the multiplier according to the characterizing part of patent claim 1.
  • the advantage which can be achieved with the invention is in particular that the delay which occurs when a multiplier bit is supplied to the cells of a row in question occurs during the step runtime which is provided for the cells combined in the previous row.
  • the partial product bits for the line under consideration are also formed and temporarily stored within this step duration. Therefore, both the required sum signals and carry signals of the cells of the previous line, which are temporarily stored in register stages, and the partial product bits, which are temporarily stored in other register stages of this previous line and assigned to the line in question, can be supplied to the line in question, so that the stage runtime of the line in question corresponds to the processing time the full adder in it is reduced. The same applies to the step run times of all lines.
  • FIG. 1 corresponds essentially to the known multiplier according to FIG. 7 (b) of the above-mentioned IEEE article.
  • first input lines L0 to L3 are provided, the upper connections of which are occupied with the bits x0 to x3 of a multiplicand MD present as a binary signal.
  • x0 represents the least significant bit of MD.
  • Second input lines ZL0 to ZL3 are connected at their upper terminals with bits y0 to y3 of a multiplier MT, which is also present as a binary signal, where y0 means the least significant bit.
  • Z11 to Z14 denote four cells of the multiplier combined in a first row.
  • the structure of one of these cells which are essentially identical to one another, e.g. of Z33, which can also be found in FIG. 4 on page 862 of the article mentioned, will be explained in more detail with reference to FIG. 2.
  • the lines L2 and ZL2, which have a crossing point in the area of Z33, are connected to the two inputs of an AND gate 1, the output of which is connected to the input 2 of a full adder 3.
  • Another input 4 of the full adder 3 is connected to the part of a summation path 5 described in more detail below, via which a summation signal is received.
  • a third input 6 of FIG. 3 is connected to the part of a treated carry path 7, which will also be discussed below, via which a carry signal is received.
  • the sum output 8 of FIG. 3 is connected to a second part of the sum path 5, via which a sum signal is emitted.
  • the carry output 9 of FIG. 3 is connected to a second part of the carry path 7, via which a carry signal is emitted.
  • the total path 5 runs according to FIG. 1 via cells Z24, Z33 and Z42. Further total paths are with 10 to 14 designated and run respectively via Z14, Z23, Z32 and Z41, via Z13, Z22 and Z31, via Z12 and Z21, via Z34 and Z43 and via Z44.
  • a path denoted by 15 can also be understood as a summation path, but runs only via cell Z11.
  • the cells Z11 to Z14 can be of simpler design than the other cells in that they do not have to contain a full adder. With them, the output of the AND gate 1 can each be connected to a part of a summation path connected at the bottom right point, via which a signal is emitted.
  • Each of the drawn sections of the sum paths 5 and 10 to 13 means that the signal emerging at the bottom right corner of a cell is fed to the top left corner of the next cell lying on the sum path concerned and thus to the input 4 of its full adder 3.
  • the transmission path 7 runs in FIG. 1 via cells Z23, Z33 and Z43. Further transmission paths are designated 16 to 18 and each run via cells Z24, Z34 and Z44, via cells Z22, Z32 and Z42 or via cells Z21, Z31 and Z41.
  • Each of the drawn sections of these carry paths means that a carry signal emitted at the lower limit of a cell and coming from the carry output 9 of this cell is fed to the upper limit of the next cell on the path and from there to the input 6 of its full adder 3.
  • the lower-order product bits P0 to P3 can be tapped directly.
  • the higher-order product bits are generated from those occurring at the end connections 19 to 22 of the transmission paths 18, 17, 7 and 16 and at the end connections 23 to 25 of the summation paths 5, 13 and 14 Composite signals.
  • addition stages 26 to 35 are provided, of which stages 26 to 29 are each connected to cells Z41 to Z44 via the extended transmission paths 18, 17, 7 and 16.
  • the extended transmission path 7 also connects the stages 28 and 32, the extended transmission path 17 the stages 27, 31 and 34 and the extended transmission path 18 the stages 26, 30, 33 and 35.
  • each section of an extended transmission path means that a carry signal is tapped at the lower limit of an addition stage and thus at the carry output of the adder located therein and the upper limit of the next addition stage lying on the carry path and from there is fed to one input of the adder located therein.
  • each section of one of the extended sum paths means that a sum signal appearing at the sum output of the adder located in it is tapped at the bottom right corner of a stage and an input of the adder located in the next addition stage lying on the sum path via the top left corner of its limitation is fed. Since only a maximum of two input signals are supplied to stages 26 to 35, their adders can be designed as half adders, which is indicated by the designation HA. The product bits P4 to P7 can then be tapped at the lower ends of the sum paths 5, 13, 14 and 36.
  • Fig. 1 are in the sum and carry outputs, such as 8 and 9 (Fig. 2), of the individual cells, such as Z33, shift register stages, for example 37 and 38, are provided, in which the emitted sum and carry signals are each temporarily stored.
  • further shift register stages, for example 39 are inserted into the input lines L0 to L3 in such a way that a number of register stages corresponding to the number of previous lines is inserted before each branch, such a line which is in the area of a cell, for example Z33 .
  • two further shift register stages 40 and 41 lie in the part of L2 which is located above the branch 39a for Z33.
  • shift register stages for example 42 and 43
  • the second input lines for example ZL2
  • each of which is assigned to a specific row of cells, for example Z31 to Z34, in accordance with the number of previous rows. Since the input line ZL2 in the case under consideration is assigned to the cells Z31 to Z34 in the third row, it accordingly contains two shift register stages 42 and 43.
  • the shift register stages, for example 37 and 38, at the outputs of the individual cells, for example Z33, and the others Shift register stages, for example 39, on the first input lines are expediently included in the individual cells, for example Z33, although they are shown outside the cells for the sake of clarity in FIG. 1.
  • Fig. 1 shows horizontal, dashed lines HL1 to HL4, each indicating the position of the shift register stages at the outputs of the cells in the individual rows.
  • the shift register stages are now clocked so that all of them at the outputs of the cells, eg Z11 to Z14, a line occurring and temporarily stored on the shift register stages indicated by HL1 signals are transmitted within one clock period to the next line of cells, e.g. Z21 to Z24, within the next clock period then the signals occurring at the outputs of this line to the following one Line, for example Z31 to Z34, etc.
  • the product bits P0 to P7 are only available after the signal transmission via the line HL8 .
  • the shift register stages, e.g. 42 and 43 in the second input lines ZL0 to ZL3 as well as the clocked forwarding of the product bits, e.g. P0, by means of the shift register stages, e.g. 44 to 49a, inserted into the sum paths, e.g. 15, all are available for product formation MD and MT require signals, depending on the clock period in question, only between two successive horizontal lines, for example HL3 and HL4, so that in the vertical direction of FIG.
  • the clocking described allows only one circuit stage, i.e. between two adjacent horizontal lines, e.g. HL2 and HL3, located circuit parts of a certain multiplication, eg. from MD with MT.
  • the other stages can be used simultaneously for further multiplications, so that the throughput rate of the circuit (computation rate) is multiplied accordingly.
  • This principle is referred to in the literature as "pipelining".
  • Fig. 3 shows the block diagram of a multiplier designed according to the invention.
  • the second input line ZL1 via which the bit y 1 of the multiplier MT is supplied, does not run via the cells Z21 to Z24, but via the cells Z11 to Z14.
  • the partial product bits which are formed as the results of the AND operation between x0 and y1, x1 and y1, x2 and y1 as well as x3 and y1, are assigned to cells Z21 to Z24 and in these with the sum paths 12, 11 and 10 sum signals supplied by cells Z12, Z13 and Z14 are added, the points of intersection of lines L0 to L3 with ZL1 each lie in the area of cells Z11 to Z14.
  • the formation of the partial product bits which take place in the third and fourth lines according to FIG. 1, also take place in the second and third lines according to FIG. 3, which is indicated by the course of the lines ZL2 and ZL3, their crossing points with the lines L0 to L3 in the cells of the second and third rows.
  • the partial product bit which is to be added in a specific cell, for example Z33, to the sum and carry signals supplied to this cell via a sum path, for example 5, and a carry path, for example 7, in the corresponding cell , eg Z23, the previous line is formed by an AND link, the result of the link being fed to the cell under consideration via a connecting line, eg 58.
  • a multiplier bit is supplied.
  • y2 and the delay occurring in the formation of the partial product bit which results primarily from the running times of a driver circuit, for example 52, and the horizontally drawn part of the input line in question, for example ZL2, into the step running time of the subcircuit between lines HL1 and HL2 relocate.
  • a shift register stage, for example 59, is inserted into the connecting line, for example 58, which can be assigned to the cell of the previous line, for example Z23. It is in Fig. 3 only indicated for reasons of clear representation outside of Z23. It is essential that the shift register stage 59 is simultaneously clocked together with the other shift register stages located at the outputs of the cells Z21 to Z24, which is indicated by the line HL2.
  • the cells Z11 to Z34 i.e. all cells of the first three rows have outputs for connecting lines, e.g. 58, which are led to inputs of the full adders of the corresponding cells of the next row. At all of these outputs there are shift register stages, e.g. 59, which ensure that the cells Z21 to Z44 are assigned the partial product bits assigned to them at the same time as the sum and carry signals of the respective previous line.
  • the step runtimes of the second line formed from cells Z21 to Z24, the third line formed from cells Z31 to Z34 and the fourth line formed from Z41 to Z44 are each reduced to the processing times of the full adders contained in them.
  • FIG. 3 The other parts of FIG. 3 have already been described with reference to FIG. 1 and have the reference numerals also used there.
  • FIG. 4 shows a cell designed according to the invention, for example Z33, of the multiplier according to FIG. 3.
  • a full adder 3 with inputs 2, 4 and 6, a sum output 8 and a carry output 9 is also provided here.
  • the input 2 is connected to the connecting line 58, the input 4 to the summation path 5 and the input 6 to the carry path 7.
  • the sum output 8 is connected to the next section of the summation path 5, the carry output 9 to the next section of the carry path 7
  • One input of an AND gate 60 is connected at node 61 to input line L2, the other input at node 62 to input line ZL3.
  • the shift register stages 37, 38 and 39 are included in the cell Z33 in FIG. 4.
  • a shift register stage 63 which is in the connecting line connected to the output of 60 and leading to input 2 of cell Z43, is shown as part of cell Z33.
  • FIG. 5 shows the block diagram of one of the cells Z11 to Z14 of FIG. 3, which are configured identically to one another, for example that of cell Z13.
  • a partial product bit is formed in the AND gate 63a, which corresponds to either a logical 1 or a logical 0. This is delivered via cell 11 to cell Z22. Since no sum or carry signals are supplied, a full adder can be omitted.
  • an AND gate 64 is provided, the inputs of which are each connected to lines ZL2 and ZL1. The output of 64 is connected to the connecting line 56, which is led to an input of the full adder of Z23.
  • further such stages 65 and 66 are inserted into the connecting line 56 and the summation path 11.
  • FIG. 6 shows a circuit design of the cell Z33 shown schematically in FIG. 4.
  • the full adder 3 contains a NOR gate 67, the two inputs of which are connected to the inputs 2 and 6 of FIG. 3.
  • the two inputs of an AND gate 68 are also connected to inputs 2 and 6.
  • the outputs of 67 and 68 are led to the inputs of a NOR gate 69.
  • the output of 69 is at the first input of a NOR gate 70, the second input of which is connected to the input 4 of FIG. 3.
  • An AND gate 71 has two inputs, which are also connected to the output of 69 and input 4.
  • the outputs of 70 and 71 are connected to the two inputs of a NOR gate 72, the output of which forms the sum output 8 of 3.
  • the output of the NOR gate 67 is still led to the first input of a NOR gate 73.
  • the output of an AND gate 74 the inputs of which are connected to the output of 69 and the input 4 of 3, is connected to the second input of 73.
  • the output of 73 represents the inverted carry output 9 of the full adder.
  • the shift register stage 37 consists in particular of the series connection of a field effect transistor 75, an inverter 76, a second field effect transistor 77 and a second inverter 78, the output of which is connected to the part of the carry path 7 which transmits the carry signals.
  • the gate of transistor 75 is driven via a line 79, which has a terminal 80 which is occupied by a clock voltage ⁇ M.
  • the gate of 77 is controlled via a line 81, which is provided with a connection 82 which is assigned a clock voltage ⁇ S.
  • the carry signal is then emitted to the carry path 7 via the transistor 77 and the inverter 78, while the transistor 75 blocks.
  • the shift register stages 38, 39 and 63 are constructed in accordance with stage 37, their transistors being driven together with transistors 75 and 77 via lines 79 and 81.
  • the cells of the second to fourth rows are advantageously designed in accordance with FIG. 6.
  • the inputs 4 of cells Z24, Z34 and Z44 are connected with a logic 0.
  • multiplier for four-digit multiplicands and multipliers described so far represents only one exemplary embodiment that serves to explain the invention.
  • the idea of the invention is of course also applicable to cell-structured multipliers that are set up for binary numbers with any number of digits.
  • a NAND gate can expediently be used instead of the AND gate 60 in all cells.
  • the inverted partial product bits are passed on to the cells assigned to them.
  • the carry signals formed in the full adders are then advantageously also output inverted at the outputs 9, the inversion of the received partial product bits and carry signals in the full adders 3 being taken into account accordingly.
  • one or more of the horizontal lines HL1 to HL8 or the shift register stages indicated by them are omitted. This is possible if a clock period corresponds to a multiple of the processing time of a full adder 3.

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Claims (6)

1. Multiplicateur numérique à structure cellulaire, possédant une constitution semi-systolique,
dans lequel tous les bits d'un multiplicande sont combinés selon la combinaison ET respectivement avec un bit d'un mul­tiplicateur pour former un groupe de bits de produits par­tiels et un tel groupe est formé pour chaque bit du multipli­cateur, et
dans lequel des cellules disposées dans une première ligne sont associées individuellement à un premier groupe de bits de produits partiels, qui est constitué par tous les bits de multiplicande, qui sont combinés respectivement selon la com­binaison ET avec le bit de poids le plus faible du multipli­cateur, et
dans lequel des cellules situées dans d'autres lignes succes­sives sont associées à d'autres groupes de bits de produits partiels, les cellules de chaque autre ligne étant associées individuellement aux bits de produits partiels, formés par une combinaison ET de tous les bits de multiplicande avec un seul bit de multiplicateur, et le poids des bits de multipli­cateur respectivement utilisés augmente d'une ligne à la sui­vante; et
dans lequel des premiers conducteurs d'entrée occupés par les bits de multiplicande sont raccordés aux cellules associées à ces bits, et
dans lequel il est prévu des seconds conducteurs d'entrée, occupés par les bits de multiplicateur et dont chacun est raccordé à toutes les cellules qui sont situées dans une ligne et sont associées au bit de multiplicateur envoyé à ces cellules, et
dans lequel il est prévu des voies de transmission de signaux sommes, qui passent par les cellules qui sont associées aux bits de produits partiels de même poids, qui doivent être ad­ditionnés entre eux, et
dans lequel il est prévu des voies de transmission de signaux de report, qui passent par les cellules qui sont associées à des bits de produits partiels devant être additionnés entre eux et possédant un poids croissant, et
dans lequel dans les cellules est prévu respectivement un ad­ditionneur complet, qui sert à additionner un signal somme, envoyé par l'intermédiaire d'une voie de transmission de si­gnaux sommes, éventuellement à un signal de report envoyé par l'intermédiaire d'une voie de transmission et un bit de pro­duit partiel associé à la cellule, et
dans lequel dans les cellules est prévu respectivement un circuit combinatoire, qui sert à réaliser la combinaison ET d'un bit de multiplicande et d'un bit de multiplicateur, et dans lequel les cellules contiennent des étages de registres à décalage, qui sont branchés en aval de la sortie du signal somme et de la sortie du signal de report de l'additionneur complet, et
dans lequel d'autres étages de registres à décalage sont in­sérés dans les premier et second conducteurs d'entrée de telle sorte que tous les conducteurs d'entrée aboutissant aux cellules d'une ligne contiennent respectivement au maximum un nombre d'autres étages de registres à décalage, qui corres­pond au nombre des lignes précédentes, et
dans lequel des signaux numériques pouvant être prélevés sur les extrémités des voies de transmission de signaux sommes et des voies de transmission de signaux de report sont réunis pour former des bits de produits, caractérisé par le fait qu'un circuit combinatoire, qui sert à former un bit de produit partiel, et un additionneur complet dans lequel un signal somme et éventuellement un signal de report sont ajoutés à ce bit de produit partiel, sont disposés respectivement dans deux cellules séparées (Z23, Z33), situées dans des lignes différentes, que la ligne de la cellule (Z33), qui contient l'additionneur complet, est disposée respectivement en aval de la ligne de la cellule (Z23), qui contient le circuit combinatoire, et que la sortie du circuit combinatoire est raccordée par l'intermédiaire d'une ligne de raccordement (58) à l'entrée de l'additionneur complet, dans lequel est inséré un étage de registre à décalage (59), qui sert à mémoriser temporairement le bit de produit partiel formé.
2. Multiplicateur numérique à structure cellulaire suivant la revendication 1, caractérisé par le fait que la cellule (Z23) contenant le circuit combinatoire et la cellule (Z33) contenant l'additionneur complet sont situées directement l'une derrière l'autre dans une même voie (7) de transmission d'un signal de report.
3. Multiplicateur numérique à structure cellulaire suivant la revendication 1 ou 2, caractérisé par le fait que les cellules (Z11 à Z14) situées dans la première ligne contiennent, en-dehors d'un premier circuit combinatoire (64) servant à former les bits de produits partiels associés (Z21 à Z24) de la seconde ligne, respectivement un second circuit combinatoire (63a) servant à former les bits de produits partiels, qui sont associés à ces cellules, et que les sorties des seconds circuits combinatoires (63a) sont reliées aux voies (15, 12, 11, 10) de transmission de signaux sommes.
4. Multiplicateur numérique à structure cellulaire suivant la revendication 3, caractérisé par le fait que des étages de registres à décalage (66) sont prévus respectivement sur les sorties des deux circuits combinatoires (63a) des cellules (Z11 à Z4) situées dans la première ligne.
5. Multiplicateur numérique à structure cellulaire suivant l'une des revendications précédentes, caractérisé par le fait que dans les seconds conducteurs d'entrée (ZL0 à ZL3) sont insérés respectivement des circuits d'attaque (50 à 53), qui sont raccordés, côté sortie, aux autres étages de re­gistres à décalage (42).
6. Multiplicateur numérique à structure cellulaire suivant l'une des revendications précédentes, caractérisé par le fait que les étages de registres à décalage (37, 38, 39, 63) sont constitués respectivement par le circuit série formé d'un premier transistor à effet de champ (75), d'un premier inverseur (76), d'un second transistor à effet de champ (77) et d'un second inverseur (78), les grilles des premier et se­cond transistors à effet de champ (75, 77) de tous les étages de registres à décalage (37, 38, 39, 63) raccordés aux sorties des cellules d'une ligne, pouvant être commandées respective­ment par l'intermédiaire d'une ligne commune (79 ou 81).
EP85110468A 1984-09-17 1985-08-20 Multiplieur numérique sémisystolique à structure cellulaire Expired - Lifetime EP0178424B1 (fr)

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AT85110468T ATE60675T1 (de) 1984-09-17 1985-08-20 Zellenstrukturierter digitaler multiplizierer mit semisystolischem aufbau.

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DE3434085 1984-09-17
DE3434085 1984-09-17

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EP0178424A2 EP0178424A2 (fr) 1986-04-23
EP0178424A3 EP0178424A3 (en) 1988-02-10
EP0178424B1 true EP0178424B1 (fr) 1991-01-30

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US (1) US4748583A (fr)
EP (1) EP0178424B1 (fr)
JP (1) JPH0664530B2 (fr)
AT (1) ATE60675T1 (fr)
AU (1) AU581924B2 (fr)
DE (1) DE3581581D1 (fr)
FI (1) FI88548C (fr)

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US4887233A (en) * 1986-03-31 1989-12-12 American Telephone And Telegraph Company, At&T Bell Laboratories Pipeline arithmetic adder and multiplier
JP2672956B2 (ja) * 1988-01-25 1997-11-05 沖電気工業株式会社 並列乗算器
WO1992000561A1 (fr) * 1990-06-27 1992-01-09 Luminis Pty Ltd. Multiplicateur serie en virgule flottante a anneau systolique a usage general
US5101372A (en) * 1990-09-28 1992-03-31 International Business Machines Corporation Optimum performance standard cell array multiplier
US5283755A (en) * 1993-04-14 1994-02-01 International Business Machines Corporation Multiplier employing carry select or carry look-ahead adders in hierarchical tree configuration
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FI853534A0 (fi) 1985-09-16
JPH0664530B2 (ja) 1994-08-22
US4748583A (en) 1988-05-31
DE3581581D1 (de) 1991-03-07
EP0178424A3 (en) 1988-02-10
AU4748985A (en) 1986-03-27
ATE60675T1 (de) 1991-02-15
FI88548C (fi) 1993-05-25
JPS6174029A (ja) 1986-04-16
FI88548B (fi) 1993-02-15
AU581924B2 (en) 1989-03-09
EP0178424A2 (fr) 1986-04-23
FI853534L (fi) 1986-03-18

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