EP0171322A1 - Elektrisches Gerät oder Schaltkreis-Testmethode und Apparatur - Google Patents

Elektrisches Gerät oder Schaltkreis-Testmethode und Apparatur Download PDF

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Publication number
EP0171322A1
EP0171322A1 EP85401474A EP85401474A EP0171322A1 EP 0171322 A1 EP0171322 A1 EP 0171322A1 EP 85401474 A EP85401474 A EP 85401474A EP 85401474 A EP85401474 A EP 85401474A EP 0171322 A1 EP0171322 A1 EP 0171322A1
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EP
European Patent Office
Prior art keywords
response
measurements
difference
equals
measurement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP85401474A
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English (en)
French (fr)
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EP0171322B1 (de
Inventor
Keibock Lee
Robert Dvorak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Camera and Instrument Corp
Schlumberger Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Camera and Instrument Corp, Schlumberger Technologies Inc filed Critical Fairchild Camera and Instrument Corp
Publication of EP0171322A1 publication Critical patent/EP0171322A1/de
Application granted granted Critical
Publication of EP0171322B1 publication Critical patent/EP0171322B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
    • G01R31/2815—Functional tests, e.g. boundary scans, using the normal I/O contacts

Definitions

  • the present invention relates to a method and apparatus for testing electrical devices, particularly analog electrical devices.
  • a conventional test system 10 utilized to test an analog device 11 is illustrated in Figure 1. Since the device 11 to be tested is typically one component of many components embedded within a printed circuit board (not shown), it is necessary to establish electrical contact with this device within its associated circuit. Thus, such a test system 10 includes one or more pin probes 13 which are electrically connected through a switching and amplifier matrix 14 to an electric test assembly.
  • This electric test assembly has a controller or processor 15; as well as a stimulus section 16 and a measurement section 17, which are controlled by the processor 15.
  • a clock or sequencer 18 is also connected to the processor 15 to afford the timing and sequencing of the stimulus and the measurement sections.
  • the stimulus section 17 of system 10 is capable of generating a stimulus signal (such as a voltage step function) having a known and constant magnitude after some time "T ".
  • This stimulus signal is applied to the device 11 under test through the probes 13.
  • a stimulus voltage could be applied at node 20 in order to cause a current to flow through the device 11.
  • the resulting current flowing through the device 11 and the resulting voltage drop across the device 11 could then be measured at node 21.
  • the impedance of the device 11 under test can be determined from the voltage drop across the device 11 and the current flowing through the device 11. This determined impedance can then be compared to the known impedance of a comparable functioning device, derived either by calculation from the known parameters of the device, or by measuring a comparable device known to be good. This derived value for the impedance of a functioning device can be provided as an input to the processor 15 at terminal 19. If the determined response is substantially equivalent to the derived or known response for a functioning device, the component under test is considered acceptable and functioning properly. If however the determined response differs from the calculated or measured response by more than a predetermined range of tolerance, the device under test is assumed to be defective.
  • Such conventional test systems as described above are not however, able to efficiently test circuits or devices having a response that varies with time, e.g. circuits containing either capacitance or inductance therein.
  • the response to the stimulus signal is neither immediate nor constant. Rather there is a rise time and a settling time associated with such circuits. It is not abnormal in such circuits to have a settling time in the range of from 2 milliseconds to 5 seconds after the stimulus signal has been applied.
  • the conventional testing systems wait for the response to substantially settle to its final value before making a measurement in order for the ultimate comparison to have a significance. This wait time substantially increases the time required to test a device or the printed circuit board containing the time varying device.
  • a general object of the present invention is an inproved method and apparatus for testing an electronic device.
  • a method for testing an analog device comprising a) applying a pre-determined input signal to the device, b) taking a first measurement of the response of the device resulting from the input signal, c) waiting a predetermined time T and taking a second measurement of the response of the device resulting from the input signal, d) waiting the same predetermined time T as in step c) and taking a third measurement of the response of the device resulting from the input signal, e) predicting the final value of the response from the measured values without waiting to actually measure the final value, and f) comparing the predicted final response to a known. response value derived trom a functioning device.
  • Another aspect includes apparatus for testing an analog device comprising a signal generator for stimulating the device with a predetermined electrical signal, means for taking at least three measurements of the response of the device to the stimulus signal, which measurements are separated by a predetermined and equal time delay, circuit means for selectively electrically connecting ana/or disconnecting said measurement means and said signal generator to the device, means for predicting the final value of the response of the device to the stimulus signal from the measured values, and means for comparing tne predicted final response to a response value derived from a functioning device thereby evaluation whether the device under test is functioning or not functioning.
  • FIG. 2 A schematic diagram of a test system 25 according to the present invention is illustrated in Figure 2, wherein the device 11, which is to be tested, i.e. typically one or more individual components within a printed circuit board, is brought into electrical contact with probes 13 and thus with switching matrix 14.
  • probes 13 and switching matrix 14 are of conventional design and need not be further explained to those skilled in the art.
  • the parameters of the device 11 which are necessary to make a decision as to whether the device is functioning or not functioning are also programmed into the system 25. Such parameters would include not only the specific impedance, capacitance, or inductance values, or desired current and voltage levels, etc. for example, but also the acceptable tolerance ranges for the devices.
  • the configuration of the entire circuit board which is to be tested including a description of the devices contained therein and their specific interconnections has been programmed into the system 25 such that the probes 13 can be correctly positioned to contact specific test points, e.g. as nodes 20 and 21 on the printed circuit board, such that the matrix 14 can be switched at the appropriate times to electrically connect the signal generator 16 and the measurement circuit 17 to the appropriate nodes, and such that appropriately shaped stimulus signals are generated.
  • the signal generator 16 and measurement circuit 17 are also considered conventional in design and will not be further described herein.
  • this data is typically stored in a retrievable format such as on magnetic tape or disks which can be loaded into a conventional processor 15 in a conventional manner such as through input terminal 19, to initialize the parameters for the test, whenever that particular board is to be tested.
  • the signal generator 16 Upon instruction by the processor 15, the signal generator 16 provides the appropriate stimulus signal to the probes 13 through the matrix 14. For example, a DC voltage of a predetermined magnitude can be applied at node 20.
  • the processor 15 simultaneously sends a signal to to the timer 18 that the stimulus signal has been applied, and instructs the matrix 14 to electrically connect the measurement circuit 17 to node 20 and 21.via probes 13. Since the switching circuits involved within the matrix 14 can introduce transient into the measurement circuit, the processor 15 typically waits a predetermined time before taking the first measurement, which time is a function of the particular switching circuits utilized. In the preferred emboaiment this time is typically in the order of 1.5 milliseconds. After this initial wait time a first measurement is made at node 21 of the response of device 11 to the input stimulus. Since such measurement circuit 17 typically includes an amplifier, an RMS to DC converter, a DC scaling circuit, and an analog to digital converter, the measurement can be stored in a digital format. In the preferred embodiment this storage is done within standard memory units within the processor
  • the relationship developed to predict the final value as part of the present invention has been empirically as well as theoretically derived and can be proven algebraically. It is based upon the assumptions that the input to the device is a basic first order step function, as well as the assumption that the measurement system has a dominant real pole such that it can be approximated as a first order system. This latter assumption is valid since compensation . capacitors are typically utilized within the measurement circuitry.
  • the resulting derived relationship is as follows: Where X,Y, and Z are samples taken at times T 1 , T 2 and T 3 respectively. This relationship requires three measurements to be taken with an equivalent time delay there between.
  • the optimum time "T" between measurements is a function of the speed at which the response is changing, i.e. insignificant variance in the magnitude of the response signifies a response that has either substantially settied to its final value or a response being sampled too rapidly to measure any variance therein. Although a fast sampling rate is desirable to afford a rapid calculation of the predicted value,
  • T an optimum time "T"
  • a "T” is initially chosen which is known to be small in view of the parameters of the device 11 being tested. Measurements of the response are then made with this between-measurement interval being extended dynamically until the magnitude of the measured response equals approximately 12X of the expected final value, i.e. the derived value.
  • the present invention restarts the timer 18 prior to taking each measurement. This eliminates any variation in the time between measurements due to a variation in the time taken for performing the measurement.
  • all three measurements are made prior to any calculations for predicting the final value. Once taken, the three values are provided as inputs to a conventional arithmetic processor 23 in which the predicted final value is calculated.
  • the final response or voltage is predicted, it is compared to the derived value for such response which has been previously stored in the processor 15. Typically such comparison will have a range of tolerance over which a component will be found acceptable. This tolerance range has be programmed into the processor 15 during the initiation of the parameters as has already been described. Thus the device 11 under test will either be rejected or accepted. This status can be indicated by a message on the screen of a CRT, the generation of a printout, the lighting of indicators, etc.
  • instruction 28 initializes the processor 15 with the testing parameters including the derived valued and the tolerance range for the device 11 under test.
  • Instruction 29 causes the switching matrix 14 to electrically connect the appropriate probes 13 to the signal generator 16, and also causes the signal generator 16 to apply the appropriate stimulus signal to the nodes of the device 11.
  • the application of the stimulus signal activates the timer 18 as is indicated by instruction 30.
  • Instruction 30 also causes the switching matrix to connect the appropriate probes to the measurement circuit 17. Since the accurate control of the elapsed time between measurements is critical, instruction 31 restarts the timer as soon as the programmed time delay has expired.
  • a first measurement of the response of the device to the stimulus signal is then taken as a result of instruction 32. This measurement is identified as measurement "Z" and stored in the processor 15 by instruction 33. If this is the first measurement, instruction 34 will respond with a "no" and instruction 35 will cause the first measurement to also be stored as measurement "Y”.
  • Instruction 38 causes the processor 15 and the arithmetic processor 23 to process the measured values according to a mathematical relationship derived to predict the final value of the responses to the stimulus, i.e. the value which would occur at some time "T f ", which is greater than the settling time. Once this value is calculated it can be compared to the determined value which has been programmed into the processor 15 during step 28. As has already been stated, substantial equivalence (i.e. within the programmed tolerance range) between the predicted value and the determined value will lead to a conclusion that the device under test is functioning properly.
  • instruction 36 is processed.
  • instruction 37 leads into the measurement loop which has already been discussed.
  • Instruction 41 determines the ratio of the difference between the first and second measured values to the difference between the second and third values. (The nomenclature third, second and first is used for convenience to indicate the most recent measurement, the prior measurement and the measurement before the prior measurement, respectively.) This ratio is then stored in the processor 15 as ratio "R”. If only three measurements are in memory this ratio is also stored as ratio "S" and a fourth measurement is made in the conventional manner via instructions 37, 35 and 31 through 33.
  • instruction 41 is again processed and the ratio "R" is calculated and stored utilizing the second, third and fourth measurement.
  • the ratio "S” however now exists due to the initial processing of instructions 41 and 42.
  • instruction 43 is processed.
  • Empirical investigations with the present invention have determined that the test method according to the present invention is more efficient and potentially more accurate when the ratios as calculated by instruction 41 are substantially equal. This premise has also been mathematically confirmed. Similarly greater accuracy is achieved when the ratios are positive and greater than unity.
  • Instruction 44 makes this determination. If either of these conditions is not met, another measurement is made via instruction 42, 37, 35 and 31 through 33, and another ratio is calculated. Such conaitions can be determinea in a conventional manner by the arithmetic processor 23. This process is repeated until the conditions hold true.
  • both of the conditions set forth by instructions 43 and 44 will result in the calculation of the predicted final value via instruction 38 and a determination of the condition of the device via instruction 39 as has already been described.
  • a determination can be made within a fraction of the time required for the response to fully settle.
  • the actual time taken is, however, dependent upon the time constant of circuit being tested. For most circuits the time taken to predict the final value is approximately one half of this time constant.
  • the present invention affords a determination of the condition of the device under test in substantially less time than conventional testing systems which are currently availabie. Furthermore such reduction in test time can be accomplished with minimal reduction in accuracy for most circuits.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Measurement Of Resistance Or Impedance (AREA)
EP85401474A 1984-07-19 1985-07-18 Elektrisches Gerät oder Schaltkreis-Testmethode und Apparatur Expired - Lifetime EP0171322B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/632,460 US4686628A (en) 1984-07-19 1984-07-19 Electric device or circuit testing method and apparatus
US632460 1984-07-19

Publications (2)

Publication Number Publication Date
EP0171322A1 true EP0171322A1 (de) 1986-02-12
EP0171322B1 EP0171322B1 (de) 1991-09-11

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EP85401474A Expired - Lifetime EP0171322B1 (de) 1984-07-19 1985-07-18 Elektrisches Gerät oder Schaltkreis-Testmethode und Apparatur

Country Status (5)

Country Link
US (1) US4686628A (de)
EP (1) EP0171322B1 (de)
JP (1) JPH065261B2 (de)
CA (1) CA1248181A (de)
DE (1) DE3584054D1 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997045748A1 (fr) * 1996-05-29 1997-12-04 Softlink Procede de test de composants electroniques
WO2019243188A1 (de) * 2018-06-18 2019-12-26 ATEip GmbH Verfahren und vorrichtung zum elektrischen prüfen einer elektrischen baugruppe

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0192981B1 (de) * 1985-01-31 1989-12-27 Hewlett-Packard Company Schaltung zur Messung der Kenngrössen einer getesteten Anordnung
US5043910A (en) * 1985-04-19 1991-08-27 Graphtec Kabushikikaisha Printed circuit board function testing system
DE3636427A1 (de) * 1986-10-25 1988-05-05 Standard Elektrik Lorenz Ag Schaltungsanordnung und nachrichtennetzwerk mit pruefeinrichtung und pruefverfahren
US5107969A (en) * 1987-09-17 1992-04-28 Alfred Teves Gmbh Controllable vibration damper
US5307290A (en) * 1988-10-18 1994-04-26 Fiat Auto S.P.A. System for the automatic testing, preferably on a bench, of electronic control systems which are intended to be fitted in vehicles
US5134998A (en) * 1990-04-26 1992-08-04 Minnesota Mining And Manufacturing Company System and method for predicting the value of a compositional parameter of blood
GB2307051B (en) * 1995-11-06 1999-11-03 Marconi Instruments Ltd An equipment for testing electronic circuitry
FR2796157B1 (fr) * 1999-07-05 2002-05-31 Softlink Procede de tests de composants electroniques
FR2812401B1 (fr) * 2000-07-28 2002-10-11 Bealach Bo No Finne Teo Ta Gal Procede de test de composants electroniques tenant compte de la derive de la moyenne
JP2003130919A (ja) * 2001-10-25 2003-05-08 Agilent Technologies Japan Ltd コネクションボックス及びｄｕｔボード評価システム及びその評価方法
US6760680B2 (en) * 2002-10-09 2004-07-06 Nyt Press Services Llc Testing system for printing press circuit board controllers
US7231573B2 (en) * 2002-12-20 2007-06-12 Verigy Pte. Ltd. Delay management system
JP4777794B2 (ja) * 2006-02-14 2011-09-21 日置電機株式会社 測定装置
JP4275696B2 (ja) * 2006-11-09 2009-06-10 三菱電機株式会社 サンプリング周波数制御方式および保護継電器
TWM343792U (en) * 2008-06-10 2008-11-01 Princeton Technology Corp Circuit testing apparatus
TWM343798U (en) * 2008-06-25 2008-11-01 Princeton Technology Corp Circuit testing apparatus
US8527231B2 (en) * 2010-09-15 2013-09-03 Teradyne, Inc. High throughput semiconductor device testing
US8549764B2 (en) 2011-09-23 2013-10-08 Lexmark International, Inc. Fluid tilt sensor within ink tank supply item for micro-fluid applications
TW201412027A (zh) * 2012-09-14 2014-03-16 Chicony Electronics Co Ltd 矩陣測試方法、系統及電壓時脈控制方法
US10340919B2 (en) * 2017-11-29 2019-07-02 Taiwan Semiconductor Manufacturing Company Limited Circuit for monitoring transient time in analog and digital systems

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2007025A1 (de) * 1969-02-17 1970-09-03 International Business Machines Corp., Armonk, N.Y. (V.St.A.) Prüfsystem für logische Schaltungsanordnungen
DE2532801B2 (de) * 1974-07-29 1977-04-14 Time/Data Corp., Palo Alto, Calif. (V.StA.) Anordnung zur bestimmung der uebertragungsfunktion eines pruefobjekts
US4162531A (en) * 1977-01-14 1979-07-24 Hewlett-Packard Company Method and apparatus for programmable and remote numeric control and calibration of electronic instrumentation

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3978325A (en) * 1973-09-05 1976-08-31 Control Electronics Co., Inc. Electronic thermometer
US4176556A (en) * 1977-06-17 1979-12-04 Omron Tateisi Electronics Co. Electronic thermometer
JPS58700A (ja) * 1981-06-26 1983-01-05 Hitachi Ltd 流体輸送システムの制御方式
US4455612A (en) * 1982-01-27 1984-06-19 Iowa State University Research Foundation, Inc. Recursive estimation in digital distance relaying system
US4574359A (en) * 1982-12-21 1986-03-04 Terumo Kabushiki Kaisha Electronic clinical thermometer, and method of measuring body temperature

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2007025A1 (de) * 1969-02-17 1970-09-03 International Business Machines Corp., Armonk, N.Y. (V.St.A.) Prüfsystem für logische Schaltungsanordnungen
DE2532801B2 (de) * 1974-07-29 1977-04-14 Time/Data Corp., Palo Alto, Calif. (V.StA.) Anordnung zur bestimmung der uebertragungsfunktion eines pruefobjekts
US4162531A (en) * 1977-01-14 1979-07-24 Hewlett-Packard Company Method and apparatus for programmable and remote numeric control and calibration of electronic instrumentation

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ELECTRONICS INTERNATIONAL, vol. 57, 19th April 1984, pages 135-139, New York, US; D. JOHNSON "VLSI testers ramp up capabilities for mixed-signal chips and hybrids" *
ELEKTRONIK, vol. 22, no. 4, 1973, pages 117-121, R.W. HARTENSTEIN: "Elemente der Prüftechnik für digitale Schaltungen" *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997045748A1 (fr) * 1996-05-29 1997-12-04 Softlink Procede de test de composants electroniques
FR2749396A1 (fr) * 1996-05-29 1997-12-05 Softlink Outil d'aide pour appareil de test de composants electroniques
US6269326B1 (en) 1996-05-29 2001-07-31 Softlink Method for testing electronic components
WO2019243188A1 (de) * 2018-06-18 2019-12-26 ATEip GmbH Verfahren und vorrichtung zum elektrischen prüfen einer elektrischen baugruppe
US11320477B2 (en) 2018-06-18 2022-05-03 ATEip GmbH Method and device for electrical testing of an electrical assembly for defects

Also Published As

Publication number Publication date
CA1248181A (en) 1989-01-03
JPH065261B2 (ja) 1994-01-19
US4686628A (en) 1987-08-11
DE3584054D1 (de) 1991-10-17
JPS6188170A (ja) 1986-05-06
EP0171322B1 (de) 1991-09-11

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