EP0149788A2 - Anzeigesteuersystem - Google Patents

Anzeigesteuersystem Download PDF

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Publication number
EP0149788A2
EP0149788A2 EP84115208A EP84115208A EP0149788A2 EP 0149788 A2 EP0149788 A2 EP 0149788A2 EP 84115208 A EP84115208 A EP 84115208A EP 84115208 A EP84115208 A EP 84115208A EP 0149788 A2 EP0149788 A2 EP 0149788A2
Authority
EP
European Patent Office
Prior art keywords
coordinate
values
display
memory
coordinates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP84115208A
Other languages
English (en)
French (fr)
Other versions
EP0149788A3 (en
EP0149788B1 (de
Inventor
Takatoshi Ishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ASCII Corp
Original Assignee
ASCII Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP58234334A external-priority patent/JPS60126689A/ja
Priority claimed from JP58243678A external-priority patent/JPS60135988A/ja
Priority claimed from JP58243677A external-priority patent/JPS60135987A/ja
Application filed by ASCII Corp filed Critical ASCII Corp
Publication of EP0149788A2 publication Critical patent/EP0149788A2/de
Publication of EP0149788A3 publication Critical patent/EP0149788A3/en
Application granted granted Critical
Publication of EP0149788B1 publication Critical patent/EP0149788B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/391—Resolution modifying circuits, e.g. variable screen formats

Definitions

  • the present invention relates to a display control system e.g. for use in a computer.
  • Fig. 1 illustrates a block diagram of a conventional color graphics display system.
  • a CPU(microprocessor) 1 for controlling the whole system, and a main memory 2 and a display control circuit 3 are respectively connected to CPU 1.
  • Main memory 2 is used to hold programs and data, and Display Control Circuit 3 is dedicated to control the display of color graphics.
  • Reference 4 designates a VRAM(video memory) for holding CRT display data, and 5 represents a CRT color display unit.
  • Fig. 2 there is shown a block diagram of an example of the display control circuit 3 illustrated in Fig. 1.
  • a timing controller 11 is operated to generate a clock signal which is in turn input to a counter 12 having a column counter, a line counter and a row counter.
  • This counter 12 generates a CRT display synchronizing signal via a display timing circuit 13, while this counter 12 creates a display address which is output via a multiplexer 15 as a VRAM address.
  • the data that is read out from VRAM4 for display access is inputted via a buffer 19 into a video output control circuit 20, where a CRT video signal is created.
  • Fig. 3 illustrates an example of the above-mentioned VRAM 4, the screen configuration of which comprises 640 horizontal dots, 200 vertical dots, and 4-bit (16-color) color information.
  • CPU 1 calculates the physical address of VRAM4 based on the source area coordinates (Sx, Sy) and sets the calculated physical address in VRAM Address Register 14 within Display Control Circuit 3. Also, CPU 1 outputs a read command to read out thn color data within VRAM 4 that corresponds to the coordinates (Sx, Sy).
  • CPU 1 calculates the physical address in VRAM 4 based on the coordinates (Dx, Dy) of the destination area to which the block data is to be transferred, and sets the calculated physical address in VRAM Address Register 14 within Display Control Circuit 3. Also, CPUI writes the color data corresponding to the coordinates (Sx, Sy) into VRAM 4, that is, the locations thereof that correspond to the coordinates (Dx, Dy).
  • the conventional display control system for use in the personal computer is designed such that its hardware is reduced in amount. As a result of this, its software must take heavy loads to make up for the reduction of the hardware amount.
  • CPU1 must perform all of the processing operations and thus it takes a lot of time to transfer such block data in the prior art system.
  • the present invention aims at eliminating the problems seen in the above-mentioned conventional system.
  • FIG. 4 there is illustrated a block diagram of an embodiment of the invention.
  • This embodiment is different from the conventional system shown in Fig. 2 in that an X register 30, a Y register 31 and an address conversion/composition circuit 32 are provided instead of the VRAM address register 14 in Fig. 2, and that a limit check circuit 33 is provided.
  • Limit Check Circuit 33 is a circuit that checks whether the values of the coordinates to be accessed exist or not on a display screen.
  • the illustrated display control circuit 3A otherwise corresponds to the display control circuit 3 in Fig. 2.
  • Address Conversion/Composition Circuit 32 inputs the value set in X Register 30 and the value set in Y Register 31 to convert or compose these values into the physical address of VRAM 4-, and always supplies the thus-converted or composed physical address as an access address to Multiplexer 15.
  • CPU1 can access color information via a data bus by giving a write strobe or a read strobe to CPU Interface Controller 18.
  • X Register 30 and Y Register 31 may each comprise an ordinary register.
  • Address Conversion/Composition Circuit 32 may be realized by use of a simple adder or by means of rearrangement of bits of X Register 30 and Y Register 31. Some examples of the address conversion/composition circuit 32 are shown in Fig. 5.
  • Fig. 5 illustrates the operation of an adder when the adder is employed as the address conversion/composition circuit 32.
  • Fig. 5(a) illustrates how an address created by a value in X Register 30 and a value in Y Register 31 is converted into a physical address for VRAM 4 in case of a screen configuration comprising 640 x 200 dots as shown in Fig. 3.
  • a value contained in the bit array of X Register 30, a value in the bit array of Y Register 31 shifted by 7 bits from X Register 30, and a value in the bit array of Y Register 31 shifted by 2 bits shifted from the above Y Register 31 are added. Addition of these three values permits execution of 640 X Y + X based on the values of X Register 30 and Y Register 31 (that is, these values can be converted into the physical address of VRAM 4).
  • Figs. 5(b) and (c) respectively illustrate cases in which the number of dots in the X axis direction comprises the power value of 2.
  • Y Register 31 needs only be connected as a higher bit of X Register 30.
  • Fig. 5(b) illustrates a case wherein the screen is composed of 512 x 200 dots and thus Y Register 31 need only be connected to the higher position of the 8 bit of X Register to provide for conversion into the physical address.
  • Fig. 5(c) shows a case in which the screen has a configuration of 256 x 200 dots and thus the bit array of Y Register 31 need only be connected to the higher position of the lower 7 bit of X Register 30 to provide for conversion into the physical address.
  • the information that occurs first is values on the X, Y coordinates. Therefore, if it is possible to specify such values on the X, Y coordinates as they are, to hardware, then CPU1 can save all of processings necessary to calculate the physical address.
  • the first occurring information is positions on the screen.
  • the positions on the screen are expressed as values on the X, Y coordinates.
  • Fig. 6 illustrates a block diagram of an example of Limit Check Circuit 33
  • Fig. 7 illustrates comparison circuits included in this limit check circuit 33.
  • Comparison Circuits 40 and 41 may be connected to a data bus by means of a gate circuit 42 such that their output conditions can be written in the form of a status indication, so that it is possible to know which of the coordinate values is in excess of the maximum value.
  • Fig. 7(a) illustrates an example of a comparison circuit for checking whether the value of X Register 30 is in excess of 640 or not.
  • NL (NOT LESS) signal is output from Comparison Cincult 40.
  • This NL signal and a value in the bits 15 - 10 of X Register 30 is ORed to create an X Limit Out signal having the meaning that the associated value has exceeded the maximum value on the X coordinate.
  • the value on the X coordinate is stored in terms of 2 bytes (16.bits) of software.
  • the respective values of the X coordinate should have been determined in accordance with the respective demand items of the system previously occurred, and if the value is other than "0 - Max. value", then its position on the coordinates exists outside the screen and thus any access to it must be prohibited. Since the value of the coordinates is operated in terms of a binary number sufficiently greater than its maximum value, when it is out of position in either of a positive or negative direction, it becomes a value other than "0 - Max. value".
  • the bit 15 is interpreted as a sign.
  • Fig. 7(b) illustrates an example of a comparison circuit for checking whether a value on the Y coordinate is in excess of 200 or not. If the value is more than 200, then a Y Limit Out signal is output.
  • Fig. 7(c) illustrates a check circuit for checking whether a value on the X coordinate is in excess of 512 or not. If its screen is structured such that its limit value is composed of a power value of 2 in this manner, then Check Circuit 33 can be realized very simply.
  • Fig. 8 illustrates a block diagram of another embodiment of the invention.
  • This embodiment is substantially similar to the prior embodiment in Fig. 4, but a display control circuit 3B in Fig. 8 is different from the display control circuit 3A in Fig. 4 in that an X counter 30c is employed in place of the X register 30.
  • the discussion made in connection with the embodiment in Fig. 4 may also apply to the embodiment in Fig. 8, with X Register 30 being replaced by X Counter 30c.
  • Fig. 9 illustrates the operation of an adder when the adder is used as Adress Conversion/Composition Circuit 32. Similarly, the description given in connection with Fig. 5 can also apply to Fig. 9, only with X Register 30 replaced by X Counter 30c.
  • Fig. 10 illustrates X Counter 30c
  • Fig. 11 illustrates a decoder circuit for distributing the respective read/write signals from CPU1 to registers.
  • X Counter 30c is used as means to set up a value on the X coordinate, and as a load signal to X Counter 30c an indication signal is used which is employed by CPU 1 to set up the value on the X coordinate.
  • a count-up signal a signal in used which indicates that CPU 1 has accessed VRAM 4.
  • Decoder 18d is included within CPU Interface Controller 18 and is operated when CPU1 reads/writes data between the respective registers.
  • X Counter 30c may be counted up by use of the trailing edge of the count signal.
  • Y Register 31 may also be composed of a counter.
  • its count-up signal may be supplied from CPU 1 or it may occur automatically within Display Control Circuit 3.
  • This automatic occurrence may include such an operation as to count up by 1 a value on the Y coordinate when X Counter 30c counts N times.
  • Such automatic operation can improve the performance of the system.
  • it may be possible not only to count up the value on the Y coordinate but also to specify its count-down.
  • Fig. 12 illustrates a block diagram of another embodiment of the invention.
  • This embodiment is different from the above-mentioned embodiment in Fig. 8 in that it is further provided with a mode register 34.
  • the thus-modified display control circuit is designated by 3C in this Figure.
  • CPU 1 sets up a value to specify a screen configuration to Mode Register 34. Based on this value, Column Counter/ Line Counter/Row Counter 12 performs its counting operation and at the same time outputs a signal and a display address to Display Timing Circuit 13.
  • Fig. 3 the value of the X coordinate ranges up to 639 and thus it can display 640 dots, while this horizontal display dot number can be changed.
  • the change of the number is referred to as change of the screen configuration.
  • Address Conversion/Composition Circuit 32 is composed of two selectors 321, 322 and an adder 323 as shown in Fig. 13.
  • Selector 1(321) shown in Fig. 13 has shifted the values of Y Register by one bit for M0,M1, thereby realizing the conditions of S1.
  • Selector 2 (322) selects 0 for M1,M2 and thus realizes the conditions of S2.
  • the circuit shown in Fig. 10 may be used to compose the bits (that is, re-arrange them) only, which eliminates the need for Adder 323.
  • a mode register 34 used to perform such mode specification and a circuit 18d responsive to the mode register 34 to generate count signals.
  • a mode register 34 used to perform such mode specification and a circuit 18d responsive to the mode register 34 to generate count signals.
  • an X counter that corresponds to the operation of software
  • timing of the display control circuits 3A, 3B, and 3C and the setting of the registers are to be performed by Timing Controller 11 and CPU Interface Controller 18.
  • the invention is able to cope with a configuration employing 16 bits for 1 memory address by specifying the modification portions of a word by means of the lower bits of X Counter 30c and using the higher bits of X Counter 30c as address values.
  • the invention is advantageous in that it is able to speed up its display memory access and that, in doing so, the amount of the hardware added is comparatively small.
  • the present invention eliminates the need to set up values on the X coordinate every time, when the X, Y coordinate system is employed.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
EP19840115208 1983-12-14 1984-12-12 Anzeigesteuersystem Expired - Lifetime EP0149788B1 (de)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP58234334A JPS60126689A (ja) 1983-12-14 1983-12-14 表示制御装置
JP234334/83 1983-12-14
JP58243678A JPS60135988A (ja) 1983-12-26 1983-12-26 表示制御装置
JP243678/83 1983-12-26
JP58243677A JPS60135987A (ja) 1983-12-26 1983-12-26 表示制御装置
JP243677/83 1983-12-26

Publications (3)

Publication Number Publication Date
EP0149788A2 true EP0149788A2 (de) 1985-07-31
EP0149788A3 EP0149788A3 (en) 1987-08-26
EP0149788B1 EP0149788B1 (de) 1992-04-15

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP19840115208 Expired - Lifetime EP0149788B1 (de) 1983-12-14 1984-12-12 Anzeigesteuersystem

Country Status (3)

Country Link
EP (1) EP0149788B1 (de)
CA (1) CA1232381A (de)
DE (1) DE3485661D1 (de)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0274439A2 (de) * 1987-01-07 1988-07-13 Brother Kogyo Kabushiki Kaisha Bildanzeigesystem für mehrere Bildbereiche auf einem Schirm
GB2210239A (en) * 1987-09-19 1989-06-01 Hudson Soft Co Ltd An apparatus for controlling the access of a video memory
EP0444812A1 (de) * 1990-02-21 1991-09-04 Crosfield Electronics Limited Verfahren und Einrichtung zur Anzeige von Bildern
GB2246935A (en) * 1987-09-19 1992-02-12 Hudson Soft Co Ltd An apparatus for the control of an access to a video memory

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ELECTRONICS, vol. 45, no. 12, 5th June 1972, pages 111-116, New York, US; L.R. LOVERCHECK: "Raster scan technique provides multicolor graphic displays" *
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 23, no. 6, November 1980, pages 2342,2343, IBM, New York, US; D.R. MERSEL: "Highlighting image data on pel for pel adressable displays" *

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0274439A2 (de) * 1987-01-07 1988-07-13 Brother Kogyo Kabushiki Kaisha Bildanzeigesystem für mehrere Bildbereiche auf einem Schirm
EP0274439A3 (en) * 1987-01-07 1989-07-19 Brother Kogyo Kabushiki Kaisha Display system for plural display areas on one screen
US4903013A (en) * 1987-01-07 1990-02-20 Brother Kogyo Kabushiki Kaisha Display system for plural display areas on one screen
GB2210239A (en) * 1987-09-19 1989-06-01 Hudson Soft Co Ltd An apparatus for controlling the access of a video memory
GB2246935A (en) * 1987-09-19 1992-02-12 Hudson Soft Co Ltd An apparatus for the control of an access to a video memory
GB2246935B (en) * 1987-09-19 1992-05-20 Hudson Soft Co Ltd An apparatus for the control of an access to a video memory
GB2210239B (en) * 1987-09-19 1992-06-17 Hudson Soft Co Ltd An apparatus for controlling the access of a video memory
EP0444812A1 (de) * 1990-02-21 1991-09-04 Crosfield Electronics Limited Verfahren und Einrichtung zur Anzeige von Bildern
US5373311A (en) * 1990-02-21 1994-12-13 Crosfield Electronics Limited Image display apparatus and method

Also Published As

Publication number Publication date
DE3485661D1 (de) 1992-05-21
EP0149788A3 (en) 1987-08-26
EP0149788B1 (de) 1992-04-15
CA1232381A (en) 1988-02-02

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