CA1232381A - Display control system - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

An improved display control system is disclosed which is capable of reducing the time necessary for executing its display operation. In this display control system, when a display memory is to be accessed, its software supplies values on the X, Y coordinates in a display screen and these values are then converted into the physical addresses of the memory. For this purpose, a limit check function is provided. Also, an X
register for setting up values on the X coordinate in a display unit is formed of a counter, thereby eliminating the need for setting the values on the X coordinate each time. The display control system is also capable of dealing with the change of a plurality of screen configurations in the above-mentioned X, Y
coordinate system.

Description

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The present invention relates to a display control system for use in a computer.
The background of the invention and the invention itself will now be described in greater detail with reference to the accompanying drawings, in which:
Figure 1 is a block diagram of a typical conven-tional color display system;
Figure 2 is a block diagram of a display control circuit employed in Figure l;
Figure 3 is a block diagram of a VRAM in Figure 1, illustrating the transfer operation of a block data;
Figure ~ is a block diagram of an embodiment of the invention;
Figures 5(a)-(c), are views to explain the operation of an address conversion/composi-tion circuit employed in the above-mentioned embodiment of the invention;
Figure 6 is a block diagram of a limit check circuit in the above embodimen-t;
Figures 7(a)-(c), are views to illustrate an example of a comparison circuit contained the above-mentioned limit check circuit;
Figure 8 is a block diagram of another embodiment of the invention;
Figures 9(a) (c), are views to illustrate the operation of an address conversion/composition circuit employed in the embodiment in Figure 8;

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Flgure lO is a view to illus-trate an X counter employed in the above-mentioned embodiments of the invention;
Eigure 11 is a schematic view of a decoder circuit for distributing the respec-tive read/write signals from CPU to registers;
Figure 12 is a block diagram of still another embodimen-t of the invention;
Eigures 13 and 14 are schematic views respectively showing an address conversion/composition circuit that corres-ponds to a plurality of screen resolutions or configurationsand, Figure 15 is a view to illustrate a mode register and a count signal generation circuit.
Figure l illustrates a block diagram of a conventional color graphics display system. In -this figure, there is provided a CPU (microprocessor) 1 for controlling the whole system, and a main memory 2 and a display control circuit 3 are respectively connected to CPU 1. Main memory 2 is used to hold programs and data, and Display Control Circuit 3 is dedicated to control the display of color graphics. Reference 4 designates a VRAM (video memory) for holding CRT display data, and 5 represents a CRT
color display unit.
In Figure 2, there is shown a block diagram of an example of the display control circuit 3 illustra-ted in Figure 1.
A timing con-troller ll is operated to generate a clock signal which is in turn input to a counter 12 having a column counter, 3'~

a line countex and a row coun-ter. This counter 12 generates a CRT display synchronizing signal via a display -timing circuit 13, while this counter 12 creates a display address which is output via a multiplexer 15 as a VRAM address.
The data that is read out from VRA~l 4 Eor display access is inputted via a buffer 19 into a video output control circuit 20, where a CRT video signal is created.
On the other hand, in the case when CPU 1 tries to access VRAM 4, if an address of VRAM 4 is set in a VRAM address register 14 and a write strobe is input to a CPU interface controller 18, then the output of VRAM Address Register 14 due to CPU 1 is selected by the multiplexer 15 as the VRAM address, and the write data from CPU 1 is writ-ten via bufEers 16, 17 into VRAM 4.
Figure 3 illus-tra-tes an example of the above-mentioned VRAM 4, the screen configuration of which comprises 640 horizontal dots, 200 vertical do-ts, and 4-bit (16 color) color information.
Let us -take a conventional example of operation where the block data of a source area within VRAM 4 is transferred to a destination area based on the X, Y coordinates as shown in Figure 3.
CPU 1 calculates -the physical address of VRAM 4 based on the source area coordinates (Sx, Sy) and sets the calculated physical address in VRA~l Address Register 14 within Display Control Circui-t 3. Also, CPU l ou-tputs a read command to read out the color data within VRAM 4 that corresponds -to the coordinates (Sx, Sy).
Next, CPU 1 calculates the physical address in VRAM 4 based on the coordinates(Dx, Dy) of the destination area to which the block data is to be transferred, and sets the calculated physical address in VRAM Address Register 14 within Display Control Circuit 3. Also, CPU 1 writes the color data correspond-ing to the coordinates (Sx, Sy) into VRA~I 4, that is, the locations -thereof that correspond to the coordinates (Dx, Dy).
Then, it is necessary to repeat the above-mentioned read/write operations NX times regarding the horizontal direction and NY times regarding the vertical direction, or a total of (NX x NY) times before the block data of the source area can be transferred to the destination area.
In order to satisfy the needs of small size and low cost of a personal computer, the conventional display control system for use in the personal computer is designed such that the amount o~ its hardware is reduced. As a result, its software must take over an increased load to make up for the reduction of the hardware.
As can be seen from the example of the transfer of the block data mentioned above, CPU 1 mus-t perform all of the processing operations and thus it takes a lot oE time to transfer such block data in the prior art system.

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Also, in the above-mentioned eonventional system, normally, CPU 1 and Display Control Circuit 3 are operating independently of each other and the display timing of Display Control Circuit 3 has priority over the VRAM access timing of CPU 1. As a result of thisl a wait time arises when CPU 1 accesses VRAM 4, which greatly decreases the efficiency of the data transfer.
In other words, in the above-mentioned prior art system, since the software must take over control of a greater number of processes in the display control, there is a problem that it takes a very long time to execute its operations. Also, as the computer is graded up with its display specifications increased, the time necessary for its operation execution becomes outstandingly longer.
On the other hand, in the above-mentioned prior art system, when the software is used to calculate the physical address of VRP~l 4, if the va:Lues of the physical address on the X, Y coordinates are not contained in the display sereen, then a proper conversion into the physical address is not per-formed.
Therefore, it is necessary to carry out a check (which is referred to as a limit check) whether the values on the X, Y coordinates exist within the limit of -the disp]ay screen, before -the physical address is calcula-ted. This limit check increases the load of -the sof-tware considerably, and, in this sense, the time required for execu-tion of -the operation is also increased. In particular, when drawing a circle, such a limit check must be performed quite ~L~3~3~

frequently so that the operation execu-tion time becomes longer.
The present invention aims at eliminating the problems seen in the above-mentioned conventional system.
Accordingly, it is an object of the invention to provide an improved display control system for a eomputer which can reduce the execution time of its display operations.
In accomplishing the above object, according to the invention, when accessing a display memory, software gives the values on the X, Y coordinates on a display screen and these values are converted to the physical address of the memory.
There are also provided a limit check function and means for operating on the values on the X, Y coordinates step-by-step for each access to the display memory.
The invention will now be described in greater detall with reference -to Figures 4 - 15 of the accompanying drawings.
In Figure 4, there is illustrated a block diagram of an embodiment of the invention. This embodiment is different from the conventional system shown in Figure 2 in that an X
register 30, a Y register 31 and an address conversion/composition circuit 32 are provided instead of -the VRA~l address register 14 in Figure 2~ and that a limit check circuit 33 is provided.
Limit Check Circuit 33 is a circuit that checks whether the values on the coordinates to be accessed exist or not on a display screen.
The illustrated display control circuit 3A is one -that corresponds to the display control circuit 3 in Figure 2.
When CPU 1 -tries to access VRAM 4, a value on the X

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coordinate corresponding to its screen position on the VRAM 4 is set in X Register 30 and an associated value on the Y co-ordinate is set in Y Register.
Address Conversion/Composition Circuit 32 inputs the value se-t in X Regis-ter 30 and the value set in Y Register 31 to convert or compose these values into the physical address of VRAM 4, and al~ays supplies the thus-converted or composed physical address as an access address to Multiplexer 15.
Accordingly, after setting of the values on the X, Y
coordinates, CPU 1 can access color information via a data bus by giving a write strobe or a read strobe to CPU Interface Controller 18.
X Register 30 and Y Register 31 may each comprise an ordinary register.
Address Conversion/Composition Circuit 32 may be realized by use of a simple adder or by means of a rearrangement of bits of X Register 30 and Y Register 31. Some examples of the address conversion/composi-tion circuit 32 are shown in Figure 5.
Figure 5 illustrates the operation of an adder when the adder is employed as the address conversion/composition circuit 32.
First, Figure 5(a) illustra-tes how an address created by a value in X Register 30 and a value in Y Register 31 is converted into a physical address for VRAM 4 in case of a screen configuration comprising 640 x 200 dots as shown in Figure 3.
In other words, a value contained in the bit array of X Register 30, a value in the bit array of Y Register 31 shifted by 7 bits ;3~L.

from X Register 30, and a value in the bit array of Y Register 31 shifted by 2 bits shifted from the above Y Register 31 are added. Addition of these three values permits execution of 640 x Y -~ X based on the values of X Register 30 and Y Register 31 (that is, these values can be converted into the physical address of VRAM 4).
Next, Figures 5~b) and (c) respectively illustrate cases in which the number of dots in the X axis direction comprises the power value of 2. In these cases, in order to convert the address created by the value of X Register 30 and the value of Y Register 31 to the physical address of VRAM 4, Y
Register 31 needs only be connected as a higher bit of X Register 30.
That is, Figure 5(b) illustrates a case wherein the screen is composed of 512 x 200 dots and thus Y Register 31 needs only be connected to the higher position of -the 8 bit of X Register to provide for conversion into the physical address.
Also, Figure 5(c) shows a case in which the screen has a configuration of 256 x 200 dots and thus the bit array of Y
Register 31 needs only be connected to the higher position of the lower 7 bit of X Register 30 to provide for conversion into the physical address.
When the transfer of the block data shown in Figure 3 is executed, the information that occurs first is values on the X, Y coordinates. Therefore, if it is possible to specify such values on the X, Y coordinates, as they are, to hardware, then 3~3~

CPU 1 can save all of processings necessary to calcula-te the physical address.
In other cases than that shown in Figure 3 as well, if the system which is using -the display screen has a higher level language as its original language, then when the screen is accessed, -the first occurring information, most of all, is positions on the screen. In particular, the positions on the screen are expressed as values on the X, Y coordinates.
Therefore, even in an ordinary case, it is possible to lighten the load of its software to a great extent, if it happens to be a case in which these X, Y coordinates can be used to provide access to a display memory.
Now, Figure 6 illustrates a block diagram of an example of Limit Check Circuit 33, and Figure 7 illustrates comparison circuits included in this limit chec]s circui-t 33.
When CPU 1 is going to access VRAM 4, if coordinate values are set in X Regis-ter 30 and Y Register 31 respectively, then Limit Check Circuit 33, together with Address Conversion/
Composition Circuit 32, is operated. That is, Comparison Circuits 40 and 41 are operated to ckeck whether the respective values on -the X, Y coordinates are in excess of maximum values or not. If either of them exceeds the maximum value, then an interrupt signal is generated. In this way, by interrupting CPU 1, it is possible to inform to the effect that the coordinates to be accessed do not exist in the associated display screen.
Also, Comparison Circuits 40 and 41 may be connected 3f~

to a data bus by means of a gate circuit 42 such that their output conditions can be written in the form of status, so that it is possible to know which of the coordinate values is in excess of the maximum value.
Even in case when CPU 1 is operated in a condition in which it cannot or does not initiate an interrupt, if, after setting of the X, Y coordinates, such status is examined by all means, then it is possible to judge which of the comparison circuits 40, 41 exceeds the maximum value.
Figure 7(a) illustrates an example of a compaxison circuit for checking whether the value of X Register 30 is in excess of 640 or not.
When the bits 9 - 7 of X Register 30 are equal to or more than "101, NL (NOT LESS) signal is output from Comparison Circuit 40. This NL signal and a value in the bits 15 - 10 of X Register 30 is ORed to create an X Limit Out signal having the meaning -that the associated value has exceeded the maximum value on the X coordinate.
The value on the X coordinate is stored in terms of 2 bytes (16 bits) on software. The respective values on the X
coordinate should have been determined in accordance with the respective demand items of the system previously occurred, and if the value is o-ther than "O - Max. value", then its position on the coordinates exists outside the screen and thus any access to it must be prohibited. Since the value on -the coordinate is operated in terms of a binary number sufficiently greater than ~c~3~

its maximum value, when it is out of position in either of a positive or negative direction, it becomes a value other than "O - Max. value". Here, the bi-t 15 is interrupted as a sign.
Figure 7(b) illustrates an example of a comparison circuit for checking whether a value on the Y coordinate is in excess of 200 or not. If the value is more than 200, then a Y
Limit Out signal is output.
Figure 7(c) illustrates a check circuit for checking whether a value on the X coordinate is in excess of 512 or not.
I~ its screen is structured such that its limit value is composed of a power value of 2 in this manner, then Check Circuit 33 can be reali~ed very simply.
Figure 3 illustrates a block diagram of another embodiment of the invention. This embodiment is substantially similar to the prior embodiment in Figure 4, but a display control circuit 3B in Figure 8 is different from the display control circult 3A in Figure 4 in that an X counter 30c is employed in place of the X register 30. The discussion made in connection with the embodiment in Figure 4 may also apply to the embodiment in Figure 8, with X Register 30 being replaced by X
Counter 30c.
Figure 9 illustrates the operation of an adder when the adder is used as Address Conversion/Composition Circui-t 32.
Similarly, the description given in connection with Figure 5 can also apply to Figure 9, only with X Register 30 replaced by X
Counter 30c.

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E'igure 10 illustrates X Counter 30c, and Figure 11 illustrat:es a decoder eircuit for distributing the respeetive read/write signals from CPU 1 to registers.
X Counter 30c is used as means to set up a value on the X coordinate, and as a load signal to X Counter 30c an indication signal is used which is employed by CPU 1 to set up the value on the X coordinate. As a count-up signal, a signal is used which indicates that CPU 1 has accessed VRAM 4.
Each of the signals is outputted from Decoder 18d.
Decoder 18d is included within CPU Interface Controller 18 and is operated when CPU 1 reads/writes data between the respective registers.
X Counter 30c may be counted up by use of the -trailing edge of the count signal.
Y Register 31 may also be composed oE a counter. In this case, its eount-up signal may be supplied from CPU 1 or it may occur automatically within Display Control Circuit 3. This automatie occurrence may include such an operation as to count up by 1 a value on the Y coordinate when X Counter 30c counts N
times. Thus, such automatic operation can improve the performance of the system. Alternatively, it may be possible not only to count-up the value on the Y coordinate but also to speeify its eount-down.
Figure 12 illustrates a bloek diagram of another embodiment of the invention.
This embodiment is different from the above-men-tioned :~3~3~3~

embodiment in Figure 8 in that it is further provided with a mode register 3~. The-thus modified display control circuit is designated by 3C in this figure.
At an initialization time or the like, prior to access to VRAM 4, CPU 1 sets up a value to specify a screen configuration to Mode Register 34. Based on this value, Column Counter/Line Counter/Row Counter 12 performs its counting operation and at the same time outputs a signal and a display address to ~isplay Timing Circuit 13.
In Figure 3 the value on the X coordinate ranges up to 639 and thus it can display 640 dots, while this horizontal display dot number can be changed. The change of the number is referred to as change of the screen configuration.
Further, since it is also necessary to change the contents of Address Conversion/Composition Circuit 32 correspond-ingly to the change of the respective screen configurations, the contents of Mode Register 34 are inputted to Address Conversion/
Composition Circuit 32 as well. Address Conversion/Composition Circuit 32 is composed of two selectors 321, 322 and an adder 323 as shown in Figure 13.
In this embodiment, three kinds of screen configurations (or MO, Ml, M2) are employed and, therefore, the following correspondences are necessary:
For MO, 640 x Y + X
For Ml, 512 x Y + X
For M2, 256 x Y + X

These equations can be generalized by the following equations:
X + Y x 256 x Sl + 128 x S2 where, Sl is 1 for M2 and 2 for M1, MO, while S2 is 1 for MO and O for Ml and M2.
Selector 1(321) shown in Figure 13 has shifted the values of Y Register by one bit for MO, Ml, thereby realizing the conditions of Sl. Selector 2(322) selec-ts O for Ml, M2 and thus realizes the conditions of S2.
When the number of horizontal dots in the screen configuration is the power number of 2 only, for example, when it is only Ml, M2, -the circuit shown in Figure 10 may be used to compose the bits (that is, re~arrange them) only, which eliminates -the need for Adder 323.
Next, we will describe -the specifica-tion function of such an X counter as shown in Figure 15 for specifying coun-t modes in addition -to the specification of the screen configuration.
In Eigure 15, there are provided a mode register 34 used to perform such mode specification and a circuit 18s reponsive to the mode register 34 to generate count signals.
When we -take account of the opera-tion of an X counter that corresponds -to the opera-tion of software, in case of a read/
modlfy/write operation, it may be convenient -to count up only for the wri-te operations. However, when a continuous reading or a continuous writing is carried out, i-t is convenient -to count up for no-t only -the write operations bu-t also -the read operations.

Also, it would be more convenient to be able to specify a count-down operation according to the direction of processings on the screen, which can improve the performance of a display control system.
Recently, with progress in the semi-conduc-tor technology, even a relatively complicated circuit has been made in -the form of an LSI, a gate array or the like which can reduce its effect to the cost of the finished product. Thus, situations permitting addition of hardware have been under arrangement.
In the above-mentioned description, various controlling operations not directly concerned with the present invention can be realized by the techniques well known in the art. For example, the timing of the display control circuits 3A, 3B, and 3C and the setting of the registers are to be performed by Timing Controller 11 and CPU Interface Controller 18.
Also, in the above-mentioned embodiment, although the principles of the invention have been described by way of the memory so constructed as to have 4 bits for 1 memory address (= 1 dot, each display color information is composed of 16 colors), as shown in Figure 3, it should be understood that they are not limited to the illustrated example but other embodiments can also be included within the scope of the invention. For example, the invention is adaptable to a configuration that employs 8 bits for 1 memory address (= 2 dots, each display color information of 16 colors, or, 4 dots, each display color inEormation of 4 colors) in accordance with the construc-tion of a memory element, the access time of the memory, the adjustability relative to CPU 1 and the like. Further, the invention is capable to cope with a configuration employing 16 bi-ts for 1 memory address by specifying the modification portions of a word by means of the lower bits of X Counter 30c and using the higher bits of X Counter 30c as address values.
As can be seen from the foregoing description, according to the invention, most of the operations of the sof-tware relating to the display operations can be processed by the hardware.
Accordingly, the invention is advantageous in that it is able to speed up its display memory access and that, in doing so, the amount of the hardware added is comparatively small.
Also, the present invention eliminates the need -to set up values on the X coordinate every time, when the ~, Y
coordinate system is employed.

Claims (7)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A display control system comprising:
means for setting up values on the X coordinate in a display unit;
means for setting up values on the Y coordinate in said display unit; and means for converting/composing said set-up values on said X, Y coordinates into the physical addresses of a display memory, characterized in that a memory access for reading/modifying/
writing the content of said display memory is specified on said X, Y coordinates.

2. A display control system comprising:
means for setting up values on the X coordinate in a display unit;
means for setting up values on the Y coordinate in said display unit;
means for converting/composing said set-up values on said X, Y coordinates into the physical addresses of a display memory;
X coordinate comparison means for comparing said values on said X coordinate with a maximum value on said X coordinate that is determined according to the screen configuration of said display unit;
Y coordinate comparison means for comparing said values on said Y coordinate with a maximum value on said Y coordinate that is determined according to the screen configuration of said display unit; and means for informing CPU of the results compared by said X and Y coordinate comparison means, characterized in that memory accesses for reading/modifying/
writing the contents of said display memory are specified on said X, Y coordinates respectively, and that said CPU is informed of the fact that the X, Y coordinates to be accessed are present outside the limit of said screen.

3. The display control system as claimed in Claim 2, characterized in that said informing means is constructed such that said CPU is able to read the outputs of said X, Y coordinate comparison means as status.

4. The display control system as claimed in Claim 2, characterized in that said informing means is adapted to interrupt said CPU when it judges that at least one of said X, Y coordinate comparison means is greater than said maximum value.

5. A display control system comprising:
means for setting up values on -the X coordinate in a display unit;
means for setting up values on the Y coordinate in said display unit;
means for converting/composing said set-up values on said X, Y coordinates into the physical addresses of a display memory; and step-by-step means for advancing said values on said Y
coordinate step by-step for each access to said display memory, characterized in that memory accesses for reading/modifying/
writing the contents of said display memory are specified on said X, Y coordinates, and that in case of accesses in the X
coordinate direction the need for resetting said values on said X coordinate is eliminated.

6. A display control system comprising:
means for setting up values on the X coordinate in a display unit;
means for setting up values on the Y coordinate in said display unit;
means for converting/composing said set-up values on said X, Y coordinates in-to the physical addresses of a display memory;
means for setting up a plurality of screen configurations and specifying one of said screen configurations; and, means for changing the contents of said conversion/
composition in accordance with said specified screen configuration, characterized in that memory accesses for reading/modifying/
writing the contents of said display memory are specified on said X, Y coordinates, and that a plurality of screen configurations are available.

7. A display control system comprising:
means for setting up values on the X coordinate in a display unit;
means for setting up values on the Y coordinate in said display unit;
means for converting/composing said set-up values on said X, Y coordinates into the physical addresses of a display memory;
step-by-step means for advancing said values on said X
coordinate for each access to said display memory;
means for specifying count modes; and, means responsive to said memory access based on said specification for generating a pulse signal for count-up or count-down, characterized in that memory accesses for reading/modifying/
writing the contents of said display memory are specified on said X, Y coordinates, and that various count modes can be realized correspondingly to said memory accesses.