EP0126784A1 - Mémoire semi-conductrice - Google Patents

Mémoire semi-conductrice Download PDF

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Publication number
EP0126784A1
EP0126784A1 EP83105171A EP83105171A EP0126784A1 EP 0126784 A1 EP0126784 A1 EP 0126784A1 EP 83105171 A EP83105171 A EP 83105171A EP 83105171 A EP83105171 A EP 83105171A EP 0126784 A1 EP0126784 A1 EP 0126784A1
Authority
EP
European Patent Office
Prior art keywords
word
lines
line
switches
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP83105171A
Other languages
German (de)
English (en)
Other versions
EP0126784B1 (fr
Inventor
Siegfried Dr. Dipl.-Ing. Wiedmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
IBM Deutschland GmbH
International Business Machines Corp
Original Assignee
IBM Deutschland GmbH
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by IBM Deutschland GmbH, International Business Machines Corp filed Critical IBM Deutschland GmbH
Priority to DE8383105171T priority Critical patent/DE3380678D1/de
Priority to EP83105171A priority patent/EP0126784B1/fr
Priority to JP59049454A priority patent/JPS59217290A/ja
Priority to CA000452131A priority patent/CA1211212A/fr
Priority to US06/602,866 priority patent/US4596000A/en
Publication of EP0126784A1 publication Critical patent/EP0126784A1/fr
Application granted granted Critical
Publication of EP0126784B1 publication Critical patent/EP0126784B1/fr
Expired legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device

Definitions

  • the invention relates to a semiconductor memory according to the preamble of patent claim 1.
  • DE-OS 28 55 866 describes a discharge method for such memories in order to enable the discharge of capacitive currents on certain lines, so that faster writing or reading is possible.
  • MTL memory cells are for example in the. DE-PS 2 612 666.
  • bipolar and FET memories it is common for both bipolar and FET memories to divide the row or word lines into two parts.
  • a memory is described for example in DE-OS 25 48 564.
  • This memory is characterized in that the row lines, respectively right and left row line portions, in that one of the number of row lines is corresponding number of sense amplifiers in a column arranged such that each of the amplifiers rush line section a right Z connects with a left row line portion, that the memory cells each have a field effect transistor, the gate of which is connected to one of the column lines and the source or drain connection of which is connected to one of the row lines, and have a capacitive storage element, in addition to which a plurality of auxiliary cells are provided, one of which is connected to one of the right or left row line sections, and that an input / output bus line is disposed at and connected to one end of the row lines, the bus line being connected to some of the memory cells can be coupled for the sense amplifier.
  • the effective word line capacity is halved. Nevertheless, this word line capacity is still too high, in particular for memories with a very large number of memory cells per word line, so that such a proposal is not suitable for highly integrated memories with a very high information storage capacity. Because the word lines can only be selected after discharging, there is a loss of speed, and there are also very large capacitive currents which cause increased power loss and interference problems within the matrix.
  • a data memory with a large number of storage locations, an address register and a decoding device for addressing a storage location for reading out stored information or for writing information is known, which is characterized in that the decoding device has a main decoder which is connected to the address register via address signal lines and has a group of decoders downstream of the main decoder, all in parallel to other addresses Signal lines of the address register are connected, and that each of the downstream decoders is assigned a switching device for selectively turning on the decoder in question to the operating voltage and each of the output lines of the main decoder is connected to a control connection of the switching device of one of the downstream decoders, such that when the decoder by the address register is activated, by means of a signal appearing on one of the output lines of the main decoder, only that downstream decoder is activated as the only one whose switching device is connected to the relevant output line
  • the invention is therefore based on the object of providing a semiconductor memory with a very high storage capacity, extremely short access time and minimal power loss using the highest integration technology, the effective word line capacities of which, in spite of substantial expansion of the word lines, i.e. Increasing the number of bits per word line is reduced.
  • the present solution proposes a circuit concept that avoids the disadvantages described above. Due to the division of the word lines into several partial word lines and the insertion of separately controllable word switches for each partial word line, the effectively effective word line capacity is now only 2. of the total effective word line capacity without subdivision. For typical N numbers of 8 or 16, the power / speed ratio of the memory cell selection can be effortlessly improved by an order of magnitude. The additional space required for the multiple word driver transistors is negligible if, for example, 16 memory cells are arranged on a partial word line. It is also noteworthy that the word switches in MTL memories can be enclosed in the trough of the memory cells in order to further reduce the space requirement.
  • the additional word drive line which runs parallel to the divided word lines and which drives all word switches of a word together, requires practically no additional space, particularly in MTL technology and also in the case of multilayer metallization.
  • the word switch transistors cannot be designed as power transistors, but rather as so-called minimum transistors.
  • With the MTL storage they can be integrated with the storage cells in the same tub.
  • Another great advantage is that the voltage drop along the word line is reduced considerably because of the small current and the very short length. This allows small word line switching level differences to be worked with. The interference conditions on the lines for the entire chip are significantly reduced, so that the overall performance limits of such a chip improve significantly.
  • X word drive lines can be combined by dividing the connections to the Y word drive lines accordingly and increasing the number of Y word control lines accordingly.
  • This option provides an additional degree of freedom for an optimal splitting of the word lines in the entire memory array.
  • the load for the drivers of the X and Y drive lines optimally redistributed and thus achieved an extremely good speed / performance ratio of the memory.
  • the space required for the memory cell array and the peripheral circuits at a certain speed is minimal, since one does not have to enlarge the conductor widths, but also manages very long selection lines with minimal conductor widths due to the reduced currents.
  • the circuit diagram shown in FIG. 1 shows a word-organized memory matrix with divided word lines WL and additional word drive lines WB and WE.
  • the word lines WL of the entire memory cell matrix are divided into a plurality of word lines WL1, WL2, ..., WLN divided, and each partial word line is controlled by a separate word switch in the form of a transistor T1, T2, ..., TN.
  • an additional word drive line WB is introduced into the memory structure, which drives all word switches Tl, T2, ..., TN of a word together.
  • the two XY word control lines can be attached in separate layers and then run parallel to each other.
  • the selection of a single partial word line, for example WL1 is carried out by an X - Y control of the respective word switch, for example Tl, with the aid of the corresponding word control lines, for example WB1 and WE1.
  • the effective word line capacity is now only N of the total effective word line capacity of a previous memory without the word line division shown here.
  • the power / speed ratio of such a semiconductor memory can be improved by an order of magnitude.
  • the additional space required for the multiple word driver transistors is negligibly small if, for example, a partial word line 16 memory cells allocated.
  • the word switches can be included in the tub of the memory cells, which further reduces the overall space requirement.
  • Fig. 2 another embodiment is shown, which is intended to show that in connection with Fig. 1 described principle of word line subdivision can also be applied to memory cell arrays with positive word line selection pulse, such as bipolar cross-coupled multi-emitter transistor cells.
  • the circuit-like difference to the circuit according to FIG. 1 consists only in the fact that the word drive lines WBI, WB2, ... are not routed directly to the base of the word switches T1, T2, ..., TN, but via a resistor RB for decoupling of selected and unselected word control lines, e.g. WB1, WB2 or WE1, WE2.
  • PNP transistors can also be used.
  • FIG. 3 shows a further modified exemplary embodiment of a semiconductor memory, in which two or more X word drive lines are combined by the connections to the Y word drive lines being divided accordingly and the number of Y word drive lines being increased accordingly.
  • An X word drive line for example WBl ', is therefore connected to the bases of at least two word switches Tl and T1 1 , while the Y word drive lines WEla, b each have the emitter of a word switch Tl or Tl belonging to this X word drive line WB1' l are connected.
  • This option provides an additional degree of freedom for an optimal splitting of the word lines in the entire memory array.
  • FIG. 4 shows a further variant of the circuit principle, which can be used very advantageously in the case of the opposite starting conditions to FIG. 3.
  • a dual arrangement with combined Y-word drive lines WE1, 2 and correspondingly increased X-drive lines WBa and b is shown.
  • a Y word drive line WE is therefore connected to the emitters of the word drive line, e.g. WBla and b, associated word switches Tl and T2, during which the divided X word drive lines WBa and b are each connected to a base of these word switches Tl and T2.
  • circuit principle of the word line division into several sections enables an optimal array division, which is adapted to the respective physical (layout) and electrical parameters (capacitances and resistances) of the memory matrix and to the external and internal organizations of the memory chip is. This results in a significant improvement in the power / speed ratio of the respective memory chip with a minimal space requirement.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
EP83105171A 1983-05-25 1983-05-25 Mémoire semi-conductrice Expired EP0126784B1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE8383105171T DE3380678D1 (en) 1983-05-25 1983-05-25 Semiconductor memory
EP83105171A EP0126784B1 (fr) 1983-05-25 1983-05-25 Mémoire semi-conductrice
JP59049454A JPS59217290A (ja) 1983-05-25 1984-03-16 半導体メモリ
CA000452131A CA1211212A (fr) 1983-05-25 1984-04-16 Memoire a semiconducteur
US06/602,866 US4596000A (en) 1983-05-25 1984-04-23 Semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP83105171A EP0126784B1 (fr) 1983-05-25 1983-05-25 Mémoire semi-conductrice

Publications (2)

Publication Number Publication Date
EP0126784A1 true EP0126784A1 (fr) 1984-12-05
EP0126784B1 EP0126784B1 (fr) 1989-10-04

Family

ID=8190486

Family Applications (1)

Application Number Title Priority Date Filing Date
EP83105171A Expired EP0126784B1 (fr) 1983-05-25 1983-05-25 Mémoire semi-conductrice

Country Status (5)

Country Link
US (1) US4596000A (fr)
EP (1) EP0126784B1 (fr)
JP (1) JPS59217290A (fr)
CA (1) CA1211212A (fr)
DE (1) DE3380678D1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0257680A1 (fr) * 1986-08-27 1988-03-02 Koninklijke Philips Electronics N.V. Circuit de mémoire intégrée avec sélection par bloc
EP0600184A2 (fr) * 1992-10-06 1994-06-08 Nec Corporation Dispositif de mémoire à semi-conducteurs ayant une structure de paires de lignes de mot

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE47928T1 (de) * 1984-05-14 1989-11-15 Ibm Halbleiterspeicher.
US4797858A (en) * 1987-03-30 1989-01-10 Motorola, Inc. Semiconductor memory with divided word lines and shared sense amplifiers
JPH0628861A (ja) * 1992-07-07 1994-02-04 Oki Electric Ind Co Ltd 半導体記憶装置
EP0624844A2 (fr) * 1993-05-11 1994-11-17 International Business Machines Corporation Architecture d'antémémoire entièrement intégrée
JPH08129876A (ja) * 1994-10-28 1996-05-21 Nec Corp 半導体記憶装置
US8713491B2 (en) * 2012-03-29 2014-04-29 Taiwan Semiconductor Manufacturing Co., Ltd. Pre-colored methodology of multiple patterning

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3736574A (en) * 1971-12-30 1973-05-29 Ibm Pseudo-hierarchy memory system
DE2523853B1 (de) * 1975-05-30 1976-10-07 Ibm Deutschland Verfahren und Schaltungsanordnung zum Betreiben eines Informationsspeichers
EP0050022A2 (fr) * 1980-10-09 1982-04-21 Fujitsu Limited Dispositif de mémoire statique semiconductrice

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3599182A (en) * 1969-01-15 1971-08-10 Ibm Means for reducing power consumption in a memory device
US3959781A (en) * 1974-11-04 1976-05-25 Intel Corporation Semiconductor random access memory
DE2612666C2 (de) * 1976-03-25 1982-11-18 Ibm Deutschland Gmbh, 7000 Stuttgart Integrierte, invertierende logische Schaltung
DE2855866C3 (de) * 1978-12-22 1981-10-29 Ibm Deutschland Gmbh, 7000 Stuttgart Verfahren und Schaltungsanordnung zum Betreiben eines integrierten Halbleiterspeichers
JPS6042554B2 (ja) * 1980-12-24 1985-09-24 富士通株式会社 Ｃｍｏｓメモリデコ−ダ回路
JPS6059677B2 (ja) * 1981-08-19 1985-12-26 富士通株式会社 半導体記憶装置
JPS58211393A (ja) * 1982-06-02 1983-12-08 Mitsubishi Electric Corp 半導体メモリ装置
JPS5930294A (ja) * 1982-08-11 1984-02-17 Toshiba Corp 半導体記憶装置
JPS5975488A (ja) * 1982-10-20 1984-04-28 Mitsubishi Electric Corp 半導体メモリ装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3736574A (en) * 1971-12-30 1973-05-29 Ibm Pseudo-hierarchy memory system
DE2523853B1 (de) * 1975-05-30 1976-10-07 Ibm Deutschland Verfahren und Schaltungsanordnung zum Betreiben eines Informationsspeichers
EP0050022A2 (fr) * 1980-10-09 1982-04-21 Fujitsu Limited Dispositif de mémoire statique semiconductrice

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0257680A1 (fr) * 1986-08-27 1988-03-02 Koninklijke Philips Electronics N.V. Circuit de mémoire intégrée avec sélection par bloc
EP0600184A2 (fr) * 1992-10-06 1994-06-08 Nec Corporation Dispositif de mémoire à semi-conducteurs ayant une structure de paires de lignes de mot
EP0600184B1 (fr) * 1992-10-06 1999-09-08 Nec Corporation Dispositif de mémoire à semi-conducteurs ayant une structure de paires de lignes de mot

Also Published As

Publication number Publication date
CA1211212A (fr) 1986-09-09
JPH041957B2 (fr) 1992-01-14
JPS59217290A (ja) 1984-12-07
EP0126784B1 (fr) 1989-10-04
US4596000A (en) 1986-06-17
DE3380678D1 (en) 1989-11-09

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