EP0099114B1 - Simulateur logique pouvant opérer par base de niveaux et sur base de blocs logiques à chaque niveau - Google Patents

Simulateur logique pouvant opérer par base de niveaux et sur base de blocs logiques à chaque niveau Download PDF

Info

Publication number
EP0099114B1
EP0099114B1 EP83106834A EP83106834A EP0099114B1 EP 0099114 B1 EP0099114 B1 EP 0099114B1 EP 83106834 A EP83106834 A EP 83106834A EP 83106834 A EP83106834 A EP 83106834A EP 0099114 B1 EP0099114 B1 EP 0099114B1
Authority
EP
European Patent Office
Prior art keywords
logic
block
output
signal
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP83106834A
Other languages
German (de)
English (en)
Other versions
EP0099114A2 (fr
EP0099114A3 (en
Inventor
Tohru Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP57121600A external-priority patent/JPS5911459A/ja
Priority claimed from JP57121599A external-priority patent/JPS5911458A/ja
Priority claimed from JP57177073A external-priority patent/JPS5966754A/ja
Application filed by NEC Corp filed Critical NEC Corp
Publication of EP0099114A2 publication Critical patent/EP0099114A2/fr
Publication of EP0099114A3 publication Critical patent/EP0099114A3/en
Application granted granted Critical
Publication of EP0099114B1 publication Critical patent/EP0099114B1/fr
Expired legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Definitions

  • This invention relates to a logic simulatorfor use in simulating operation of a logic device, which may be an electronic digital computer comprising a central processing unit, a main memory, a cache memory, and microprogram memories.
  • the device input signal may comprise a plurality of individual device input signals and the device output signal, a plurality of individual device output signals.
  • Each logic block has at least one inputterminal and at least one outputterminal. It is to be noted as regards the predetermined manner of connection that an output terminal of a logic block is not ordinarily connected to at least one input terminal thereof but either to at least one input terminal of another logic block or to input terminals of other logic blocks and that each individual device input (output) signal is for at least one input (output) terminal of at least one logic block.
  • Each individual logic operation need not be a single AND operation for two or more input logic states, a single inverting operation, or the like single operation but may be a combination of such single logic operations.
  • the logic blocks are identified by block numbers, respectively.
  • the block input and output terminals are identified by block input and output terminal numbers, respectively.
  • One and the same block input terminal number may be used in common for inputterminals of different logic blocks. Even in this event, it is possible to understand that such input terminals are identified by different block input terminal numbers, respectively, because the logic blocks are identified by different block numbers, respectively.
  • the predetermined manner of connection between a block output (input) terminal and at least one block input (output) terminal is defined by a combination of a block output (input) terminal number and at least one block input (output) terminal number. It is therefore possible to define the predetermined manner of connection by such combinations.
  • a logic simulator is very effective in error diagnosis of an overall or a partial logic operation of a logic device. With a logic simulator, it is possible to find the design error without actually manufacturing the logic device in compliance with a possibly erroneous design.
  • a logic simulator according to this invention as claimed isforsimulating an overall logic operation carried out by a logic device on a device input signal to provide a device output signal.
  • the logic device should be divisible into a plurality of logic blocks which are identified by block numbers, respectively, are for carrying out individual logic operations identified by types, respectively, and have block input and output terminals identified by block input and output terminal numbers, respectively, and directly connected to one another in a predetermined manner of connection so that the device input signal may flow through the logic blocks to provide input and output logic states at the block input and output terminals with the individual logic operations carried out on the input logic states to provide the output logic states and eventually the device output signal.
  • the logic blocks are given level numbers according to the flow of the device input signal from a less number to a greater number.
  • the logic simulator according to this invention comprises first signal producing means, first memory means, simulating means, second signal producing means, second memory means, substituting means, and updating means as follows.
  • the first signal producing means is for producing a first address signal successively indicative of the block numbers of the respective logic blocks of each level number and then the block number for a next greater level number.
  • the first memory means is for memorizing, for the respective block numbers, the types and, for each block number, the input and output logic states of the respective block input and output terminals of the logic block of the block number under consideration.
  • the first memory means is responsive to the first address signal indicative of each block number to produce a first output signal representative of the type for the block number being indicated and the input and output logic states for the indicated block number.
  • the simulating means is responsive to the first output signal produced in response to the first address signal indicative of each block number for simulating the individual logic operation of the type represented by the first output signal to provide a simulated logic operation for the indicated block number.
  • the simulating means thereby carries out the simulated logic operation on the input logic states represented by the first output signal to provide simulated logic states for the indicated block number and to produce a simulated signal representative of the simulated logic states.
  • the second memory means is for memorizing, for each block number, the block numbers of those connected ones of the logic blocks which have block input terminals directly connected in the predetermined manner of connection to the block output terminals of the logic block of the block number under consideration and, for the respective block output terminal numbers of the last-mentioned block output terminals, the block input terminal numbers of the last-mentioned block input terminals.
  • the second memory means is responsive to the second address signal to produce a second output signal representative of the block number of each connected logic block for the block number indicated by the first part and those state-varied ones of the block input terminal numbers which are memorized for the respective state-varied output terminal numbers indicated by the second part.
  • the updating means is coupled to the first memory means and is responsive to the second output signal for updating, with reference to the state-varied input terminal numbers represented by the second output signal, the input logic states memorized in the first memory means for the block number represented by the second output signal.
  • Each equivalent logic simulator comprises similar means, which are operable in response to a different combinations of input signals to produce an output signal representative of like and yet somewhat different items.
  • the additional memory means is for memorizing, for each block number, the block number under consideration and the block output terminal numbers for the block number under consideration.
  • the additional memory means is responsive to the second address signal to produce an additional output signal representative of the block number indicated by the first part and the state-varied output terminal numbers indicated by the second part.
  • the means coupled to the updating means is responsive to the additional output signal for making the updating means update, with reference to the state-varied output terminal numbers represented by the additional output signal, the output logic states memorized in the first memory means for the block number represented by the additional output signal.
  • a logic simulator of the above-specified type wherein the first signal producing means makes the first address signal keep indication of each block number until the substituting means substitutes the simulated logic states for the output logic states memorized in the first memory means for the block number being indicated.
  • a logic simulator of the above-specified type for which the logic blocks of each level number are allotted to a third predetermined number of groups.
  • each of the first signal producing means, the first memory means, the simulating means, the second signal producing means, the second memory means, and the substituting means is assigned to the respective groups so that one of the first signal producing means, that one of the first memory means, that one of the simulating means, that one of the second signal producing means, that one of the second memory means, and that one of the substituting means, all of which are assigned to each group, are for dealing with the block number of the logic block of the group under consideration.
  • the updating means comprises first and second means as follows.
  • the first means is coupled to the first memory means assigned to the respective groups and is responsive to the second output signal produced by the second memory means assigned to each group for updating the input logic states in the first memory means assigned to the group comprising the logic block of the block number represented by the last-mentioned second output signal.
  • the second means is coupled to the first means and to the first signal producing means assigned to the respective groups and is for making the first address signal successively indicate the level numbers from each thereof to another thereof when the input logic states are updated by the first means in the first memory means assigned to the respective groups.
  • the logic device comprises first through fourth device input terminals 11, 12, 13, and 14 and first and second device output terminals 16 and 17.
  • the logic device is divided into first through eighth logic blocks 21, 22, 23, 24, 25, 26, 27, and 28. Each logic block has at least one block input terminal and at least one block output terminal.
  • each logic block is an IC.
  • Each block input terminal is therefore an input pin and each block output terminal, an output pin. It will moreover be assumed that the input and the output pins are directly connected to one another and to the (device) input and output terminals 11 through 14, 16, and 17 in compliance with a predetermined manner of connection, which is depicted in the figure being referred to.
  • the IC's 21 through 28 are for carrying out various individual logic operations on device input signals supplied to the respective input terminals 11 through 14 to provide device output signals at the respective output terminals 16 and 17.
  • logic-processed signals flow through the IC's 21 to 28 generally from the input terminals 11 through 14 towards the output terminals 16 and 17 as block or pin input and output signals.
  • Each of the device and pin input and output signals takes either of logic one and zero states at a time.
  • level numbers are assigned to the IC's 21 through 28 in accordance with the general flow of signals. More specifically, three IC's 21 through 23 having input pins directly connected to the input terminals 11 through 14 and depicted at the top of the IC's 21 through 28, are given a level number one. Alternatively, the three IC's 21 through 23 are referred to as IC's of a first level or first level IC's. Two IC's 24 and 25 which receive pin output signals from the first level IC's 21 through 23, are assigned with a level number two. In this manner, two other IC's 26 and 27 are given a level number three. Only one IC 28 is exemplified as a fourth level IC.
  • input terminal logic states of the input terminals 11 through 14 vary from time to time between the logic one and zero states.
  • Pin output logic states at the respective output pins of an IC of a certain level number are dependent on the input terminal logic states and the individual logic operation carried out thereby on the input pin logic states.
  • the logic state of an output pin depends on the number of IC's through which a device input signal appears at the output pin under consideration, namely, the number of individual logic operations carried on the device input signal.
  • the above-exemplified level number is equal to the maximum of the numbers of such IC's or individual logic operations.
  • the input and output terminal logic states and input and output pin logic states which the logic device has at the start of the patient behavior will be referred to with addition of a modifier "initial.”
  • the IC's 21 through 28 are identified by block numbers, respectively.
  • the IC's of the first level are preferably identified by block numbers starting at one.
  • block numbers one through three will be given to the first through the third IC's 21 to 23.
  • the IC's of every level number are conveniently identified by consecutively ascending block numbers.
  • the fourth through the eighth IC's 24 to 28 are identified by block numbers four through eight.
  • the order in which the block numbers are given to the IC's of each level number, is immaterial.
  • the block numbers one through eight will be represented by decimal 100 through 800, respectively.
  • the input terminals 11 through 14 provide the input logic states of at least the IC's 21 through 23 of the first level. It is therefore possible to understand that the input terminals 11 through 14 are four input pins of an "IC" of a block number zero and of a level number zero or a zeroth level.
  • the "IC” is for carrying out a specific individual logic operation of giving the output logic states by the input logic states as they are.
  • the input terminals 11 through 14 therefore serve also as the output pins of the "IC" of the block number zero and of the level number zero.
  • the first IC 21 given the block number 100 has two input pins and two output pins. According to the predetermined manner of connection, the two input pins are directly connected to the first and the second input terminals 11 and 12. The two output pins are directly connected to two of three input pins of the fourth IC 24.
  • Such input pins of each IC may be given first, second, and similar input pin (namely, block input terminal) numbers, which are conveniently represented by 01,02, and so forth.
  • the output pins of each IC are given first, second, and like output pin numbers, which may be designated by 11, 12, and so on. In this manner, it is possible to identify all pins of the IC's 21 through 28 by three-digit decimal numbers unless at least one of the IC's has one hundred or more pins.
  • the input or the output pins will be numbered from left to right in the figure.
  • Each IC usually has more than thirty input and more than thirty output pins. It is therefore more convenient to use "5" as the ten's digit of the output pin numbers rather than the ten's digit of "1" as described above.
  • the fifth IC 25 has first and second input pins 501 and 502 directly connected to a single output pin 351 of the third IC 23 and to a second output pin 252 of the second IC 22, respectively.
  • First and second output pins 551 and 552 are directly connected to third and fourth input pins 603 and 604 of the sixth IC 26 and also to first and second input pins 701 and 702 of the seventh IC 27.
  • the input terminals 11 through 14 may likewise be given input "pin” numbers 001 through 004, respectively.
  • the output terminals 16 and 17 are the output pins of at least one IC and need not be given specific output "pin” numbers.
  • the individual logic operations may or may not differ from an IC to another. It will be assumed for clarity of description that the IC's 21 and 25 are for carrying out individual logic operations of a first type.
  • the IC's 22 and 24 are for carrying out individual logic operations of a second type, the IC's 23 and 27, individual logic operations of a third type, and the IC's 26 and 28, individual logic operations of a fourth type. It should be understood that the differently numbered types show different individual logic operations.
  • each individual logic operation may be a combination of logic operations to be carried out on the input logic states of the IC in question. At any rate, the individual logic operations of the respective IC's will be identified by differently numbered types.
  • the number of different individual logic operations is referred to hereinabove as the first predetermined number.
  • the first predetermined number is equal to four.
  • the number of levels is called the second predetermined number. Attention may be directed only to the actual IC's 21 through 28. In this event, the second predetermined number is equal to four. If the zeroth level is also taken into account, the second predetermined number becomes equal to five.
  • a logic simulator according to an embodiment of the invention is for use in simulating an overall logic operation of a logic device of the type exemplified with reference to Figure 1.
  • Various circuit units which will be described in the following, will later be described in detail as the description proceeds with reference to other figures of the accompanying drawing.
  • a first memory unit 32 is for memorizing, for the respective block numbers zero through eight, the types and, for each block number, the input and output logic states of the respective input and output pins of the IC of the block number under consideration.
  • the first memory unit 32 is responsive to the first address signal indicative of each block number to produce a first output signal representative of the type of the IC of the block number being indicated and the input and output logic states of the input and output pins of the IC of the indicated block number.
  • a simulating unit 36 is responsive to the first portion 33 produced in response to the first address signal indicative of each block number for simulating the individual logic operation of the type represented by the first portion 33.
  • the simulating unit 36 thereby provides a simulated logic operation for the IC of the indicated block number and carries out the simulated logic operation on the input logic states represented by the first portion 33 to provide simulated logic states for the output pins of the IC of the indicated block number and to produce a simulated signal representative of the simulated logic states.
  • a second signal producing unit 37 is supplied with the first address signal, the second portion 34, and the simulated signal.
  • the second signal producing unit 37 produces a second address signal comprising a first and a second part.
  • the first part is indicative of each block number indicated by the first address signal.
  • the second part is indicative of state-varied output pin numbers identifying those stated-varied ones of the output pins of the IC of the block number indicated by the first part at which the output logic states represented by the second portion 34 are varied to the simulated logic states represented by the simulated signal.
  • the second signal producing unit 37 comprises a comparator 38 for comparing the simulated logic states bit by bit with the output logic states represented by the second portion 34.
  • the comparator 38 produces a result signal in which a logic one and a logic zero bit appear when each simulated logic state is different from and the same as, respectively, the output logic state subjected to the bit by bit comparison with the simulated logic state in question.
  • a modifying circuit 39 converts the result signal into the second part of the second address signal.
  • a second memory unit 42 is for memorizing, for each block number, the block numbers of those connected ones of the IC's 21 through 28 which have input pins directly connected in compliance with the predetermined manner of connection to the output pins of the IC of the block number under consideration and, for the respective output pin numbers of the last-mentioned output pins, the input pin numbers of the last-mentioned input pins. Responsive to the second address signal, the second memory unit 42 produces a second output signal representative of the block number of each IC connected to the IC of the block number indicated by the first part. The second output signal is moreover representative of those state-varied ones of the input pin numbers which are memorized for the respective state-varied output pin numbers indicated by the second part.
  • a substituting unit 46 is coupled to the first memory unit 32 and is responsive to the simulated signal for substituting the simulated logic states represented" by the simulated signal produced in response to the first address signal indicative of a block number, for the output logic states memorized in the first memory unit 32 for the block number in question.
  • the substituting unit 46 is therefore equivalently responsive to the first address signal and the second portion 34 to substitute the simulated logic states for the output logic states represented by the second portion 34, namely, memorized in the first memory unit 32 for the block number indicated by the first address signal.
  • An updating unit 47 is coupled to the first memory unit 32 and is responsive to the second output signal for updating or renewing, with reference to the state-varied input pin numbers represented by the second output signal, the input logic states memorized in the first memory unit 32 for the block number represented also by the second output signal.
  • the logic simulator comprises a state memory, a simulator, a comparator, and a connection memory, which are of the types described as the first memory unit 32, the simulating unit 36, the comparator 38, and the second memory unit 42 in conjunction with Figure 2 and will be designated by like reference numerals.
  • a first multiplexer 51 is for supplying a first address signal to the state memory 32.
  • a second multiplexer 52 is for delivering a second address signal to the connection memory 42.
  • the first address signal indicates, during indication of the first through the fourth levels, the block numbers 100 through 800 which identify the respective IC's 21 through 28 and are used instead of the actual IC's 21 to 28. In other words, the block numbers simulate the respective IC's. Before indication of the first block number 100, the first address signal indicates zero as the zeroth block or level number.
  • the second address signal is controlled so as to consecutively indicate the block numbers 100 through 800 and, while indicating each block number, state-varied output pin numbers assigned to those state-varied output pins of the IC identified by the block number being indicated, at each of which a variation takes place in the output logic state as a result of the simulation carried out by the simulator 36 as will later be described more in detail.
  • the state-varied output pin numbers are used in place of the actual state-varied output pins.
  • the second address signal is also made to indicate zero. Those parts of the second address signal which indicate the block number and the state-varied output pin numbers, will be called first and second parts, respectively.
  • the state memory 32 comprises a plurality of block memory sectors (not shown) accessible by the first address signal indicative of the respective block numbers 100 through 800. Stated otherwise, the memory sectors are assigned to the respective IC's 21 through 28 according to the respective block numbers. The state memory 32 has an additional memory sector accessible by the first address signal indicative of zero.
  • the block memory sector allotted to each IC is for storing state data of the IC under consideration.
  • the block memory sector is for furthermore storing a block flag Fo, which will presently be described.
  • Each block memory sector comprises a type field, a state field, and a flag field.
  • the state field comprises, in turn, a plurality of bit positions, such as eleventh through thirtieth bit positions of the memory sector as first through twentieth bit positions of the state field.
  • the first through the twentieth bit positions of the state field are assigned to the input and the output pin numbers which identify the input and the output pins of the IC assigned with the memory sector in question.
  • the state data to be stored in each memory sector comprise the type of the individual logic operation of the IC.
  • a type signal representative of the type is stored in the type field.
  • the state data moreover comprise the input and the output logic states, which are stored in the state field according to the respective pin numbers. For example, letthe first and the second input pins have at an instant logic one and zero states, respectively. Logic one and zero bits are stored in the first and the second bit positions of the state field. It will be understood that the state data are for use in more specifically simulating the IC's together with their input and output logic states.
  • the block flag Fb is for discriminating between the IC's which have each level number in common.
  • a logic one flag a logic one bit is stored in the flag field of the memory sector assigned to the IC that is identified by the greatest block number among the block numbers of the IC's of the level number under consideration.
  • the flag fields of the memory sectors for the other IC's are loaded with logic zero flags. The logic one block flags therefore serve as level flags.
  • the first address signal indicative of a block number makesthe state memory 32 produce the block flag Fb from the memory sector accessed by the block number being indicated.
  • a level flag is produced, it is understood that the block number or numbers of one level number is all indicated by the first address signal.
  • the first address signal thus equivalently indicates the successive level numbers. Stated otherwise, the first address signal need not actually indicate the respective level numbers but may merely indicate the block numbers from a level numberto a higher level number.
  • the simulator 36 may comprise IC's (not shown) which are for carrying out different individual logic operations, respectively. According to the above-described assumption, the simulator 36 comprises four IC's which correspond in operation to the IC's 21 through 23 and 24, respectively.
  • the simulator 36 may alternatively be a general logic circuit, which may comprise a gate array for simulating the different individual logic operations.
  • the simulator 36 may comprise an input-output mapping memory. As has briefly been described heretobefore, the simulator 36 provides simulated logic states which correspond to new output logic states obtained by the individual logic operation of each of the IC's 21 through 28.
  • the comparator 38 compares the simulated logic states with previous output logic states preliminarily read out of the state memory 32.
  • the previous output logic states are supplied to the comparator 38 through a state latch circuit 53.
  • the simulated logic states are delivered to the comparator 38 through a simulator latch circuit 54.
  • connection memory 42 comprises a plurality of block memory segments (not shown) accessible by the second address signal indicate of the respective block numbers 100 through 800. Each memory segment is furthermore accessed by the second address signal indicative of the state-varied output pin numbers. An additional memory segment is accessible by the second address signal indicative of zero and likewise state-varied input terminal numbers.
  • the state FIFO signal next gives the above- mentioned one block number and the input pin numbers correspnding to the state-varied output pin numbers. Previous input logic states for that block number are renewed or updated to new input logic states. In this manner, the previous input logic states of the higher level number or numbers are rendered equal to the new output logic states for the b-th block number.
  • a logic device will temporarily be assumed which is similar to the illustrated one except that the second and the fourth levels consist of only one logic block and of two logic blocks, respectively, and that the third logic block 23 has block output terminals connected only to block input terminals of a third level logic block and of a fourth level logic block.
  • the third logic block 23 need not necessarily be given the level number one.
  • the maximum of the numbers of individual logic operations by which the output logic states of the third logic block 23 is one.
  • the maxima of the numbers of individual logic operations by which the input logic states are decided are two and three for the logic blocks to which attention is directed.
  • the minimum of the maxima is two.
  • the third Logic block 23 may therefore be of any one of the level numbers one and two. When the third logic block 23 is given the level number two, each level consists of two logic blocks.
  • the first reversal circuit 56 inverts the state flag Fs from the posterior state to the prior state. This shows that the output logic states are not yet renewed during the instant cycle of the diagnosis operation and are subject to the renewal by the simulated logic states.
  • the logic simulation system is for use in carrying out a diagnosis operation on an overall logic operation of a logic device in which the IC's of each level are allotted to a third predetermined number of groups. It is preferred that the third predetermined number be not less than the maximum number of IC's on each level.
  • the above-described natural number N is equal to the third predetermined number.
  • the IC's or the block numbers are therefore allotted to a first through an N-th group.
  • the block numbers 100, 400, and 600 of the first, fourth, and sixth IC's 21, 24, and 26 ( Figure 1) are allotted to the first group.
  • the block numbers 200, 300, and 700 are allotted to the second group.
  • the first through the N-th group logic simulators 81-1 to 81-N are assigned to the first through the N-th groups, respectively. On so forming groups of IC's, it is desirable that the groups have approximately equal numbers of IC's.
  • each group logic simulator 81 (the affix omitted) is similar in structure to the logic simulator illustrated with reference to Figure 4.
  • the group logic simulator 81 comprises a state memory 32, a simulator 36, a (second) signal producing circuit 37, and a connection memory 42.
  • the state register 76 ( Figure 4), when used as a substituting unit 46 ( Figure 2), is depicted by a mere connection extended from the simulator 36 to the state memory 32.
  • the first address signal is produced by a local controller 82, which is shown to exchange data with the state memory 32 (for example, the logic one block flag used as the level flag), the simulator 36 (the state flag Fs), the signal producing circuit 39 (the first address signal used as the first part of the second address signal), and the connection memory 42.
  • the state memory 32 for example, the logic one block flag used as the level flag
  • the simulator 36 the state flag Fs
  • the signal producing circuit 39 the first address signal used as the first part of the second address signal
  • the logic one block flag (the level flag) is detected by the local controller 82 of a certain one of the group logic simulators 81.
  • the local controller 82 delivers the level simulation end signal to a central controller 87.
  • the central controller 87 makes the local controller 82 of the respective group logic simulators 81 produce the first address signals indicative of different block numbers of the next higher level.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Quality & Reliability (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Claims (5)

1. Simulateur logique pour simuler une opération logique générale exécutée par un dispositif logique (figure 1) sur un signal (11, 12, 13, 14) d'entrée à un dispositif pour fournir un signal de sortie du dispositif (16, 17), le dispositif logique pouvant être divisé en une multitude de blocs logiques (21-28) qui sont identifiés par des numéros de bloc (1 à 8) respectivement, blocs destinés à exécuter des opérations logiques individuelles identifiées par des types, respectivement, et ayant des bornes d'entrée et de sortie de bloc identifiées par des numéros de borne d'entrée et de sortie de bloc, respectivement, et bornes qui sont directement connectées l'une à l'autre selon une manière prédéterminée de connexion de sorte que le signal d'entrée au dispositif peut traverser le dispositif logique pour fournir des états logiques d'entrée et de sortie aux bornes d'entrée et de sortie de bloc, avec les opérations logiques individuelles effectuées sur les états logiques d'entrée %fin de fournir lesdits états logiques de sortie et finalement le signal de sortie du dispositif, les blocs logiques ayant reçu des numéros de niveau selon la circulation du signal d'entrée au dispositif entre un niveau de numéro inférieur et un niveau de numéro supérieur, le simulateur logique comprenant:
-un premier moyen (31) de production de signal pour produire un premier signal d'adresse représentatif successivement des numéros des blocs logiques respectifs de chaque numéro de niveau et ensuite le numéro de bloc pour le numéro de niveau supérieur suivant;
-un premier moyen de mémoire (32) pour mémoriser, pour les numéros de bloc respectifs, les types et, pour chaque numéro de bloc, les états logiques d'entrée et de sortie du bloc logique du numéro de bloc considéré, ce premier moyen de mémoire répondant au premier signal d'adresse représentatif de chaque numéro de bloc pour produire un premier signal de sortie (en 33) représentatif du type pour le numéro de bloc indiqué et l'état logique d'entrée (en 33) et l'état logique de sortie (en 34) pour le numéro de bloc indiqué;
-un moyen de simulation (36) répondant au premier signal de sortie produit en réponse au premier signal d'adresse représentatif de chaque numéro de bloc pour simuler l'opération logique individuelle du type représenté par le premier signal de sortie (en 33) afin de fournir une opération logique simulée pour le numéro de bloc indiqué, ce moyen de simulation exécutant ainsi l'opération logique simulée sur les états logiques d'entrée représentés par le premier signal de sortie afin de fournir des états logiques simulés pour le numéro de bloc indiqué et de produire un signal simulé représentatif des états logiques simulés;
-un second moyen de production de signal (37) répondant à la première adresse et aux signaux d'état logique d'entrée/sortie en provenance du premier moyen de mémoire et au signal simulé pour produire un second signal d'adresse comprenant une première et une seconde partie, la première partie étant représentative de chaque numéro de bloc indiqué par le premier signal d'adresse, la seconde partie étant représentative des numéros des bornes de sortie dont l'état a varié, identifiant celles des bornes à l'état ayant varié parmi les bornes de sortie du bloc logique du numéro de bloc indiqué par la première partie à laquelle les états logiques de sortie représentés par le premier signal de sortie ont changé en états logiques simulés représentés par le signal simulé;
-un second moyen de mémoire (42) pour mémoriser, pour chaque numéro de bloc, les numéros des blocs connectés parmi les blocs logiques qui ont des bornes d'entrée de bloc directement connectées selon ladite manière prédéterminée de connexion aux bornes de sortie du bloc logique ayant le numéro de bloc sous considération, et pour les numéros respectifs des bornes de sortie de bloc parmi les bornes de sortie de bloc citées en dernier, les numéros des bornes d'entrée de bloc des bornes d'entrée de bloc cités en dernier, le second moyen de mémoire (42) répondant au second signal d'adresse pour produire un second signal de sortie représentatif du numéro de bloc de chaque bloc logique connecté pour le numéro de bloc indiqué par la première partie et les numéros à l'état ayant varié parmi les numéros des bornes d'entrée de bloc qui sont mémorisés pour les numéros respectifs des bornes de sortie à l'état ayant varié, indiqués par la seconde partie;
-un moyen de substitution (46) couplé au premier moyen de mémoire (32) et répondant au signal simulé pour substituer les états logiques simulés représentés par le signal simulé produit pour le numéro de bloc indiqué par le premier signal d'adresse pour les états logiques de sortie mémorisés dans le premier moyen de mémoire pour le numéro de bloc indiqué par le premier signal d'adresse; et
-un moyen de mise à jour (47) couplé au premier moyen de mémoire (32) et répondant au second signal de sortie provenant du second moyen de mémoire pour mettre à jour, par référence aux numéros des bornes d'entrée à l'état ayant varié, représentés par le second signal de sortie, les états logiques d'entrée mémorisés dans le premier moyen de mémoire pour le numéro de bloc représenté par le second signal de sortie.
2, Simulateur logique selon la revendication 1, dans lequel le numéro de niveau est attribué à chaque bloc logique avec l'attention portée aux blocs logiques ayant des bornes d'entrée de bloc directement connectées aux bornes de sortie du bloc logique sous considération de façon à ne pas être inférieur au maximum des nombres des opérations logiques individuelles par lesquelles les états logiques de sortie sont décidés pour les bornes de sortie du bloc logique sous considération et à ne pas être supérieur au minimum des maxima des nombres des opérations logiques individuelles par lesquelles les états logiques d'entrée sont décidés pour toutes les bornes d'entrée des blocs logiques auxquels l'attention est portée.
3. Simulateur logique selon la revendication 2, dans lequel le moyen de substitution (46) comprend:
-des moyens supplémentaires (61, 63 à 66-figure 3b) répondant au second signal d'adresse pour produire un signal de sortie supplémentaire représentatif de numéro de bloc indiqué par la première partie et les numéros des bornes de sortie à l'état ayant varié indiqués par la seconde partie;
-des moyens de renouvellement (63, 52, 42 et 72-figure 3b; 71; 51 et 56-figure 3a) couplés au premier moyen de mémoire et répondant au signal de sortie supplémentaire pour renouveler, par référence aux numéros des bornes de sortie à l'état ayant varié représentés par le signal de sortie supplémentaire, les états logiques de sortie mémorisés dans le premier moyen de mémoire pour le numéro de bloc représenté par le signal de sortie supplémentaire.
4. Simulateur logique selon la revendication 2, dans lequel le premier moyen de production de signal (31) fait en sorte que le premier signal d'adresse conserve l'indication de chaque numéro de bloc jusqu'à ce que le moyen de substitution (46) ait remplacé les états logiques simulés pour les états logiques de sortie pour le numéro de bloc indiqué.
5. Simulateur logique selon la revendication 2, les blocs logiques de chaque numéro de niveau étant affectés à un nombre prédéterminé de groupes, dans lequel:
le premier moyen de production de signal, le premier moyen de mémoire, le moyen de simulation, le second moyen de production de signal, le second moyen de mémoire, et le moyen de substitution est chacun affecté aux groupes respectifs (figure 5, 81-1 à 81-N), de sorte que ce premier moyen de production de signal (37), ce premier moyen de mémoire (32), ce moyen de simulation (36), ce second moyen de production de signal, ce second moyen de mémoire, et ce moyen de substitution, qui sont tous affectés à chaque groupe, servent au traitement du numéro du bloc logique du groupe sous-considération;
le moyen de mise à jour (86) comprenant:
-un premier moyen (72, 52-figure 3b) couplé au premier moyen de mémoire affecté aux groupes respectifs et répondant au second signal de sortie produit par le second moyen de. mémoire affecté à chaque groupe pour mettre à jour les états logiques d'entrée dans le premier moyen de mémoire affecté au groupe comprenant le bloc logique du numéro de bloc représenté par le second signal de sortie cité en dernier; et
-un second moyen (71, 51-figure 3a) couplé au premier moyen et au premier moyen de production de signal affectés aux groupes respectifs pour faire en sorte que le premier signal d'adresse indique de façon sensiblement simultanée les numéros, de bloc de chaque numéro de niveau avec les numéros de niveau successivement changés au numéro de niveau supérieur suivant lorsque les états logiques d'entrée sont mis à jour dans le premier moyen de mémoire affecté aux groupes respectifs.
EP83106834A 1982-07-13 1983-07-12 Simulateur logique pouvant opérer par base de niveaux et sur base de blocs logiques à chaque niveau Expired EP0099114B1 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP57121600A JPS5911459A (ja) 1982-07-13 1982-07-13 論理シミユレ−タ
JP57121599A JPS5911458A (ja) 1982-07-13 1982-07-13 論理シミユレ−タ
JP121599/82 1982-07-13
JP121600/82 1982-07-13
JP177073/82 1982-10-08
JP57177073A JPS5966754A (ja) 1982-10-08 1982-10-08 論理シミユレ−シヨンシステム

Publications (3)

Publication Number Publication Date
EP0099114A2 EP0099114A2 (fr) 1984-01-25
EP0099114A3 EP0099114A3 (en) 1986-01-29
EP0099114B1 true EP0099114B1 (fr) 1988-05-11

Family

ID=27314277

Family Applications (1)

Application Number Title Priority Date Filing Date
EP83106834A Expired EP0099114B1 (fr) 1982-07-13 1983-07-12 Simulateur logique pouvant opérer par base de niveaux et sur base de blocs logiques à chaque niveau

Country Status (3)

Country Link
US (1) US4725975A (fr)
EP (1) EP0099114B1 (fr)
DE (1) DE3376592D1 (fr)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3376592D1 (en) * 1982-07-13 1988-06-16 Nec Corp Logic simulator operable on level basis and on logic block basis on each level
JPS6142040A (ja) * 1984-08-03 1986-02-28 Nec Corp 論理シミユレ−タ
US5056014A (en) * 1985-02-04 1991-10-08 Lockheed Sanders, Inc. Network simulation system
JPS6274158A (ja) * 1985-09-27 1987-04-04 Hitachi Ltd 回路変換方式
US4937770A (en) * 1986-02-07 1990-06-26 Teradyne, Inc. Simulation system
CA1271259A (fr) * 1986-02-07 1990-07-03 Teradyne, Inc. Systeme simulateur
JPS62182939A (ja) * 1986-02-07 1987-08-11 Hitachi Ltd 情報処理装置の論理シミユレ−シヨン方法
US4862347A (en) * 1986-04-22 1989-08-29 International Business Machine Corporation System for simulating memory arrays in a logic simulation machine
US5126966A (en) * 1986-06-25 1992-06-30 Ikos Systems, Inc. High speed logic simulation system with stimulus engine using independent event channels selectively driven by independent stimulus programs
US4787061A (en) * 1986-06-25 1988-11-22 Ikos Systems, Inc. Dual delay mode pipelined logic simulator
US4816999A (en) * 1987-05-20 1989-03-28 International Business Machines Corporation Method of detecting constants and removing redundant connections in a logic network
CA1300265C (fr) * 1987-06-22 1992-05-05 William Curtis Newman Simulateur de diagrammes synoptiques
US4916647A (en) * 1987-06-26 1990-04-10 Daisy Systems Corporation Hardwired pipeline processor for logic simulation
US4873656A (en) * 1987-06-26 1989-10-10 Daisy Systems Corporation Multiple processor accelerator for logic simulation
US4872125A (en) * 1987-06-26 1989-10-03 Daisy Systems Corporation Multiple processor accelerator for logic simulation
US4862399A (en) * 1987-08-31 1989-08-29 General Electric Company Method for generating efficient testsets for a class of digital circuits
US4916627A (en) * 1987-12-02 1990-04-10 International Business Machines Corporation Logic path length reduction using boolean minimization
US4924430A (en) * 1988-01-28 1990-05-08 Teradyne, Inc. Static timing analysis of semiconductor digital circuits
JP2786206B2 (ja) * 1988-07-29 1998-08-13 株式会社日立製作所 機能設計図生成方法
US5572708A (en) * 1989-02-28 1996-11-05 Nec Corporation Hardware simulator capable of dealing with a description of a functional level
US5327361A (en) * 1990-03-30 1994-07-05 International Business Machines Corporation Events trace gatherer for a logic simulation machine
US5680318A (en) * 1990-12-21 1997-10-21 Synopsys Inc. Synthesizer for generating a logic network using a hardware independent description
US5410678A (en) * 1991-01-11 1995-04-25 Nec Corporation Fault simulator comprising a signal generating circuit implemented by hardware
US5500808A (en) * 1991-01-24 1996-03-19 Synopsys, Inc. Apparatus and method for estimating time delays using unmapped combinational logic networks
US5490266A (en) * 1991-03-01 1996-02-06 Altera Corporation Process oriented logic simulation having stability checking
EP0508620B1 (fr) * 1991-04-11 1998-05-20 Hewlett-Packard Company Méthode et Système pour déterminer automatiquement la fonction logique d'un circuit
EP0508619A2 (fr) * 1991-04-11 1992-10-14 Hewlett-Packard Company Interface de stimuli à socle bidirectionnel pour un simulateur logique
GB9121540D0 (en) * 1991-10-10 1991-11-27 Smiths Industries Plc Computing systems and methods
US5884065A (en) * 1992-01-10 1999-03-16 Nec Corporation Logic circuit apparatus and method for sequentially performing one of a fault-free simulation and a fault simulation through various levels of a logic circuit
DE4211162C2 (de) * 1992-03-31 1996-03-21 Manfred Dipl Ing Zeiner Hardware-Emulationssystem
US5649163A (en) * 1992-10-29 1997-07-15 Altera Corporation Method of programming an asynchronous load storage device using a representation of a clear/preset storage device
JP3056026B2 (ja) * 1993-07-29 2000-06-26 株式会社日立製作所 論理シミュレーション方法
US5559718A (en) * 1994-04-28 1996-09-24 Cadence Design Systems, Inc. System and method for model-based verification of local design rules
US5721695A (en) * 1994-10-17 1998-02-24 Advanced Micro Devices, Inc. Simulation by emulating level sensitive latches with edge trigger latches
US5615127A (en) * 1994-11-30 1997-03-25 International Business Machines Corporation Parallel execution of a complex task partitioned into a plurality of entities
JP3184420B2 (ja) * 1995-01-19 2001-07-09 株式会社日立製作所 論理分割装置および方法
US6053948A (en) * 1995-06-07 2000-04-25 Synopsys, Inc. Method and apparatus using a memory model
US5809283A (en) * 1995-09-29 1998-09-15 Synopsys, Inc. Simulator for simulating systems including mixed triggers
US5784593A (en) * 1995-09-29 1998-07-21 Synopsys, Inc. Simulator including process levelization
FR2790887B1 (fr) * 1999-03-09 2003-01-03 Univ Joseph Fourier Circuit logique protege contre des perturbations transitoires
US7895560B2 (en) * 2006-10-02 2011-02-22 William Stuart Lovell Continuous flow instant logic binary circuitry actively structured by code-generated pass transistor interconnects

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1583545A (en) * 1976-08-04 1981-01-28 Martin Sanchez J Control systems
JPS5413883A (en) * 1977-07-04 1979-02-01 Hitachi Ltd Abnormalness detector of automatic controller
US4306286A (en) * 1979-06-29 1981-12-15 International Business Machines Corporation Logic simulation machine
DE3376592D1 (en) * 1982-07-13 1988-06-16 Nec Corp Logic simulator operable on level basis and on logic block basis on each level
JPS59154374A (ja) * 1983-02-23 1984-09-03 Fujitsu Ltd 論理シミユレ−シヨンの結果記録方式

Also Published As

Publication number Publication date
EP0099114A2 (fr) 1984-01-25
US4725975A (en) 1988-02-16
EP0099114A3 (en) 1986-01-29
DE3376592D1 (en) 1988-06-16

Similar Documents

Publication Publication Date Title
EP0099114B1 (fr) Simulateur logique pouvant opérer par base de niveaux et sur base de blocs logiques à chaque niveau
US4787061A (en) Dual delay mode pipelined logic simulator
CA1256563A (fr) Methode et appareil pour simuler les memoires dans une machine de simulation logique
EP0978124B1 (fr) Procede pour tester une memoire integree a l'aide d'un regisseur d'acces direct a la memoire integre
US4769817A (en) Concurrent fault simulation for logic designs
JP2916045B2 (ja) Ｆｉｆｏモジュール
EP0108346B1 (fr) Méthode de reconfiguration topographique de mémoire dans un système de traitement de données
EP0292206A1 (fr) Dispositif et méthode de mémoire auto-testante
JPH0122652B2 (fr)
EP0450839A2 (fr) Machine de simulation logique
JPH011042A (ja) ハードウェア・シミュレータ及びそのシミュレーション方法
US3737637A (en) Data generator
US5349686A (en) Method and circuit for programmably selecting a variable sequence of elements using write-back
US5353289A (en) Fault judging device comprising a compression circuit for compressing output pattern signals of a circuit model
JPH0345580B2 (fr)
US4814983A (en) Digital computer for implementing event driven simulation algorithm
US5689683A (en) Hardware simulator capable of dealing with a description of a functional level
CA1271259A (fr) Systeme simulateur
JPH04225475A (ja) ロジック・シミュレーション・マシン及び処理方法
JP2924968B2 (ja) 時間双方向シミュレーション装置
JPS6229824B2 (fr)
US5894581A (en) Method for reducing control store space in a VLSI central processor
JPS6221138B2 (fr)
JPS6235699B2 (fr)
JPS6244843A (ja) シミユレ−タ

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Designated state(s): DE FR GB IT

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Designated state(s): DE FR GB IT

17P Request for examination filed

Effective date: 19860318

17Q First examination report despatched

Effective date: 19870624

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB IT

REF Corresponds to:

Ref document number: 3376592

Country of ref document: DE

Date of ref document: 19880616

ET Fr: translation filed
ITF It: translation for a ep patent filed

Owner name: MODIANO & ASSOCIATI S.R.L.

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
ITTA It: last paid annual fee
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 19980703

Year of fee payment: 16

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 19980722

Year of fee payment: 16

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 19980929

Year of fee payment: 16

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19990712

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: THE PATENT HAS BEEN ANNULLED BY A DECISION OF A NATIONAL AUTHORITY

Effective date: 19990731

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 19990712

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20000503

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST