EP0065181B1 - Système d'identification électronique - Google Patents

Système d'identification électronique Download PDF

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Publication number
EP0065181B1
EP0065181B1 EP82103814A EP82103814A EP0065181B1 EP 0065181 B1 EP0065181 B1 EP 0065181B1 EP 82103814 A EP82103814 A EP 82103814A EP 82103814 A EP82103814 A EP 82103814A EP 0065181 B1 EP0065181 B1 EP 0065181B1
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EP
European Patent Office
Prior art keywords
key
pulses
lock
circuit
loading
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP82103814A
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German (de)
English (en)
French (fr)
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EP0065181A2 (fr
EP0065181A3 (en
Inventor
Alain Marie-Louis Mole
Jean-Louis Paul Jules Savoyet
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Individual
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Individual
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Publication date
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Priority to AT82103814T priority Critical patent/ATE36085T1/de
Publication of EP0065181A2 publication Critical patent/EP0065181A2/fr
Publication of EP0065181A3 publication Critical patent/EP0065181A3/fr
Application granted granted Critical
Publication of EP0065181B1 publication Critical patent/EP0065181B1/fr
Expired legal-status Critical Current

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    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07C—TIME OR ATTENDANCE REGISTERS; REGISTERING OR INDICATING THE WORKING OF MACHINES; GENERATING RANDOM NUMBERS; VOTING OR LOTTERY APPARATUS; ARRANGEMENTS, SYSTEMS OR APPARATUS FOR CHECKING NOT PROVIDED FOR ELSEWHERE
    • G07C9/00—Individual registration on entry or exit
    • G07C9/00174—Electronically operated locks; Circuits therefor; Nonmechanical keys therefor, e.g. passive or active electrical keys or other data carriers without mechanical keys
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
    • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
    • G07F7/086—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means by passive credit-cards adapted therefor, e.g. constructive particularities to avoid counterfeiting, e.g. by inclusion of a physical or chemical security-layer

Definitions

  • the present invention relates to an identification system, for example of a person, for the control of an electrical, mechanical or other device.
  • Systems of identification or recognition of people of this type have many applications. They are used in particular for opening doors, managing schedules, managing devices used by several people such as photocopying machines or even in systems for distributing banknotes by credit cards.
  • a removable part which includes an identification code and which is in the form of a badge in the form of a credit card which the person to be identified carries with it (see by example US patent 3,637,994).
  • the identification code is materialized in the badge either by perforations or by a magnetic strip.
  • the use of such badges has many drawbacks. They are indeed relatively bulky and can deteriorate easily. In the case of punched badges, the code is relatively easy to recognize.
  • the carrier of the identification code is magnetic, the magnetic tape can be damaged by scratches or under the influence of magnets.
  • the device used for reading badges of this type is necessarily complex and must in particular include a mechanical drive system enabling the badge to be moved in order to read the identification code. As a result, the reading devices have a high production cost.
  • a removable part is used in the form of an electronic key similar to a conventional key but comprising means for memorizing an identification code which can be detected and recognized by a system.
  • reading device similar to a lock but comprising a set of electronic circuits (see for example the American patent 4,038,637).
  • a programmable memory key system in which the identification code can be contained in a shift register housed in the electronic key.
  • the information contained in the key can be read by the electronic lock by means of pulses supplied by a clock located in said lock.
  • the information thus obtained is compared with a code stored in the lock so as to determine the identity of the two codes and the command, for example the opening of a strike or any other desired operation.
  • the present invention relates to an identification system which notably improves the security of the identification systems currently used and known and in which the mobile part analogous to a key is inert so that the simple reading of the shift register contained in the key does not allow simple identification of the identification code.
  • the invention also relates to such a system in which the process of loading the identification code into the memory of the key or the reading process, results in one or more modifications of the content of this memory, thus making any fraudulent duplication extremely difficult. .
  • the electronic identification system comprises a mobile part similar to an electronic key intended to cooperate, by electrical coupling, with a fixed part similar to an electronic lock.
  • the means for multiplexing the key are connected to the shift register of the key in order to cause an offset of the content of the memory which can be read each time that the means of counting the key have counted a number of preliminary loading pulses greater than one unit than the number of positions in the memory that can be read.
  • the memory that can be read from the mobile part comprises a parallel / serial shift register, the passive memory area preprogrammed in the mobile part comprising a plurality of switches whose position determines the electronic identification code. It will be understood that these switches can be simply produced by means of connections, for example fuses, some of which can be removed during the initial programming of the key.
  • Each flip-flop of the shift register of the mobile part is associated with one of the switches corresponding to a bit of the electronic code.
  • the various flip-flops are grouped into register elements each corresponding to one or more bits of the aforementioned code.
  • the mobile part comprises a counter associated with a multiplexer, the different outputs of which are connected to the different register elements corresponding to one or more bits of the aforementioned electronic code.
  • Another output of the multiplexer is connected to all of the flip-flops of the shift register of the mobile part so as to cause, when a signal is transmitted on said output, the simultaneous shift of one bit of the information in the shift register.
  • the aforementioned output for example the last output of the multiplexer, can also be directly connected to the first forcing inputs imposing a determined state on the first flip-flop of the shift register. In this way, said first flip-flop is forced into a state different from that corresponding to a bit of the electronic code preprogrammed in the mobile part.
  • the means for generating the charging pulses included in the fixed part or electronic lock comprise a charging circuit advantageously provided with a double flip-flop of the master-slave type associated with a NAND gate receiving clock pulses and supplying pulses loading.
  • the output of the charging circuit is connected to a charging modulation circuit provided with a counter associated with a monostable capable of acting on the charging circuit to cause it to stop after a determined number of charging pulses.
  • the electronic means included in the fixed part for reading the content of the shift register of the mobile part comprises a reading circuit advantageously provided with a double flip-flop of the master-slave type associated with a NAND gate receiving the clock pulses mentioned above and connected to the monostable output of the load modulation circuit.
  • the reading circuit is triggered after the emission of the determined number of loading pulses and provides successive pulses allowing the reading in series of the information contained in the parallel / serial shift register of the mobile part after this register has been loaded with the identification code and possibly after a determined modification of the content of the register by the action of a determined number of loading pulses.
  • a read stop circuit makes it possible to limit the number of clock pulses to the exact number of bits contained in the shift register of the mobile part.
  • This read stop circuit advantageously comprises a pulse counter receiving the read pulses from the read circuit and a monostable capable of delivering a read stop pulse when the number of pulses counted corresponds to the number of bits of the shift register, that is to say when the content of the shift register of the mobile part has been read once.
  • the memory which can be read, from the key is locked in on itself and the lock further comprises clock modulation means receiving the pulses emitted by the reading means and capable of supplying to the memory of the key a determined number of code modification pulses, different from a multiple of the number of bits of said memory, so as to cause each time a permutation of its content, a logical combination means blocking being provided in the lock or in the key to prevent any reading operation from the key until the predetermined number of code modification pulses has been emitted.
  • the mobile part comprises a normally open logic gate receiving the successive read pulses emitted by the read circuit of the fixed part and connected to the synchronization inputs or clock inputs of the flip-flops of the parallel / serial shift register. of the moving part.
  • the fixed part includes another logic gate connected to the input of a serial / parallel shift register of the fixed part so as to allow the information read to pass only after a determined number of read pulses.
  • the mobile part comprises control means for counting the determined number of successive read pulses and a logic gate connected to the output of the parallel / serial shift register of the mobile part and to the output of the control above in order to authorize the transfer of the content of the register of the mobile part to the series / parallel register of the fixed part only after the aforementioned determined number of read pulses causing the permutations.
  • the control means can for example comprise a set of counters associated with one or more logic gates.
  • the memory area of the mobile part preferably comprises a plurality of switches which can be produced for example in the form of fuses or by destroyable connections and the position of which determines the electronic identification code.
  • Each flip-flop of the shift register of the mobile part is associated with one of the switches whose position controls its state by means of two NAND gates receiving the loading pulse on one of their inputs.
  • the pre The above-mentioned NOT AND door is connected by its other input to the switch with which it is associated.
  • the second NAND gate receives the output of the first gate on its other input.
  • each flip-flop of the shift register is placed in a state corresponding to that of the switch with which it is associated.
  • the identification code initially represented by the position of the plurality of switches is transferred to the various flip-flops of the shift register.
  • the system can also comprise, in the fixed part, a circuit for authorizing successive tests.
  • This circuit comprises a succession of flip-flops, the resetting of which depends on the positive result of the comparison made by the comparison means with the code preprogrammed in the fixed part. In this way, a number of unsuccessful attempts is authorized equal to the number of flip-flops in this succession of flip-flops before triggering an alarm.
  • Suitable timing means can also be provided to reset all of the system's rockers to zero when the key is inserted and after uncoupling.
  • a so-called negative logic is used, that is to say for which we have adopted by convention level 1 for the ground potential and level 0 for the supply voltage which is preferably very low. of the order of + 5 volts.
  • level 1 for the ground potential
  • level 0 for the supply voltage which is preferably very low. of the order of + 5 volts.
  • the current demand remains limited to a few milliamps so as to avoid any danger for the user.
  • the identification system of the invention comprises a removable transportable part or electronic key shown in FIG. 2 and a fixed part or electronic lock shown in FIG. 1.
  • the removable part is presented like a classic key. It can advantageously consist of a glass fiber plate sandwiched by two thicknesses of hard plastic resistant well to solvents and to extreme temperatures.
  • the electronic key is therefore very resistant and its wear negligible in particular compared to that of a badge of the conventional type.
  • the electronic key comprises a certain number of electrical contacts constituted by conductive elements embedded in the plastic material cooperating on the side of the fixed part playing the role of electronic lock, with steel balls held by springs not illustrated in the figures. It is also possible to envisage making these contacts in another way, for example by opto-electronic link.
  • the electronic key shown diagrammatically comprises a parallel / serial shift register referenced 9 as a whole controlled by a succession of twenty four switches 10 whose open or closed position defines all the bits of the identification code.
  • the switches 10 can for example be constituted by connections, a part of which was initially destroyed so as to cut the electronic link between the two terminals.
  • the key shown in fig. 2 comprises a certain number of terminals intended to come into contact with corresponding terminals of the electronic lock when the key is coupled with the latter. Only the main terminals of the key have been shown in fig. 2
  • the terminals 11 and 12 connected together in the key by a link not shown are intended to be connected to the system ground (T).
  • the terminal L referenced 13 is intended to receive a succession of pulses for loading the code contained in the set of switches 10 into the register 9.
  • the terminal H referenced 14 is intended to receive a succession of pulses allowing the reading information contained in the shift register 9.
  • the terminals A referenced 15 and 16 connected together in the key by a link not shown are intended to be connected to the electric current supply located in the lock.
  • the output terminal S referenced 17 is connected to the output Q of the shift register 9.
  • the electronic key is passive and does not include a power source. As long as it is not coupled to the lock, the shift register 9 contains no information and its reading therefore cannot provide the identification code.
  • the electronic lock illustrated in fig. 1 comprises a charging circuit referenced 18 as a whole, the input of which is connected to the terminal 12 when the key is coupled with the lock, i.e. with the earth of the system and the output of which provides charging pulses on terminal L.
  • the output of the charging circuit 18 is also connected by the connection 18a to the input of a loading modulation circuit 19.
  • An output of the circuit 19 is connected by the connection 19a to the input of a reading circuit referenced 20 as a whole and supplying on terminal H a succession of clock pulses or read pulses.
  • Another output of the circuit 19 is connected by the connection 19b to the charging circuit 18 in order to stop the emission of the charging pulses after a determined number of pulses.
  • the output of the read circuit 20 is further connected by the connection 22 to the input of a read stop circuit referenced 23 as a whole, the output of which returns via the connection 24 to the read circuit 20 in order to deliver a read stop pulse stopping the emission of clock pulses on terminal H when the content of the shift register 9 has been read once, that is to say when a total number of twenty four pulses are appeared on terminal H.
  • the terminal S connected to the output Q of the shift register 9 receives the serial signal representing the information contained in the shift register 9.
  • the terminal S is connected to the input E of a circuit 25 performing a serial / parallel conversion and a comparison of the information read from the key with an identification code preprogrammed in the electronic lock itself and constituted in the example illustrated in the form of a set of switches 26 preprogrammed.
  • the electronic lock further comprises in the example illustrated a circuit for authorizing successive tests 27 connected by an output connection 28 to an alarm device which is actuated after four successive unsuccessful tests.
  • a circuit 29 connected to the terminals A of the key makes it possible to stabilize the supply at + 5 volts.
  • a first reset circuit 30 causes all of the flip-flops and counters of the electronic key system to be reset to zero when the key is coupled to the lock.
  • a second reset circuit 31 causes all of the flip-flops and counters to be reset to zero and the supply cut off when the key is uncoupled.
  • a strike control circuit 32 receives a signal when the comparison made in circuit 25 is positive.
  • the loading circuit 18 comprises a double master-slave flip-flop constituted by a first flip-flop 33 or “master” and a second flip-flop 34 “slave •.
  • the two flip-flops 33, 34 are connected to each other in a conventional manner, the second flip-flop 34 receiving on its input T the clock signal coming from the clock circuit 21.
  • the output Q of flip-flop 34 is connected to one of the NAND gate 35 inputs further receiving on its second input the clock signal.
  • the input t of the first flip-flop 33 is connected via the two timers 36 and 37 to the ground of the system via terminal 12 connected to terminal T when the key is coupled to the lock. Under these conditions, the system therefore works well in negative logic.
  • the read circuit 20 is of the same type as the loading circuit 18 and it includes, like the latter, a double master-slave flip-flop 38, 39 mounted in the same way.
  • the input T of the first flip-flop 38 receives an output pulse from the load modulation circuit 19.
  • the output of the NAND gate 41 is connected by the connection 22 to the read stop circuit 23 which includes a counter 42 whose outputs Q A , Q B , Q c and Q D are connected to the input of a NAND gate 42a.
  • the output of door 42a is connected to the input A of a monostable 43.
  • the output pulses of the NAND gate 41 or clock pulses appearing on the terminal H transmitted by the connection 22 to the input H of the counter 42 are counted until reaching the corresponding number of twenty four in the example illustrated in the number of bits of the shift register 9 of the key, that is to say in the number of switches 10.
  • the output Q of the monostable 43 delivers an output signal applied by the connection 24 to the the forcing input R of the first flip-flop 38 of the read circuit 20 resetting the latter to zero and thereby stopping the clock pulses emitted by the circuit 20.
  • serial signal appearing on the terminal S and representing the content of the register 9 feeds the input E of a serial / parallel converter comprising three serial / parallel shift registers 45a, 45b and 45c included in the conversion and comparison circuit 25
  • clock pulses or read pulses are also applied by the connections 46a, 46b and 46c as well as the inverter 46d at the inputs H of the three registers 45a, 45b and 45c.
  • the comparison code preprogrammed in the fixed part or lock, materialized by the position of the switches 26, is compared with the result of the series / parallel conversion in the circuit comparator comprising the six comparators 47a, 47b, 47c, 47d, 47e and 47f, connected in series and connected by a part to the different parallel outputs of the three conversion registers 45a, 45b and 45c and on the other hand to the different switches 26 grouped by four for each of the comparators 47a to 47f.
  • the result of the comparison, coming from the last element 47f is a “zero or“ one ”signal depending on whether the comparison is negative or positive.
  • the result of this comparison appearing on the connection 51 is applied to the input D of the flip-flop 52 receiving further on its input T by the connection 53 the output signal of the read stop circuit 23.
  • a signal is emitted by the output Q of the flip-flop 52 and transmitted by the connection 54 via the amplifier 55 to the relay 56 closing the switch 57 of the door release control circuit 32.
  • the signal emitted by the output Q of the flip-flop 52 is transmitted by the connection 58 to the NAND gate 59 whose output is connected by the inverter 59a to the reset reset inputs R of the three flip-flops 60, 61 and 62 of the successive test authorization circuit 27 connected in cascade and connected to the alarm control 28.
  • the input T of the first flip-flop 60 receives the output signal from the read stop circuit 23 through connection 63.
  • the power supply stabilization circuit 29 comprises an input terminal 64 connected to the supply battery, for example + 5 volts contained in the electronic lock but not shown in the figure.
  • the two terminals 15 and 16 intended to cooperate with the corresponding terminals of the key are connected via the capacitor 65 and the diode 66.
  • the electronic lock further comprises in the first reset circuit 30 a monostable 70 receiving on its input A by connection 71 the output signal of the timer 36. Under these conditions, the monostable 70 reacts to a signal having a falling edge on connection 71, that is to say when the key is coupled.
  • the output Q of the flip-flop 70 is connected by the link 72 to one of the inputs of the NAND gate 73.
  • the output signal of the NAND gate 73 allows via the inverter 74 and by the connections 75, 76a, 76b and 76c to reset to zero by their forcing inputs R of the three registers 45a, 45b and 45c of the series / parallel conversion circuit 25.
  • the output Q of the flip-flop 70 is also connected by the connection 78 at one of the inputs of the NAND gate 79 receiving on its other input the output signal of the read stop circuit 23.
  • the output of the NAND gate 79 resets to zero, by connection 79a, the counter 42.
  • the reset circuit 31 at the end of reading when the key is removed comprises two monostables 80 and 81 connected in cascade, the output Q of the monostable 80 being connected to the input A of the monostable 81.
  • the first monostable 80 receives on its input B via connection 82 the output signal of timer 37 and reacts, taking into account this arrangement, on a signal having a rising edge on connection 82, that is to say during uncoupling of the key.
  • the output to of the second monostable 81 which provides a very short pulse is connected by the connection 83 to the second input of the NAND gate 73 which causes, as we have seen previously, the resetting of the conversion circuit series / parallel 25.
  • the Q output of monostable 81 is also connected by connection 84 to one of the inputs of NAND gate 59 so as to reset flip-flops 60, 61 and 62 of the test authorization circuit successive 27 when the key is uncoupled.
  • the rising edge signal on the connection 82 at the output of the timer 37 applied via the inverter 85 to the input T of the flip-flop 86 causes, via the amplifier 87 connected to its output Q, triggering of the relay 68 of the supply circuit 29 so that the supply is cut off.
  • the flip-flop 86 is reset to zero by its input R via the connection 84a connected to the output of the monostable 81 when the key is uncoupled from the lock.
  • the NAND gate 88 receives on its two inputs respectively the output signal from the NAND gate 73 via the inverter 74 and the connection 75 and the output signal from the inverter 85 via the connection 89.
  • the output signal from the NAND gate 88 allows the flip-flop 52 to be reset to zero by its input R by means of the connection 90 and the inverter 91 at the time of uncoupling of the key after the expiration of the timer delay time 37.
  • FIG. 3 The detailed structure of the shift register 9 of the key and of the set of switches 10 playing the role of preprogrammed memory is partially illustrated in FIG. 3.
  • the switch 10a is shown open which, in the negative logic chosen by way of example for the circuit of FIG. 2, corresponds to a “one • signal.
  • the switch 10b connected to earth is shown closed, which corresponds to a "zero " signal.
  • the other switches have not been shown on the fig. 3.
  • This figure also shows the first two flip-flops 92a and 92b corresponding to the first two bits of the shift register 9 and which receive on their inputs H the clock signals or read pulses from the read circuit 20 of the lock by the connection 117 also illustrated in FIG. 2.
  • the different flip-flops 92a, 92b, etc ... are connected together in a cascade in a conventional manner, the outputs Q and Q of each upstream flip-flop being connected to the inputs S and R of the flip-flop immediately following so as to produce the register shift 9.
  • Two NAND gates 95a and 96a are associated with the flip-flop 92a, the outputs of the two NAND gates being connected respectively to the input P placing the flip-flop 92a in the "one" state and to the input R placing the flip-flop 92a in the "zero" state.
  • the first NAND gate 95a is connected by its first input via the connection 97a to the switch 10a and by its second input via the connection 98a at the output of the inverter 99 receiving the loading pulse corresponding to the register element 9a by the connection 112a also visible in FIG. 2.
  • the output of the inverter 99 is also connected by the connection 100a to one of the inputs of the NAND gate 96a which receives on its other input by the connection 101a the output of the NAND gate 95a.
  • the same elements assigned the reference "b are associated with the flip-flop 92b and the switch 10b. The same elements are also found for each following flip-flop corresponding to each bit of the shift register 9.
  • the different elements 9a to 9f have a similar structure and are mounted as illustrated in FIG. 2.
  • a signal “one is applied to input 97a of the NAND gate 95a.
  • the negative charging pulse causes the presence of a signal “one on the second input 98a which causes a signal” zero “at the output of the NAND gate 95a.
  • Examination of the circuit associated with the flip-flop 92b shows that the closed position of the switch 10b causes for the flip-flop 92b a state opposite to that of the flip-flop 92a.
  • the appearance of a loading pulse on the connection 112a causes the transfer of four bits of the identification code materialized by the position of the first four switches 10 in the form of the state of the different flip-flops 92a to 92d which can then be read in series by the clock signals applied to the inputs H.
  • all the flip-flops remain in the zero state in the example illustrated.
  • the forcing inputs S and R of the first flip-flop 92a are also connected via the inverters 102 and 103 to the connection 113 also visible in FIG. 2.
  • the load modulation circuit 19 comprises a counter 104 receiving on its input H the load pulses emitted by the load circuit 18 and connected by its outputs Q A , Q B , O c and Q o to a group of four switches 105 connected to the four inputs of a NAND gate 106.
  • the output of gate 106 is connected to the input ⁇ of the monostable 107 whose output Q is connected by connection 19a to the input of the circuit of reading 20.
  • the output Q of the monostable 107 is connected by the connection 19b to the reset input R of the first flip-flop 33 of the charging circuit 18.
  • the counter 104 is reset to zero by the output signal emitted by the Q output of monostable 107 by means of connection 108.
  • the shift register 9 is subdivided into six elements 9a, 9b, 9c, 9d, 9e and 9f.
  • Each of the elements 9a to 9f is shown diagrammatically in FIG. 2 and actually comprises six sets of rockers and NAND gates such as those shown in FIG. 3, each of these rockers cooperating with one of the switches 10. Under these conditions, each of the elements of the shift register 9 cooperates with four switches 10.
  • the loading inputs referenced L of each of the elements 9a to 9f are respectively connected to the outputs numbered 1 to 6 of the multiplexer 111 via the connections 112a to 112f.
  • an output signal on one of the outputs of the multiplexer 111 causes the loading of a single element of the shift register 9, that is to say of four bits of the identification code represented by the position of all switches 10.
  • the output number 7 of the multiplexer 111 is connected by the connection 113 to the input E forcing the first element 9a of the shift register 9 as illustrated in detail in FIG. 3. Furthermore, the output signal emitted by the output number 7 of the multiplexer 111 is also transmitted by the connection 114 to one of the inputs of the AND gate 115, the other input of which is connected by the connection 116 to the terminal. H receiving the clock pulses or read pulses emitted by the read circuit 20 of the lock. The output of the AND gate 115 is connected by the connection 117 to all the clock inputs H of the various elements of the shift register 9 these inputs being connected to the inputs of all the flip-flops 92 as illustrated in FIG. 3.
  • the output Q of the last element 9f is connected by connection 118 to the output terminal S.
  • the counter 110 is reset to zero when the key is withdrawn via the inverter 119 connected to the power supply by the resistor 120 and the capacitor 121 and constituting a Schmidt rocker.
  • the illustrated system works as follows. When the key is inserted into the electronic lock, the entire system is switched on, the two terminals 15 and 16 being short-circuited.
  • the clock circuit 21 located in the lock emits successive pulses. After a certain time determined by the timer 36 a falling edge signal causes the monostable 70 a reset pulse of the various elements of the lock.
  • the output of the second timer 37 delivers a falling edge signal which causes, after a second delay, the start of the emission by the loading circuit 18 of negative loading pulses.
  • the loading pulses emitted by the circuit 18 are also applied to the input of the counter 104 located in the loading modulation circuit 19 of the lock. Depending on the predetermined position of the switches 105, it is therefore possible to cause the emission of a determined number of charging pulses. In fact, as soon as this number, determined by the position of the various switches 105, has been reached, a signal is emitted by the NAND gate 106 and by the monostable 107 which causes the charging circuit to stop via of connection 19b.
  • the various switches 105 can be placed so that the number of charging pulses emitted by the circuit 18 is six. Under these conditions, the six charging pulses effectively make it possible to charge all of the twenty four switches 10 grouped by four.
  • a seventh pulse appearing on the output number 7 of the multiplexer 111 causes by the connection 113 a shift of one bit of the content of the shift register 9. It will be noted that for seven pulses, the logic gate 115 is blocked by the signal “zero appearing on the output number 7 counts given the use of negative logic, so that the signal from terminal H cannot pass through gate 115 preventing any reading of the content of shift register 9.
  • the shift register containing either the initial identification code or a code modified in a predetermined manner the output signal of the loading modulation circuit 19 coming from the outputs Q and Q of the monostable 107 causes both the charging pulses to stop and the start of the emission of clock pulses or read pulses by the read circuit 20.
  • These pulses appearing on the terminal H allow by l through the AND gate 115, the serial reading of the content of the various elements 9a to 9f of the parallel / serial shift register 9 of the key.
  • the read pulses are counted by the read stop circuit 23 so as to be equal in the example illustrated to twenty four, that is to say to the number of bits of the shift register 9.
  • serial signal appearing on terminal S and applied to the serial / parallel shift registers 45a to 45c is compared in the comparators 47a to 47f with the preprogrammed code materialized by the switches 26.
  • the fixed part or electronic lock further comprises a clock modulation circuit 122 and the shift register 9 of the mobile part or electronic key illustrated in FIG. 5 is looped back on itself, the output Q of the last element 9f being connected by the connection 123 to the forcing input E of the first element 9a.
  • the clock modulation circuit 122 comprises a set of three counters 124, 125 and 126.
  • the first counter 124 receives on its input H the clock pulses or read pulses emitted by the read circuit 20.
  • switches 124a which can be preprogrammed define by their positions a determined number and are connected to the outputs Q A , Q B , Q c and Q ⁇ of the counter 124.
  • the second counter 125 receives on its input H the output QD of the first counter 124. It is also associated with four switches 125a whose position also defines a determined number and which are connected to the outputs Q A , Q B , Q c and Q D of the counter 125.
  • a NAND gate 127 receives on its various inputs all of the connections from the eight switches 124a and 125a.
  • the output of the gate 127 is connected by the connection 128 to the input of the third counter 126 which is also associated with four switches 126a as is the case for the two counters 124 and 125.
  • the connections of the four switches 126a are connected at the entrances of a NAND gate 129.
  • the output of the gate 129 emits a signal after the emission of a number of clock pulses or read pulses by the circuit 20 which depends on the position of the different switches 124a , 125a and 126a.
  • the number defined by the first two counters 124 and 125 corresponds to the number of read pulses within a cycle.
  • the number defined by the counter 126 corresponds to the number of cycles.
  • the total number defined by the entire modulation circuit 122 is the product of these two numbers. Of course, other means could be used for this counting.
  • the output of the NAND gate 127 is also connected by the connection 130 to the input A of the monostable 131 whose output Q is connected by the connection 132 to one of the inputs of the NAND gate. 133 causing the counters 124 and 125 to be reset to zero by their inputs R when a signal is sent by the NAND gate 127. Thus, the first two counters 124 and 125 are reset to zero after each of the cycles counted by the third counter 126.
  • the output signal of the NAND gate 129 transmitted by the inverter 134 appears by the connection 135 on the first input of the AND gate 136, the second input of which is connected to the input terminal E which receives the output signal from register 9 of the key. In this way, the content of said register can only be introduced into the comparison circuit 25 after the emission of the number of read pulses determined by the clock modulation circuit 122.
  • NAND gate 129 The output of NAND gate 129 is also connected to one of the inputs of a NAND gate 137 which receives on its second input by connection 138 the clock pulses emitted by the read circuit 20.
  • the operation of the identification system illustrated in figs. 4 and 5 is as follows.
  • the loading of the identification code materialized by the position of the various switches 10 in the shift register 9 of the key is done as in the previous embodiment by means of a determined number of loading pulses emitted by the circuit of load 18 whose number is determined by the load modulation circuit 19 and which are transmitted by the multiplexer 111 to the different elements 9a to 9f of the register 9. It will however be noted that in the assembly illustrated in FIG. 5, none link is not provided between the output number 7 of the multiplexer 111 and the input E of the shift register 9.
  • the modification of the identification code contained in the shift register 9 during the emission of a signal on the output number 7 of the multiplexer 111 is done only through the AND gate 115 whose output is connected by the connection 117 to the different clock inputs H of the flip-flops of the shift register 9 looped back on itself .
  • Such a one bit shift causes the content of the shift register 9 to be swapped.
  • the reading circuit 20 of the lock is switched on and a number of clock pulses determined by the three counters 124, 125 and 126 is sent to terminal H
  • Each of these pulses causes a permutation of the content of the shift register 9 of the key via the AND gate 115. It should be noted that during these different permutations the signal appearing on the output terminal S n ' is not introduced into the comparison circuit 25 taking into account the existence of the AND gate 136 which blocks the input as long as no signal is emitted at the output of the NAND gate 129.
  • the AND gate 136 receiving the signal from the NAND gate 129, lets pass read pulses equal in number to the number of bits of the shift register 9 in order to read its content. This number is determined by the read stop circuit 23 as before.
  • the comparison is made with respect to a predetermined state of the various switches 26 of the lock. Only the lock is capable of knowing the code modified after the successive permutations caused by the clock modulation circuit 122.
  • the reset of the counter 104 of the load modulation circuit 19 is done directly by the connection 144 connected to the output Q of the monostable 70.
  • the output Q of the monostable 70 which resets to zero at the start of operation by the connection 145, the counter 126, the counter 42 and by the reverser 146 the flip-flop 140.
  • FIGS. 6 and 7 illustrate this possibility for the case of a sixteen-bit code.
  • the sixteen flip-flops constituting the shift register 9 are shown, each of them being associated with one of the switches 10.
  • the multiplexer 111 has eight outputs each connected to a pair of flip-flops in the register 9 by their inputs L by means of the various connections 112.
  • the last numbered output 9 is connected to all of the inputs H of the various flip-flops via the connection 114 and the AND gate 115 which receives on its second input by connection 116 the clock or read pulses coming from terminal H.
  • the output number 9 of the multiplexer 111 is also connected by the connection 113 to one of the inputs of an AND gate 146, the other input of which is connected by the link 147 to the output Q of the shift register 9.
  • the output of the AND gate 146 is connected by connection 148 to the forcing input E of the first flip-flop of the shift register 9.
  • the key further comprises a circuit for controlling the number of clock pulses analogous to the clock modulation circuit 122 of the lock.
  • the control circuit 149 comprises three counters 150, 151 and 152.
  • the first two counters 150 and 151 each associated with four programming switches 150a and 151a, supply a NAND gate 153 which is connected to its output by connection 154 to the input of the third counter 152.
  • the latter is associated with four programming switches 152a connected to the four inputs of an AND gate 155.
  • the output of the AND gate 155 is connected by connection 156 to one of the inputs an AND gate 157, the second input of which is connected by connection 158 to the output Q of the shift register 9.
  • the output of the AND gate 157 is connected to the output terminal S.
  • the system illustrated in figs. 6 and 7 works as follows. After the coupling operation of the key and the lock, the loading is done as previously, for example according to the embodiment illustrated in FIGS. 1 and 2. It is appropriate here that the loading circuit 18 emits a number of at least one loading pulse so that all of the flip-flops of the shift register 9 of the key are loaded by the information contained in the switches 10. If this exact number of charging pulses is transmitted, the AND gate 115 remains open, so that the reading pulses or clock pulses originating from terminal H can pass through this gate and cause the information contained in the register 9 by action on the various inputs H of the flip-flops.
  • clock pulses in a number also determined by the clock modulation circuit 122 appear on terminal H.
  • the control circuit 149 of the key receives these pulses by connection 149a and counting the number, it should be noted in this connection that the programming of the control circuit 149 by means of the three groups of switches 150a, 151a and 152a is of course the same as that of the circuit of clock modulation 122 of the lock depending on the position of the three groups of switches 124a, 125a and 126a.
  • the two counters 150 and 151 of the control circuit 149 play the same role as the two counters 124 and 125 of the clock modulation circuit 122 and count the number of clock pulses in a cycle.
  • the third counter 152 of the control circuit 149 plays the same role as the third counter 126 of the clock modulation circuit 122 and counts the number of cycles.
  • Each clock pulse transmitted by the AND gate 115 open in the absence of a signal on the output number 9 of the multiplexer 111 causes a shift of one bit of the content of the shift register 9 and a permutation of this content due to the loopback by connection 147.
  • the AND gate 157 remains blocked so that the information contained in the shift register 9 is not transmitted to the terminal S and to the comparison circuit 25 of the lock.
  • the number of pulses determined by the first two counters 124 and 125 of the circuit 122 and verified by the first two counters 150 and 151 of the control circuit 149 is greater than the number of bits of the shift register 9. De in this way, the reading pulses appearing on the terminal H after the various permutations effectively allow the reading of the entire content of the shift register 9 without the gate 157 being blocked by an absence of signal on the AND gate 155.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Lock And Its Accessories (AREA)
  • Storage Device Security (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Control Of Vending Devices And Auxiliary Devices For Vending Devices (AREA)
  • Preparation Of Compounds By Using Micro-Organisms (AREA)
  • Non-Silver Salt Photosensitive Materials And Non-Silver Salt Photography (AREA)
  • Burglar Alarm Systems (AREA)
  • Cash Registers Or Receiving Machines (AREA)
  • Testing Of Coins (AREA)
EP82103814A 1981-05-12 1982-05-04 Système d'identification électronique Expired EP0065181B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT82103814T ATE36085T1 (de) 1981-05-12 1982-05-04 Verfahren zur elektronischen identifikation.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8109453 1981-05-12
FR8109453A FR2506048B1 (fr) 1981-05-12 1981-05-12 Systeme d'identification electronique

Publications (3)

Publication Number Publication Date
EP0065181A2 EP0065181A2 (fr) 1982-11-24
EP0065181A3 EP0065181A3 (en) 1983-04-06
EP0065181B1 true EP0065181B1 (fr) 1988-07-27

Family

ID=9258358

Family Applications (1)

Application Number Title Priority Date Filing Date
EP82103814A Expired EP0065181B1 (fr) 1981-05-12 1982-05-04 Système d'identification électronique

Country Status (8)

Country Link
US (1) US4481513A (ja)
EP (1) EP0065181B1 (ja)
JP (1) JPS5824073A (ja)
AT (1) ATE36085T1 (ja)
CA (1) CA1187992A (ja)
DE (1) DE3278830D1 (ja)
ES (1) ES512059A0 (ja)
FR (1) FR2506048B1 (ja)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4525713A (en) * 1983-03-01 1985-06-25 Lockheed Electronics Co., Inc. Electronic tag identification system
ES8502795A1 (es) * 1983-05-11 1985-01-16 Savoyet Jean L Dispositivo de identificacion electronica
JPH0817416B2 (ja) * 1987-05-22 1996-02-21 日本電気株式会社 ダイヤルパルス歪補正方法
US5369401A (en) * 1989-03-23 1994-11-29 F.M.E. Corporation Remote meter operation
ES2080633B1 (es) * 1992-01-27 1996-10-16 Santacruz Domingo Pena Sistema de cerradura.
CN104966480B (zh) * 2015-07-21 2017-08-25 京东方科技集团股份有限公司 阵列基板行驱动电路单元、驱动电路和显示面板
US11507310B2 (en) 2019-09-02 2022-11-22 SK Hynix Inc. Memory controller and operating method thereof
KR20210061174A (ko) 2019-11-19 2021-05-27 에스케이하이닉스 주식회사 메모리 컨트롤러 및 그 동작 방법
US11501808B2 (en) 2019-09-02 2022-11-15 SK Hynix Inc. Memory controller and operating method thereof

Citations (1)

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FR2136269A5 (ja) * 1971-04-09 1972-12-22 Eastern Co

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US3859634A (en) * 1971-04-09 1975-01-07 Little Inc A Digital lock system having electronic key card
CA1004362A (en) * 1972-04-11 1977-01-25 Gretag Aktiengesellschaft System for the individual identification of a plurality of individuals
US3911397A (en) * 1972-10-24 1975-10-07 Information Identification Inc Access control assembly
US3872435A (en) * 1973-05-18 1975-03-18 Victor L Cestaro Opto-electronic security system
US3944976A (en) * 1974-08-09 1976-03-16 Rode France Electronic security apparatus
JPS5231632A (en) * 1975-08-14 1977-03-10 Matsushita Electric Ind Co Ltd Selling amount memory unit
US4031434A (en) * 1975-12-29 1977-06-21 The Eastern Company Keyhole-less electronic lock
FR2394131A1 (fr) * 1977-06-07 1979-01-05 Cii Honeywell Bull Systeme de traitement d'informations protegeant le secret d'informations confidentielles
DE3162790D1 (en) * 1980-07-01 1984-04-26 Scovill Inc Electronic security device
US4353064A (en) * 1981-01-14 1982-10-05 Honeywell Inc. Battery operated access control card

Patent Citations (1)

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Publication number Priority date Publication date Assignee Title
FR2136269A5 (ja) * 1971-04-09 1972-12-22 Eastern Co

Also Published As

Publication number Publication date
JPS5824073A (ja) 1983-02-12
FR2506048A1 (fr) 1982-11-19
CA1187992A (fr) 1985-05-28
US4481513A (en) 1984-11-06
ES8304345A1 (es) 1983-02-16
FR2506048B1 (fr) 1986-02-07
EP0065181A2 (fr) 1982-11-24
ATE36085T1 (de) 1988-08-15
JPH0418355B2 (ja) 1992-03-27
EP0065181A3 (en) 1983-04-06
DE3278830D1 (en) 1988-09-01
ES512059A0 (es) 1983-02-16

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