EP0065181B1 - System for electronic identification - Google Patents

Abstract

The indentification system consists of a key comprising a passive memory area (10) and a shift register (9) and a lock which can be coupled with the key. The lock is capable of supplying a set number of pulses causing the code contained in the memory (10) to be loaded into the register (9). The register (9) is subdivided into a certain number of elements linked together but loaded independently. This loading is carried out successively by the multiplexer (111). Transmission of an incorrect number of loading pulses leads, through connection (113), to a modification of the contents of the shift register (9).

Description

The present invention relates to an identification system, for example of a person, for the control of an electrical, mechanical or other device. Systems of identification or recognition of people of this type have many applications. They are used in particular for opening doors, managing schedules, managing devices used by several people such as photocopying machines or even in systems for distributing banknotes by credit cards.

In certain identification systems of the conventional type, a removable part is used which includes an identification code and which is in the form of a badge in the form of a credit card which the person to be identified carries with it (see by example US patent 3,637,994). The identification code is materialized in the badge either by perforations or by a magnetic strip. The use of such badges has many drawbacks. They are indeed relatively bulky and can deteriorate easily. In the case of punched badges, the code is relatively easy to recognize. When the carrier of the identification code is magnetic, the magnetic tape can be damaged by scratches or under the influence of magnets. Furthermore, the device used for reading badges of this type is necessarily complex and must in particular include a mechanical drive system enabling the badge to be moved in order to read the identification code. As a result, the reading devices have a high production cost.

In other identification systems, a removable part is used in the form of an electronic key similar to a conventional key but comprising means for memorizing an identification code which can be detected and recognized by a system. reading device similar to a lock but comprising a set of electronic circuits (see for example the American patent 4,038,637).

In French patent 2,363,837, a programmable memory key system is used in which the identification code can be contained in a shift register housed in the electronic key. The information contained in the key can be read by the electronic lock by means of pulses supplied by a clock located in said lock. The information thus obtained is compared with a code stored in the lock so as to determine the identity of the two codes and the command, for example the opening of a strike or any other desired operation.

In this system, however, the risk is great of a fraudulent duplication of the electronic key, the reading of the shift register allowing the determination of the identification code is relatively easy for a technician familiar with this type of device.

In patent US-3,859,634 and the corresponding French patent FR-2,136,269 is further described an electronic device comprising a lock and a key. The key contains a two-part code in passive ROM-type memory. A first part of this code allows the recognition of the key by comparison with an authorization code issued by the lock. In the case where the comparison is positive, the read operation can be triggered and the second part of the code is then transmitted towards the lock, possibly under the control of an encoder device. The code thus transferred is then compared in the lock with a reference code stored in the lock. When this second comparison is positive, the lock controls the opening of the door which it protects.

The present invention relates to an identification system which notably improves the security of the identification systems currently used and known and in which the mobile part analogous to a key is inert so that the simple reading of the shift register contained in the key does not allow simple identification of the identification code. The invention also relates to such a system in which the process of loading the identification code into the memory of the key or the reading process, results in one or more modifications of the content of this memory, thus making any fraudulent duplication extremely difficult. .

The electronic identification system according to the invention comprises a mobile part similar to an electronic key intended to cooperate, by electrical coupling, with a fixed part similar to an electronic lock.

• - des moyens de couplage électrique avec la serrure destinés à assurer l'alimentation électrique de la clé et la transmission de signaux de données entre la clé et la serrure ;
• - une mémoire morte programmable ou reprogrammable comportant une pluralité de positions ou bits de mémoire dont l'état définit un code électronique d'identification, lequel ne peut pas être lu tant qu'il reste enregistré uniquement dans ladite mémoire morte,
• - une mémoire pouvant être lue, du type registre à décalage, connectée en parallèle bit à bit avec ladite mémoire morte pour recevoir ledit code d'identification programmé enregistré dans cette dernière, et constituée d'une pluralité d'éléments à décalage à une ou plusieurs positions de mémoire reliés entre eux, chacun de ces éléments, par exemple constitué par une bascule, étant pourvu d'une entrée indépendante de commande de chargement permettant un chargement indépendant et sélectif ;
• - des moyens de comptage de multiplexage et de combinaison logique destinés à coopérer avec la serrure lorsque la clé est couplée électriquement avec cette dernière ;
• - des moyens pour faire en sorte qu'en l'absence de couplage électrique entre la clé et la serrure ou après interruption de ce couplage, la mémoire pouvant être lue ne contienne pas ledit code préprogrammé dans la mémoire morte.

The electronic key is passive in nature and includes:

• - means of electrical coupling with the lock intended to ensure the electrical supply of the key and the transmission of data signals between the key and the lock;
• - a programmable or reprogrammable read-only memory comprising a plurality of memory positions or bits whose state defines an electronic identification code, which cannot be read as long as it remains recorded only in said read-only memory,
• - a readable memory, of the shift register type, connected in parallel bit by bit with said read-only memory to receive said programmed identification code recorded in the latter, and made up of a plurality of shift elements at one or several memory positions linked together, each of these elements, for example constituted by a rocker, being provided with an independent loading control input allowing independent and selective loading;
• - multiplexing counting means and logic combination intended to cooperate with the lock when the key is electrically coupled with the latter;
• - Means for ensuring that in the absence of electrical coupling between the key and the lock or after interruption of this coupling, the memory that can be read does not contain said code preprogrammed in the read-only memory.

• - des moyens d'alimentation électrique capables également d'alimenter la clé lorsqu'elle est couplée électriquement à la serrure ;
• - des moyens de modulation de chargement pour fournir à la clé après couplage un nombre prédéterminé d'impulsions préliminaires de chargement destinées à produire le chargement indépendant et sélectif d'au moins certains des éléments à décalage constituant la mémoire pouvant être lue avec le contenu des positions de la mémoire morte qui sont reliées à ces éléments à décalage, le code d'identification se trouvant ainsi transféré dans la mémoire pouvant être lue, après une éventuelle modification lorsque le nombre d'impulsions de chargement est différent du nombre d'éléments à décalage ;
• - des moyens de lecture reliés aux moyens de modulation de chargement pour fournir à la clé, après l'émission des impulsions de chargement, une succession d'impulsions de lecture dont le nombre est égal au nombre total des positions de mémoire de la mémoire pouvant être lue afin de transférer en série le contenu de la mémoire pouvant être lue vers la serrure ;
• - des moyens pour mémoriser en série le code d'identification ainsi transféré depuis la clé après une éventuelle modification ;
• - des moyens programmables ou repro- grammables de mémorisation d'un code de référence ayant le même nombre de bits que le code d'identification enregistré dans la clé ;
• - des moyens pour comparer bit à bit le code de référence avec le code d'identification transféré et éventuellement modifié ;
• - des moyens de décision réagissant au résultat de ladite comparaison ;
• - ledit nombre prédéterminé d'impulsions préliminaires de chargement étant tel que le code d'identification transféré de la clé vers la serrure, après éventuelle modification, corresponde au code de référence mémorisé dans la serrure.

The electronic lock includes:

• - Power supply means also capable of supplying the key when it is electrically coupled to the lock;
• loading modulation means for supplying to the key after coupling a predetermined number of preliminary loading pulses intended to produce the independent and selective loading of at least some of the shift elements constituting the memory that can be read with the content of the read-only memory positions which are connected to these shifted elements, the identification code thus being transferred into the memory which can be read, after a possible modification when the number of loading pulses is different from the number of elements to be shift;
• reading means connected to the loading modulation means for supplying the key, after the emission of the loading pulses, a succession of read pulses the number of which is equal to the total number of memory positions of the memory which can be read in order to transfer the contents of the readable memory to the lock in series;
• - Means for storing in series the identification code thus transferred from the key after a possible modification;
• - programmable or reprogrammable means for memorizing a reference code having the same number of bits as the identification code recorded in the key;
• - Means for bit by bit comparing the reference code with the transferred and possibly modified identification code;
• - decision means reacting to the result of said comparison;
• - Said predetermined number of preliminary loading pulses being such that the identification code transferred from the key to the lock, after any modification, corresponds to the reference code stored in the lock.

In this way, only the emission of a predetermined number preprogrammed in the electronic means of the lock makes it possible to obtain in the memory of the mobile part a perfectly defined code which is found in preprogrammed form in the fixed part or electronic lock. If it is sought to fraudulently reproduce the key of the identification system of the invention by using only an insufficient number of loading pulses, only part of the elements of the memory of the mobile part will contain the bits of the electronic identification code so that the reading of the content of the memory of the mobile part will not correspond to the expected code.

In an advantageous embodiment of the invention, the means for multiplexing the key are connected to the shift register of the key in order to cause an offset of the content of the memory which can be read each time that the means of counting the key have counted a number of preliminary loading pulses greater than one unit than the number of positions in the memory that can be read.

In this way, if we send a number of loading pulses greater than that which allows the loading of all the elements of the memory of the mobile part, the content of said memory will be modified by the first pulse exceeding the number determined so that again the content of the memory of the mobile part will no longer correspond to the appropriate code.

In another embodiment, it is possible by initial programming, to know the modification of the code caused by a number of charging pulses greater than a quantity defined than the number of pulses which cause the loading of all the elements of the memory of the moving part. This modified electronic code being preprogrammed in the comparison means of the fixed part, only the emission of the correct number of loading pulses allows a positive comparison corresponding to a validation of the key of the system of the invention.

It can therefore be seen in all cases that the system of the invention results in very high security against any attempt to fraudulently duplicate the electronic key.

In a preferred embodiment of the invention, the memory that can be read from the mobile part comprises a parallel / serial shift register, the passive memory area preprogrammed in the mobile part comprising a plurality of switches whose position determines the electronic identification code. It will be understood that these switches can be simply produced by means of connections, for example fuses, some of which can be removed during the initial programming of the key. Each flip-flop of the shift register of the mobile part is associated with one of the switches corresponding to a bit of the electronic code. The various flip-flops are grouped into register elements each corresponding to one or more bits of the aforementioned code.

In a first embodiment of the invention, the mobile part comprises a counter associated with a multiplexer, the different outputs of which are connected to the different register elements corresponding to one or more bits of the aforementioned electronic code. Another output of the multiplexer, for example the last, is connected to all of the flip-flops of the shift register of the mobile part so as to cause, when a signal is transmitted on said output, the simultaneous shift of one bit of the information in the shift register.

We therefore see in this embodiment that the emission of an additional pulse compared to the number of pulses just necessary to load the totality of the electronic code in the various elements of the shift register causes, by the shift of a bit, a modification of the code contained in the register shift which no longer corresponds to the appropriate electronic code.

The aforementioned output, for example the last output of the multiplexer, can also be directly connected to the first forcing inputs imposing a determined state on the first flip-flop of the shift register. In this way, said first flip-flop is forced into a state different from that corresponding to a bit of the electronic code preprogrammed in the mobile part.

The means for generating the charging pulses included in the fixed part or electronic lock comprise a charging circuit advantageously provided with a double flip-flop of the master-slave type associated with a NAND gate receiving clock pulses and supplying pulses loading. The output of the charging circuit is connected to a charging modulation circuit provided with a counter associated with a monostable capable of acting on the charging circuit to cause it to stop after a determined number of charging pulses.

The electronic means included in the fixed part for reading the content of the shift register of the mobile part comprises a reading circuit advantageously provided with a double flip-flop of the master-slave type associated with a NAND gate receiving the clock pulses mentioned above and connected to the monostable output of the load modulation circuit. In this way, the reading circuit is triggered after the emission of the determined number of loading pulses and provides successive pulses allowing the reading in series of the information contained in the parallel / serial shift register of the mobile part after this register has been loaded with the identification code and possibly after a determined modification of the content of the register by the action of a determined number of loading pulses.

A read stop circuit makes it possible to limit the number of clock pulses to the exact number of bits contained in the shift register of the mobile part. This read stop circuit advantageously comprises a pulse counter receiving the read pulses from the read circuit and a monostable capable of delivering a read stop pulse when the number of pulses counted corresponds to the number of bits of the shift register, that is to say when the content of the shift register of the mobile part has been read once.

In another embodiment of the invention, the memory which can be read, from the key, is locked in on itself and the lock further comprises clock modulation means receiving the pulses emitted by the reading means and capable of supplying to the memory of the key a determined number of code modification pulses, different from a multiple of the number of bits of said memory, so as to cause each time a permutation of its content, a logical combination means blocking being provided in the lock or in the key to prevent any reading operation from the key until the predetermined number of code modification pulses has been emitted.

In this way, after loading by means of a determined number of loading pulses as has just been said, the reading is no longer done by simply passing the content of the memory of the mobile part analogous to a key. to the memory of the fixed part analogous to a lock bit by bit by means of a number of read pulses exactly equal to the number of bits in the memory of the mobile part. On the contrary, according to this embodiment, a number of permutations of the content of the memory of the mobile part are first of all provoked before reading its content.

In this way, the security of the identification system of the invention is further considerably increased, only the electronic lock being able in fact to know the result of this determined number of permutations.

In a variant, the mobile part comprises a normally open logic gate receiving the successive read pulses emitted by the read circuit of the fixed part and connected to the synchronization inputs or clock inputs of the flip-flops of the parallel / serial shift register. of the moving part. The fixed part includes another logic gate connected to the input of a serial / parallel shift register of the fixed part so as to allow the information read to pass only after a determined number of read pulses.

In another variant, the mobile part comprises control means for counting the determined number of successive read pulses and a logic gate connected to the output of the parallel / serial shift register of the mobile part and to the output of the control above in order to authorize the transfer of the content of the register of the mobile part to the series / parallel register of the fixed part only after the aforementioned determined number of read pulses causing the permutations.

The control means can for example comprise a set of counters associated with one or more logic gates.

The memory area of the mobile part preferably comprises a plurality of switches which can be produced for example in the form of fuses or by destroyable connections and the position of which determines the electronic identification code. Each flip-flop of the shift register of the mobile part is associated with one of the switches whose position controls its state by means of two NAND gates receiving the loading pulse on one of their inputs. The pre The above-mentioned NOT AND door is connected by its other input to the switch with which it is associated. The second NAND gate receives the output of the first gate on its other input.

In this way, as soon as a loading pulse appears on one of the inputs of the two NAND gates, each flip-flop of the shift register is placed in a state corresponding to that of the switch with which it is associated. As a result, the identification code initially represented by the position of the plurality of switches is transferred to the various flip-flops of the shift register.

In an advantageous embodiment, the system can also comprise, in the fixed part, a circuit for authorizing successive tests. This circuit comprises a succession of flip-flops, the resetting of which depends on the positive result of the comparison made by the comparison means with the code preprogrammed in the fixed part. In this way, a number of unsuccessful attempts is authorized equal to the number of flip-flops in this succession of flip-flops before triggering an alarm.

Suitable timing means can also be provided to reset all of the system's rockers to zero when the key is inserted and after uncoupling.

• la fig. 1 représente schématiquement les principaux éléments de la partie fixe ou serrure électronique d'un système d'identification selon l'invention prévu pour la commande de la gâche d'une porte ;
• la fig. 2 représente schématiquement la partie mobile ou clé électronique destinée à être accouplée avec la partie fixe représentée sur la fig. 1 ;
• la fig. 3 est une vue détaillée partielle du registre à décalage de la partie mobile de la fig. 2 montrant le circuit de commande de chargement du code d'identification ;
• la fig. 4 est un schéma analogue à celui de la fig. 1 montrant une variante d'une serrure électronique selon l'invention ;
• la fig. 5 montre une clé électronique destinée à être couplée avec la serrure électronique de la fig. 4 ;
• la fig. 6 illustre encore une autre variante d'une serrure électronique selon l'invention et la fig. 7 montre une clé électronique destinée à être couplée avec la serrure électronique illustrée sur la fig. 6.

The invention will be better understood from the study of a few embodiments taken by way of nonlimiting examples and illustrated by the appended drawings, in which:

• fig. 1 schematically represents the main elements of the fixed part or electronic lock of an identification system according to the invention provided for controlling the strike of a door;
• fig. 2 schematically represents the mobile part or electronic key intended to be coupled with the fixed part shown in FIG. 1;
• fig. 3 is a partial detailed view of the shift register of the movable part of FIG. 2 showing the control circuit for loading the identification code;
• fig. 4 is a diagram similar to that of FIG. 1 showing a variant of an electronic lock according to the invention;
• fig. 5 shows an electronic key intended to be coupled with the electronic lock of FIG. 4;
• fig. 6 illustrates yet another variant of an electronic lock according to the invention and FIG. 7 shows an electronic key intended to be coupled with the electronic lock illustrated in FIG. 6.

In the examples illustrated, a so-called negative logic is used, that is to say for which we have adopted by convention level 1 for the ground potential and level 0 for the supply voltage which is preferably very low. of the order of + 5 volts. The current demand remains limited to a few milliamps so as to avoid any danger for the user.

As shown in particular in FIGS. 1 and 2 the identification system of the invention comprises a removable transportable part or electronic key shown in FIG. 2 and a fixed part or electronic lock shown in FIG. 1. The removable part is presented like a classic key. It can advantageously consist of a glass fiber plate sandwiched by two thicknesses of hard plastic resistant well to solvents and to extreme temperatures. The electronic key is therefore very resistant and its wear negligible in particular compared to that of a badge of the conventional type.

The electronic key comprises a certain number of electrical contacts constituted by conductive elements embedded in the plastic material cooperating on the side of the fixed part playing the role of electronic lock, with steel balls held by springs not illustrated in the figures. It is also possible to envisage making these contacts in another way, for example by opto-electronic link.

We see in fig. 2 that the electronic key shown diagrammatically comprises a parallel / serial shift register referenced 9 as a whole controlled by a succession of twenty four switches 10 whose open or closed position defines all the bits of the identification code. The switches 10 can for example be constituted by connections, a part of which was initially destroyed so as to cut the electronic link between the two terminals. The key shown in fig. 2 comprises a certain number of terminals intended to come into contact with corresponding terminals of the electronic lock when the key is coupled with the latter. Only the main terminals of the key have been shown in fig. 2

In fig. 1 we see that the terminals 11 and 12 connected together in the key by a link not shown are intended to be connected to the system ground (T). The terminal L referenced 13 is intended to receive a succession of pulses for loading the code contained in the set of switches 10 into the register 9. The terminal H referenced 14 is intended to receive a succession of pulses allowing the reading information contained in the shift register 9. The terminals A referenced 15 and 16 connected together in the key by a link not shown are intended to be connected to the electric current supply located in the lock. Finally, the output terminal S referenced 17 is connected to the output Q of the shift register 9.

It will immediately be noted that the electronic key is passive and does not include a power source. As long as it is not coupled to the lock, the shift register 9 contains no information and its reading therefore cannot provide the identification code.

The electronic lock illustrated in fig. 1 comprises a charging circuit referenced 18 as a whole, the input of which is connected to the terminal 12 when the key is coupled with the lock, i.e. with the earth of the system and the output of which provides charging pulses on terminal L.

The output of the charging circuit 18 is also connected by the connection 18a to the input of a loading modulation circuit 19. An output of the circuit 19 is connected by the connection 19a to the input of a reading circuit referenced 20 as a whole and supplying on terminal H a succession of clock pulses or read pulses. Another output of the circuit 19 is connected by the connection 19b to the charging circuit 18 in order to stop the emission of the charging pulses after a determined number of pulses.

The output of the read circuit 20 is further connected by the connection 22 to the input of a read stop circuit referenced 23 as a whole, the output of which returns via the connection 24 to the read circuit 20 in order to deliver a read stop pulse stopping the emission of clock pulses on terminal H when the content of the shift register 9 has been read once, that is to say when a total number of twenty four pulses are appeared on terminal H.

The terminal S connected to the output Q of the shift register 9 receives the serial signal representing the information contained in the shift register 9. The terminal S is connected to the input E of a circuit 25 performing a serial / parallel conversion and a comparison of the information read from the key with an identification code preprogrammed in the electronic lock itself and constituted in the example illustrated in the form of a set of switches 26 preprogrammed.

The electronic lock further comprises in the example illustrated a circuit for authorizing successive tests 27 connected by an output connection 28 to an alarm device which is actuated after four successive unsuccessful tests. A circuit 29 connected to the terminals A of the key makes it possible to stabilize the supply at + 5 volts.

A first reset circuit 30 causes all of the flip-flops and counters of the electronic key system to be reset to zero when the key is coupled to the lock.

A second reset circuit 31 causes all of the flip-flops and counters to be reset to zero and the supply cut off when the key is uncoupled.

Finally, a strike control circuit 32 receives a signal when the comparison made in circuit 25 is positive.

We will now describe in more detail the different circuits which have just been reviewed.

The loading circuit 18 comprises a double master-slave flip-flop constituted by a first flip-flop 33 or “master” and a second flip-flop 34 “slave •. The two flip-flops 33, 34 are connected to each other in a conventional manner, the second flip-flop 34 receiving on its input T the clock signal coming from the clock circuit 21. The output Q of flip-flop 34 is connected to one of the NAND gate 35 inputs further receiving on its second input the clock signal.

The input t of the first flip-flop 33 is connected via the two timers 36 and 37 to the ground of the system via terminal 12 connected to terminal T when the key is coupled to the lock. Under these conditions, the system therefore works well in negative logic.

The read circuit 20 is of the same type as the loading circuit 18 and it includes, like the latter, a double master-slave flip-flop 38, 39 mounted in the same way.

The input T of the first flip-flop 38 receives an output pulse from the load modulation circuit 19. The NAND gate 41 connected to the output of the second flip-flop 39 in the same way as the NAND gate 35 of the loading circuit 18, therefore provides a succession of pulses on terminal H, these pulses being said in the following description, clock pulses or read pulses.

The output of the NAND gate 41 is connected by the connection 22 to the read stop circuit 23 which includes a counter 42 whose outputs Q _A , Q _B , Q _c and Q _D are connected to the input of a NAND gate 42a. The output of door 42a is connected to the input A of a monostable 43.

The output pulses of the NAND gate 41 or clock pulses appearing on the terminal H transmitted by the connection 22 to the input H of the counter 42 are counted until reaching the corresponding number of twenty four in the example illustrated in the number of bits of the shift register 9 of the key, that is to say in the number of switches 10. When this number is reached, the output Q of the monostable 43 delivers an output signal applied by the connection 24 to the the forcing input R of the first flip-flop 38 of the read circuit 20 resetting the latter to zero and thereby stopping the clock pulses emitted by the circuit 20.

By this means, the reading of all the bits of the shift register 9 is therefore obtained.

The serial signal appearing on the terminal S and representing the content of the register 9 feeds the input E of a serial / parallel converter comprising three serial / parallel shift registers 45a, 45b and 45c included in the conversion and comparison circuit 25 To synchronize the serial / parallel conversion carried out in the three registers 45a, 45b and 45c with the reading of the shift register 9, the clock pulses or read pulses are also applied by the connections 46a, 46b and 46c as well as the inverter 46d at the inputs H of the three registers 45a, 45b and 45c. - The comparison code preprogrammed in the fixed part or lock, materialized by the position of the switches 26, is compared with the result of the series / parallel conversion in the circuit comparator comprising the six comparators 47a, 47b, 47c, 47d, 47e and 47f, connected in series and connected by a part to the different parallel outputs of the three conversion registers 45a, 45b and 45c and on the other hand to the different switches 26 grouped by four for each of the comparators 47a to 47f.

The result of the comparison, coming from the last element 47f is a “zero or“ one ”signal depending on whether the comparison is negative or positive. The result of this comparison appearing on the connection 51 is applied to the input D of the flip-flop 52 receiving further on its input T by the connection 53 the output signal of the read stop circuit 23. When the comparison is positive , a signal is emitted by the output Q of the flip-flop 52 and transmitted by the connection 54 via the amplifier 55 to the relay 56 closing the switch 57 of the door release control circuit 32.

At the same time, the signal emitted by the output Q of the flip-flop 52 is transmitted by the connection 58 to the NAND gate 59 whose output is connected by the inverter 59a to the reset reset inputs R of the three flip-flops 60, 61 and 62 of the successive test authorization circuit 27 connected in cascade and connected to the alarm control 28. The input T of the first flip-flop 60 receives the output signal from the read stop circuit 23 through connection 63.

In the case where the comparison is negative, a zero signal appears at the input of the monostable 52 so that the relay 56 is not energized and the strike is not opened. A loading order acts however on the input T of the first flip-flop 60 which advances by one notch.

Thanks to the cascade mounting of flip-flops 60, 61 and 62 it can be seen that four successive unsuccessful tests are authorized before the triggering of the alarm 28 by the circuit for authorizing successive tests 27. The power supply stabilization circuit 29 comprises an input terminal 64 connected to the supply battery, for example + 5 volts contained in the electronic lock but not shown in the figure. The two terminals 15 and 16 intended to cooperate with the corresponding terminals of the key are connected via the capacitor 65 and the diode 66.

When the key is coupled to the electronic lock, the current flows between the two terminals 15 and 16. The switch 67 closes under the action of the relay 68 so that the current practically no longer passes through the key. Under these conditions, the supply of the entire circuit of the electronic lock is not disturbed, in particular during possible vibrations of the key.

The electronic lock further comprises in the first reset circuit 30 a monostable 70 receiving on its input A by connection 71 the output signal of the timer 36. Under these conditions, the monostable 70 reacts to a signal having a falling edge on connection 71, that is to say when the key is coupled. The output Q of the flip-flop 70 is connected by the link 72 to one of the inputs of the NAND gate 73. The output signal of the NAND gate 73 allows via the inverter 74 and by the connections 75, 76a, 76b and 76c to reset to zero by their forcing inputs R of the three registers 45a, 45b and 45c of the series / parallel conversion circuit 25. The output Q of the flip-flop 70 is also connected by the connection 78 at one of the inputs of the NAND gate 79 receiving on its other input the output signal of the read stop circuit 23. The output of the NAND gate 79 resets to zero, by connection 79a, the counter 42.

The reset circuit 31 at the end of reading when the key is removed comprises two monostables 80 and 81 connected in cascade, the output Q of the monostable 80 being connected to the input A of the monostable 81. The first monostable 80 receives on its input B via connection 82 the output signal of timer 37 and reacts, taking into account this arrangement, on a signal having a rising edge on connection 82, that is to say during uncoupling of the key. The output to of the second monostable 81 which provides a very short pulse is connected by the connection 83 to the second input of the NAND gate 73 which causes, as we have seen previously, the resetting of the conversion circuit series / parallel 25. The Q output of monostable 81 is also connected by connection 84 to one of the inputs of NAND gate 59 so as to reset flip-flops 60, 61 and 62 of the test authorization circuit successive 27 when the key is uncoupled.

At the time of uncoupling the key, the rising edge signal on the connection 82 at the output of the timer 37 applied via the inverter 85 to the input T of the flip-flop 86 causes, via the amplifier 87 connected to its output Q, triggering of the relay 68 of the supply circuit 29 so that the supply is cut off. The flip-flop 86 is reset to zero by its input R via the connection 84a connected to the output of the monostable 81 when the key is uncoupled from the lock.

It will also be noted that the NAND gate 88 receives on its two inputs respectively the output signal from the NAND gate 73 via the inverter 74 and the connection 75 and the output signal from the inverter 85 via the connection 89. The output signal from the NAND gate 88 allows the flip-flop 52 to be reset to zero by its input R by means of the connection 90 and the inverter 91 at the time of uncoupling of the key after the expiration of the timer delay time 37.

The detailed structure of the shift register 9 of the key and of the set of switches 10 playing the role of preprogrammed memory is partially illustrated in FIG. 3. The switch 10a is shown open which, in the negative logic chosen by way of example for the circuit of FIG. 2, corresponds to a “one • signal. The switch 10b connected to earth is shown closed, which corresponds to a "zero _" signal. The other switches have not been shown on the fig. 3. This figure also shows the first two flip-flops 92a and 92b corresponding to the first two bits of the shift register 9 and which receive on their inputs H the clock signals or read pulses from the read circuit 20 of the lock by the connection 117 also illustrated in FIG. 2. The different flip-flops 92a, 92b, etc ... are connected together in a cascade in a conventional manner, the outputs Q and Q of each upstream flip-flop being connected to the inputs S and R of the flip-flop immediately following so as to produce the register shift 9.

Two NAND gates 95a and 96a are associated with the flip-flop 92a, the outputs of the two NAND gates being connected respectively to the input P placing the flip-flop 92a in the "one" state and to the input R placing the flip-flop 92a in the "zero" state.

The first NAND gate 95a is connected by its first input via the connection 97a to the switch 10a and by its second input via the connection 98a at the output of the inverter 99 receiving the loading pulse corresponding to the register element 9a by the connection 112a also visible in FIG. 2.

The output of the inverter 99 is also connected by the connection 100a to one of the inputs of the NAND gate 96a which receives on its other input by the connection 101a the output of the NAND gate 95a.

The same elements assigned the reference "b are associated with the flip-flop 92b and the switch 10b. The same elements are also found for each following flip-flop corresponding to each bit of the shift register 9. The different elements 9a to 9f have a similar structure and are mounted as illustrated in FIG. 2.

In the case of switch 10a, a signal "one is applied to input 97a of the NAND gate 95a. Taking into account the presence of the inverter 99, the negative charging pulse causes the presence of a signal "one on the second input 98a which causes a signal" zero "at the output of the NAND gate 95a. This signal “zero applied to the input 101a of the second NAND gate 96a which receives on its other input a signal“ one ”, causes the appearance of a signal“ one on the reset input R of flip-flop 92a. Examination of the circuit associated with the flip-flop 92b shows that the closed position of the switch 10b causes for the flip-flop 92b a state opposite to that of the flip-flop 92a. Under these conditions, the appearance of a loading pulse on the connection 112a causes the transfer of four bits of the identification code materialized by the position of the first four switches 10 in the form of the state of the different flip-flops 92a to 92d which can then be read in series by the clock signals applied to the inputs H. In the absence of a loading pulse, all the flip-flops remain in the zero state in the example illustrated.

The forcing inputs S and R of the first flip-flop 92a are also connected via the inverters 102 and 103 to the connection 113 also visible in FIG. 2.

Referring again to FIG. 1 we see that the load modulation circuit 19 comprises a counter 104 receiving on its input H the load pulses emitted by the load circuit 18 and connected by its outputs Q _A , Q _B , O _c and Q _o to a group of four switches 105 connected to the four inputs of a NAND gate 106. The output of gate 106 is connected to the input  of the monostable 107 whose output Q is connected by connection 19a to the input of the circuit of reading 20. The output Q of the monostable 107 is connected by the connection 19b to the reset input R of the first flip-flop 33 of the charging circuit 18. The counter 104 is reset to zero by the output signal emitted by the Q output of monostable 107 by means of connection 108.

If we now refer to fig. 2 it can be seen that the charging pulses appearing on the terminal L and coming from the charging circuit 18 are transmitted when the key is coupled to the lock by the connection 109 to the input H of a counter 110 whose outputs Q _A , O _B and O _c are connected to the inputs A, B, C of a multiplexer 111.

The shift register 9 is subdivided into six elements 9a, 9b, 9c, 9d, 9e and 9f. Each of the elements 9a to 9f is shown diagrammatically in FIG. 2 and actually comprises six sets of rockers and NAND gates such as those shown in FIG. 3, each of these rockers cooperating with one of the switches 10. Under these conditions, each of the elements of the shift register 9 cooperates with four switches 10.

The loading inputs referenced L of each of the elements 9a to 9f are respectively connected to the outputs numbered 1 to 6 of the multiplexer 111 via the connections 112a to 112f.

In other words, an output signal on one of the outputs of the multiplexer 111 causes the loading of a single element of the shift register 9, that is to say of four bits of the identification code represented by the position of all switches 10.

The output number 7 of the multiplexer 111 is connected by the connection 113 to the input E forcing the first element 9a of the shift register 9 as illustrated in detail in FIG. 3. Furthermore, the output signal emitted by the output number 7 of the multiplexer 111 is also transmitted by the connection 114 to one of the inputs of the AND gate 115, the other input of which is connected by the connection 116 to the terminal. H receiving the clock pulses or read pulses emitted by the read circuit 20 of the lock. The output of the AND gate 115 is connected by the connection 117 to all the clock inputs H of the various elements of the shift register 9 these inputs being connected to the inputs of all the flip-flops 92 as illustrated in FIG. 3.

The output Q of the last element 9f is connected by connection 118 to the output terminal S.

The counter 110 is reset to zero when the key is withdrawn via the inverter 119 connected to the power supply by the resistor 120 and the capacitor 121 and constituting a Schmidt rocker.

The illustrated system works as follows. When the key is inserted into the electronic lock, the entire system is switched on, the two terminals 15 and 16 being short-circuited. The clock circuit 21 located in the lock emits successive pulses. After a certain time determined by the timer 36 a falling edge signal causes the monostable 70 a reset pulse of the various elements of the lock. The output of the second timer 37 delivers a falling edge signal which causes, after a second delay, the start of the emission by the loading circuit 18 of negative loading pulses. These pulses appearing at the input of the counter 110 of the key successively cause the emission of a negative pulse on the different outputs of the multiplexer 111 causing the loading of the different elements 9a to 9f of the shift register 9 which each time receive information corresponding to the position of four switches 10, that is to say four bits of the electronic identification code preprogrammed in the key. It should be noted that for the sake of simplification, in FIG. 2 all of the switches 10 has been shown in the open position. In reality, of course, some of these switches are in the closed position, which defines a code initially preprogrammed in the key.

The loading pulses emitted by the circuit 18 are also applied to the input of the counter 104 located in the loading modulation circuit 19 of the lock. Depending on the predetermined position of the switches 105, it is therefore possible to cause the emission of a determined number of charging pulses. In fact, as soon as this number, determined by the position of the various switches 105, has been reached, a signal is emitted by the NAND gate 106 and by the monostable 107 which causes the charging circuit to stop via of connection 19b.

According to a first embodiment, the various switches 105 can be placed so that the number of charging pulses emitted by the circuit 18 is six. Under these conditions, the six charging pulses effectively make it possible to charge all of the twenty four switches 10 grouped by four.

During a fraudulent reproduction attempt by reading the key, the emission of a number of loading pulses greater than six causes a modification of the content of the shift register 9. In fact, a seventh pulse appearing on the output number 7 of the multiplexer 111 causes by the connection 113 a shift of one bit of the content of the shift register 9. It will be noted that for seven pulses, the logic gate 115 is blocked by the signal “zero appearing on the output number 7 counts given the use of negative logic, so that the signal from terminal H cannot pass through gate 115 preventing any reading of the content of shift register 9.

If an eighth loading pulse is emitted, a “zero” pulse again appears on the output numbered 1 of the multiplexer 111. In view of the offset which was caused by the seventh pulse, the content of the shift register 9 no longer corresponds to the code identification materialized initially by switches 10.

In another embodiment, it is possible to program in an initially predetermined manner the number of loading pulses by positioning the switches 105 of the load modulation circuit 19 differently. Knowing the number of loading pulses, it is easy to '' deduce the modification made to the content of the shift register 9 by the different pulses appearing cyclically on the output number 7 of the multiplexer 111. Knowing the code thus modified, it is possible to take it into account in the code preprogrammed in the lock materialized by the position of the various switches 26.

It can be seen that in any case the subdivision of the shift register 9 into several elements as well as the connection 113 with the output number 7 of the multiplexer 111 makes it possible to cause a modification of the preprogrammed code as a function of the number of loading pulses emitted by the loading circuit 18 of the lock. This results in very high security, preventing virtually any fraudulent reproduction of the key.

After the determined number of loading pulses has been transmitted, the shift register containing either the initial identification code or a code modified in a predetermined manner, the output signal of the loading modulation circuit 19 coming from the outputs Q and Q of the monostable 107 causes both the charging pulses to stop and the start of the emission of clock pulses or read pulses by the read circuit 20. These pulses appearing on the terminal H allow by l through the AND gate 115, the serial reading of the content of the various elements 9a to 9f of the parallel / serial shift register 9 of the key. The read pulses are counted by the read stop circuit 23 so as to be equal in the example illustrated to twenty four, that is to say to the number of bits of the shift register 9.

The serial signal appearing on terminal S and applied to the serial / parallel shift registers 45a to 45c is compared in the comparators 47a to 47f with the preprogrammed code materialized by the switches 26.

Note that for the sake of simplification, the various switches 26 have all been shown in FIG. 1 in open position. Of course in reality some of these switches 26 are in the closed position.

When the comparison made is positive, an output signal consisting of a rising edge appears on the comparator 47f. A negative pulse is supplied by the flip-flop 52 which enables the keeper 32 to be supplied by means of a falling edge signal.

The embodiment illustrated in FIGS. 4 and 5 show the main elements of the embodiment illustrated in the preceding figures, these similar elements bearing the same references. However, in this embodiment, the fixed part or electronic lock further comprises a clock modulation circuit 122 and the shift register 9 of the mobile part or electronic key illustrated in FIG. 5 is looped back on itself, the output Q of the last element 9f being connected by the connection 123 to the forcing input E of the first element 9a. The clock modulation circuit 122 comprises a set of three counters 124, 125 and 126. The first counter 124 receives on its input H the clock pulses or read pulses emitted by the read circuit 20. Four switches 124a which can be preprogrammed define by their positions a determined number and are connected to the outputs Q _A , Q _B , Q _c and Qα of the counter 124. The second counter 125 receives on its input H the output QD of the first counter 124. It is also associated with four switches 125a whose position also defines a determined number and which are connected to the outputs Q _A , Q _B , Q _c and Q _D of the counter 125. A NAND gate 127 receives on its various inputs all of the connections from the eight switches 124a and 125a. The output of the gate 127 is connected by the connection 128 to the input of the third counter 126 which is also associated with four switches 126a as is the case for the two counters 124 and 125. The connections of the four switches 126a are connected at the entrances of a NAND gate 129.

It results from the arrangement of these different means that the output of the gate 129 emits a signal after the emission of a number of clock pulses or read pulses by the circuit 20 which depends on the position of the different switches 124a , 125a and 126a. The number defined by the first two counters 124 and 125 corresponds to the number of read pulses within a cycle. The number defined by the counter 126 corresponds to the number of cycles. The total number defined by the entire modulation circuit 122 is the product of these two numbers. Of course, other means could be used for this counting. It will be noted that the output of the NAND gate 127 is also connected by the connection 130 to the input A of the monostable 131 whose output Q is connected by the connection 132 to one of the inputs of the NAND gate. 133 causing the counters 124 and 125 to be reset to zero by their inputs R when a signal is sent by the NAND gate 127. Thus, the first two counters 124 and 125 are reset to zero after each of the cycles counted by the third counter 126.

When the number thus determined of read pulses has been emitted by the read circuit 20, the output signal of the NAND gate 129 transmitted by the inverter 134 appears by the connection 135 on the first input of the AND gate 136, the second input of which is connected to the input terminal E which receives the output signal from register 9 of the key. In this way, the content of said register can only be introduced into the comparison circuit 25 after the emission of the number of read pulses determined by the clock modulation circuit 122.

The output of NAND gate 129 is also connected to one of the inputs of a NAND gate 137 which receives on its second input by connection 138 the clock pulses emitted by the read circuit 20.

In other words, after a determined number of permutations caused by the clock pulses, the number of which is determined by the three counters 124, 125 and 126, new read pulses always emitted by the read circuit 20 passing through the NAND gate 137 are transmitted by connection 139 to the input of the read stop circuit 23. These pulses are counted as in the previous embodiment. The means used are slightly different insofar as the counter 42 is here associated with a rocker 140 connected by its input T to the output Q _D of the counter 42 via the inverter 141. The two inputs of the gate NO -ET 42a are respectively connected to the output a _D of the counter 42 by the connection 142 and to the output Q of the flip-flop 140 by the connection 143. The output of the NAND gate 42a is connected to the input A of the monostable 43 which causes, as before, the emission of a signal stopping the read circuit 20 by the connection 24.

It will also be noted that in this embodiment, as a variant, certain elements have been slightly modified. Thus the NAND gate 73 associated with the inverter 74 of the embodiment of FIG. 1 has been replaced by the single door ET 73a. It is the same for the AND gates 59b and 88a of FIG. 4 which replace the NAND doors 59 and 88 associated with the inverters 59a and 91 of the embodiment of FIG. 1. Of course, the operation is strictly the same.

The operation of the identification system illustrated in figs. 4 and 5 is as follows. The loading of the identification code materialized by the position of the various switches 10 in the shift register 9 of the key is done as in the previous embodiment by means of a determined number of loading pulses emitted by the circuit of load 18 whose number is determined by the load modulation circuit 19 and which are transmitted by the multiplexer 111 to the different elements 9a to 9f of the register 9. It will however be noted that in the assembly illustrated in FIG. 5, none link is not provided between the output number 7 of the multiplexer 111 and the input E of the shift register 9. In this embodiment, in fact, the modification of the identification code contained in the shift register 9 during the emission of a signal on the output number 7 of the multiplexer 111 is done only through the AND gate 115 whose output is connected by the connection 117 to the different clock inputs H of the flip-flops of the shift register 9 looped back on itself . Such a one bit shift causes the content of the shift register 9 to be swapped.

As in the previous embodiment, a modification of the code contained in the shift register is therefore obtained as a function of the number of loading pulses.

After the transmission of the appropriate number of charging pulses, the reading circuit 20 of the lock is switched on and a number of clock pulses determined by the three counters 124, 125 and 126 is sent to terminal H Each of these pulses causes a permutation of the content of the shift register 9 of the key via the AND gate 115. It should be noted that during these different permutations the signal appearing on the output terminal S n ' is not introduced into the comparison circuit 25 taking into account the existence of the AND gate 136 which blocks the input as long as no signal is emitted at the output of the NAND gate 129. When this phase of permutation is terminated, the AND gate 136 receiving the signal from the NAND gate 129, lets pass read pulses equal in number to the number of bits of the shift register 9 in order to read its content. This number is determined by the read stop circuit 23 as before.

The comparison is made with respect to a predetermined state of the various switches 26 of the lock. Only the lock is capable of knowing the code modified after the successive permutations caused by the clock modulation circuit 122.

Note that in the embodiment of FIG. 4, the reset of the counter 104 of the load modulation circuit 19 is done directly by the connection 144 connected to the output Q of the monostable 70. In the same way, it is here the output Q of the monostable 70 which resets to zero at the start of operation by the connection 145, the counter 126, the counter 42 and by the reverser 146 the flip-flop 140.

It may prove useful to provide means for controlling the number of clock pulses in the key itself. The embodiment of FIGS. 6 and 7 illustrate this possibility for the case of a sixteen-bit code.

We find in fig. 6 and 7, the main elements already described with reference to the preceding figures and which therefore bear the same references.

We find in particular in FIG. 6 the load modulation circuit 19 which is here connected in the same way as in FIG. 1 as well as the clock modulation circuit 122. As a variant, the NAND gate 137 associated with the inverter 134 illustrated in FIG. 4 have been replaced here by the door NI 137a which plays the same role.

In the embodiment of the key illustrated in FIG. 7, the sixteen flip-flops constituting the shift register 9 are shown, each of them being associated with one of the switches 10. In this embodiment, the multiplexer 111 has eight outputs each connected to a pair of flip-flops in the register 9 by their inputs L by means of the various connections 112. The last numbered output 9 is connected to all of the inputs H of the various flip-flops via the connection 114 and the AND gate 115 which receives on its second input by connection 116 the clock or read pulses coming from terminal H.

The output number 9 of the multiplexer 111 is also connected by the connection 113 to one of the inputs of an AND gate 146, the other input of which is connected by the link 147 to the output Q of the shift register 9. The output of the AND gate 146 is connected by connection 148 to the forcing input E of the first flip-flop of the shift register 9.

The key further comprises a circuit for controlling the number of clock pulses analogous to the clock modulation circuit 122 of the lock. The control circuit 149 comprises three counters 150, 151 and 152. The first two counters 150 and 151 each associated with four programming switches 150a and 151a, supply a NAND gate 153 which is connected to its output by connection 154 to the input of the third counter 152. The latter is associated with four programming switches 152a connected to the four inputs of an AND gate 155. The output of the AND gate 155 is connected by connection 156 to one of the inputs an AND gate 157, the second input of which is connected by connection 158 to the output Q of the shift register 9. The output of the AND gate 157 is connected to the output terminal S.

The system illustrated in figs. 6 and 7 works as follows. After the coupling operation of the key and the lock, the loading is done as previously, for example according to the embodiment illustrated in FIGS. 1 and 2. It is appropriate here that the loading circuit 18 emits a number of at least one loading pulse so that all of the flip-flops of the shift register 9 of the key are loaded by the information contained in the switches 10. If this exact number of charging pulses is transmitted, the AND gate 115 remains open, so that the reading pulses or clock pulses originating from terminal H can pass through this gate and cause the information contained in the register 9 by action on the various inputs H of the flip-flops.

On the contrary, the emission of an additional loading pulse causing a signal on the output number 9 of the multiplexer 111 of FIG. 7, causes by the gate ET 146, a permuta tion of the information contained in the register 9, the entry of which is closed at the exit by the link 147.

As previously, it is possible as a variant to send a higher number of loading pulses by suitable programming of the loading modulation circuit 19 of the lock which is the only one capable of knowing the modification which will result therefrom in the content of the register. 9.

When a determined number of loading pulses has thus been emitted, clock pulses in a number also determined by the clock modulation circuit 122 appear on terminal H. The control circuit 149 of the key receives these pulses by connection 149a and counting the number, it should be noted in this connection that the programming of the control circuit 149 by means of the three groups of switches 150a, 151a and 152a is of course the same as that of the circuit of clock modulation 122 of the lock depending on the position of the three groups of switches 124a, 125a and 126a.

The two counters 150 and 151 of the control circuit 149 play the same role as the two counters 124 and 125 of the clock modulation circuit 122 and count the number of clock pulses in a cycle. The third counter 152 of the control circuit 149 plays the same role as the third counter 126 of the clock modulation circuit 122 and counts the number of cycles. Each clock pulse transmitted by the AND gate 115 open in the absence of a signal on the output number 9 of the multiplexer 111, causes a shift of one bit of the content of the shift register 9 and a permutation of this content due to the loopback by connection 147. As long as no signal appears at the output of the AND gate 155, the AND gate 157 remains blocked so that the information contained in the shift register 9 is not transmitted to the terminal S and to the comparison circuit 25 of the lock.

When the determined number of clock pulses has been emitted by the clock modulation circuit 122 and controlled by the control circuit 149, another train of clock pulses or read pulses appears on terminal H on number by being counted by the read stop circuit 23 of the lock. In this position, a signal remains transmitted by the AND gate 155 so that the AND gate 157 is open. The content of the shift register 9 is therefore transferred in series by the terminal S to the circuit and comparison 25 of the lock. When the key is uncoupled, the three counters 150, 151 and 152 are reset to zero by the Schmidt lever 119 connected to the aforementioned counters by the connection 149b.

It should be noted that in order to obtain a suitable modification of the content of the shift register 9, it is necessary that the number of clock pulses counted by the clock modulation circuit 122 and verified by the control circuit 149 is not a multiple of the number of bits in the shift register 9. Otherwise, it is understood that the permutation would not cause any modification in the content of the shift register 9.

In a first variant, the number of pulses determined by the first two counters 124 and 125 of the circuit 122 and verified by the first two counters 150 and 151 of the control circuit 149 is greater than the number of bits of the shift register 9. De in this way, the reading pulses appearing on the terminal H after the various permutations effectively allow the reading of the entire content of the shift register 9 without the gate 157 being blocked by an absence of signal on the AND gate 155.

In another variant, it is on the contrary possible to cause the reset of the third counter 152 after the counting of the number of cycles determined by the switches 152a and to authorize only the output of a bit of the shift register 9 by gate 157 each time a number of clock pulses equal to the number determined by the three counters 150, 151 and 152 has appeared on terminal H. In such a variant, it is therefore necessary to read the entire content of the shift register 9 to cause as many permutations by the clock modulation circuit 122 as there are bits in the register 9 to read the entire content of this latter register.

Ultimately, it can be seen that the system described makes it possible to obtain a complex modification of the content of the shift register 9 so that any fraudulent reproduction of the key is made extremely difficult.

In the present description, the possibility of modifying the codes by breaking fuses has been mentioned. It will be understood that it would also be possible to modify the codes using an EEPROM technology, that is to say by means of memories which can be programmed several times and thus effecting a reversible change of state. In this case, it also becomes possible to extend in application of the invention by providing that a first part of the code, for example 24 bits, is fixed, the inviolability being guaranteed by the means of the invention, while that a second part of the code, for example 48 bits, can be modified at will and repeatedly in order to perform, for example, a fund management.

Claims (16)

1. Electronic identification system comprising a movable part similar to an electronic key, intended to interact, as a result of electrical coupling, with a fixed part similar to an electronic lock, wherein : the said electronic key is of the passive type and comprises :

a) means of electrical coupling with the lock, which are intended to ensure a supply of electricity to the key and the transmission of data signals between the key and the lock ;

b) a programmable or reprogrammable read-only memory (10) having a plurality of storage locations or bits, the state of which defines an electronic identification code which cannot be read as long as it remains recorded solely in the said read-only memory (10) ; .

c) a readable memory (9) of the shift-register type connected in parallel, bit to bit, with the said read-only memory (10), in order to receive the said programmed identification code recorded in the latter, and consisting of a plurality of shift elements (9a to 9f) with one or more storage locations connected to one another, each of these elements being equipped with an independent loading control input (L) allowing independent and selective loading ;

d) counting (110), multiplexing (111) and logical combination (115) means intended for interacting with the lock when the key is coupled electrically to the latter ;

e) means (119 to 121) for ensuring that, when there is no electrical coupling between the key and lock or after this coupling has been interrupted, the readable memory (9) does not contain the said preprogrammed code in the read-only memory (10) ;-and the said electronic lock comprises :

f) electrical supply means also capable of supplying electricity to the key when it is coupled electrically to the lock ;

g) loading modulation means for supplying to the key, after coupling, a predetermined number of preliminary loading pulses intended to produce the independent and selective loading of at least some of the shift elements (9a to 9f) forming the readable memory (9) with the content of the locations of the read-only memory which are connected to these shift elements, the identification code thus being transferred into the readable memory after possible alteration when the number of loading pulses is different from the number of shift elements (9a to 9f) ;

h) reading means connected to the loading modulation means for supplying to the key, after the emission of the loading pulses, a succession of reading pulses, the number of which is equal to the total number of the storage locations of the readable memory, so as to transfer the content of the readable memory in series to the lock ;

i) means for storing in series the identification code transferred in this way from the key, after possible alteration ;

j) programmable or reprogrammable means for the storage of a reference code having the same number of bits as the identification code recorded in the key ;

k) means for comparing the reference code bit to bit with the identification code transferred and, if appropriate, altered ;

I) decision means reacting to the result of the said comparison ;

m) the said predetermined number of preliminary loading pulses being such that the identification code transferred from the key to the lock after possible alteration corresponds to the reference code stored in the lock.

2. System according to Claim 1, in which the multiplexing means (111) of the key are connected to the shift register of the key in order to cause a shift of the content of the readable memory (9) whenever the counting means (110) of the key have counted a number of preliminary loading pulses greater by one unit than the number of locations of the readable memory (9).

3. Identification system according to Claim 2, wherein the output (7, 9) of the multiplexer (111) is connected by means of an AND gate (115) to the clock inputs (H) of the elements of the shift register (9).

4. Identification system according to Claim 3, wherein the said output (7, 9) of the multiplexer (111) is also connected directly to the first forcing inputs (R, S) imposing a state on the first element of the shift register (9).

5. Identification system according to any one of the preceding claims, wherein the lock possesses a loading circuit (18) which is equipped with a double flip-flop of the master/slave type receiving clock pulses and supplying the preliminary loading pulses and the output of which is connected to a loading modulation circuit (19) equipped with a counter (104) associated with a monostable circuit (107) capable of acting on the loading circuit in order to cause it to stop after a specific number of preliminary loading pulses.

6. Identification system according to Claim 5, wherein the lock also possesses a reading circuit (20) equipped with a double flip-flop of the master/slave type receiving clock pulses and connected to the output of the monostable circuit (107) of the loading modulation circuit (19), in order to trigger the emission of successive pulses for reading in series the information contained in the shift register (9) of the key.

7. Identification system according to any one of the preceding claims, wherein the lock also possesses a reading stop circuit (23) equipped with at least one pulse counter (42) and a monostable circuit (43) connected to the output of the reading means (20) and capable of supplying a reading stop pulse when the content of the shift register (9) of the key has been read once.

8. Electronic identification system according to Claim 1, wherein the readable memory of the key is looped on itself, and the lock also possesses clock modulation means (122) receiving the pulses emitted by the reading means and capable of supplying to the memory of the key a specific number of code alteration pulses different by a multiple from the number of bits of the said memory, so as to cause a permutation of its content each time, a logical combination blocking means (136, 157) being provided in the lock or in the key to prevent any reading operation from the key as long as the predetermined number of code alteration pulses has not been emitted.

9. Identification system according to Claim 8, wherein the key possesses a normally open logical gate (115) receiving the successive reading pulses emitted by the reading circuit (20) of the lock and connected to the clock inputs (H) of the elements of the shift register (9) of the key, and the lock possesses a logical gate (136) connected to the input of a series/parallel shift register (45a) of the lock so as to allow the information read to pass through only after the specific number of reading pulses.

10. Identification system according to Claim 8, wherein the key possesses a normally open logical gate (115) receiving the successive reading pulses emitted by the reading circuit (20) of the lock and connected to the clock inputs (H) of the elements of the shift register (9) of the key, checking means (149) for counting the abovementioned specific number of successive code alteration pulses, and a logical gate (157) connected to the output of the shift register (9) of the key and to the output (156) of the abovementioned checking means (149), to allow the content of the register (9) of the key to be transferred to a series/parallel shift register (45a) of the lock only after the abovementioned specific number of code alteration pulses.

11. Identification system according to Claims 9 or 10, wherein the lock possesses a clock modulation circuit (122) for counting the abovementioned specific number of code alteration pulses emitted by the reading circuit (20), the said clock modulation circuit (122) being connected to the reading stop circuit (23) in order subsequently to authorize the emission of a number of reading pulses equal to the number of bits of the altered identification code contained in the shift register (9) of the key.

12. identification system according to Claims 10 or 11, wherein the clock modulation circuit (122) and the checking means (149) comprise a set of counters associated with one or more logical gates.

13. Identification system according to any one of the preceding claims, wherein the storage area of the key comprises a plurality of switches (10), the position of which determines the abovementioned electronic identification code, and each flip-flop (92) of the shift register (9) of the key is associated with one of the switches (10), the position of which controls its state by means of two NAND gates (95, 96) receiving the loading pulses at one of their inputs, the first (95) of the said gates being connected to the switch (10) via its other. input, and the second gate (96) receiving the output of the first gate (95) at its other input.

14. Identification system according to one of the preceding claims, also possessing a successive-test authorization circuit (27) equipped with a succession of flip-flops (60, 61, 62), the resetting to zero of which depends on the positive result of the comparison made by the comparison means (25) with the reference code preprogrammed in the lock, in order to authorize a number of fruitless tests equal to the number of flip-flops of the said succession of flip-flops, before an alarm is triggered.

15. Identification system according to one of the preceding claims, also possessing time-delay means (36) connected to a monostable circuit (70) controlling the resetting to zero of all the flip- flops of the system after the key (2) has been coupled with the lock and before the loading pulses have been emitted.

16. Identification system according to Claim 15, also possessing second time-delay means (37) connected to a set (31) of monostable circuits (80, 81) controlling the resetting to zero of all the flip-flops and counters of the system and cutting off the supply of current to the lock after the key has been uncoupled from the lock.

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