CA1060583A - Data memory for an independent portable device_ - Google Patents

Abstract

The present invention relates to systems and methods for storing data. The system according to the invention is composed: - on the one hand, of an independent portable electronic object comprising a memory, produced in the form of logic microstructures - on the other hand, of a transfer device comprising writing means and / or read for writing and / or reading data in the memory. The system is characterized by the fact that it further comprises inhibiting means, writing and / or reading means, temporarily or definitively prohibiting the writing and / or reading of specific sections (already programmed section, coded section prohibited) from memory. The system according to the invention can be used in numerous applications such as the maintenance of a bank account. keeping a health record. the distribution of banknotes.

Description

) S83 The present invention relates to methods for memo data riser and data storage systems.
A first series of compound systems is known:
- on the one hand, at least one portable object comprising a memory containing data, - on the other hand, at least one transfer device generally constituted by a peripheral unit connected to a central computer with data transfer means -between the memory of the portable object and the central computer. ~ -The carrier of the portable object introduces and mates momentarily the latter in the peripheral unit associated with the central computer. The data contained in the memory of the portable object are transferred to the central computer which ';
processes and analyzes them. The data thus processed are used for-~, .... ...
generally following ordering of various mechanisms. So, for example, it is possible to order, by means of such ~ system, opening a door or distributing tickets banking: the portable object plays the role of an electronic key allowing those who hold it to be recognized at using the identification data contained in the porta-tif and order the implementation of the associated mechanisms.
Such a system was used in particular to distribute banknotes using credit cards (cards "blue" or other9). These systems have drawbacks which are due to the fact that the memory of the portable object e9t con ~ titu ~ e by a magnetic strip, these disadvantages are the following 9:
- the contents of the memory can be erased by cha-their or by a magnetic field, - its storage capacity is relatively low, it results from this that the identification data are numerous restricted, - 1 - '' ':''' ~ 06 ~) 5 ~ 33 - the contents of the memory can be reproduced easily -on other portable objects, which is particularly annoying in case of theft or fraud, - the content of the memory can be modified using a relatively simple mechanical tool ~ e (colloidal magnifying glass, magnetic needle), - as with all systems, the magnetic strip requires storage on magnetic tapes, to be placed near of the reading head, moreover, the process is electromechanical-that, that is to say that the magnetic track must move by report to the read head.
To remedy these drawbacks, it has been proposed to use monolithic semi-read only memories conductors or fuses, in particular it has been described in the brief vet US 3,702,464 a portable object having a shape of special use of this type of memory.
Furthermore - and whatever the structure of the m ~ moire: magnetic or semiconductor - known systems have another major drawback which is due to the fact that these systems are not designed to prevent, momentarily or definitively, that certain data contained in the memory (or likely to be contained in memory) can be read by the tranq ~ ert device and extracted from memory.
Similarly, they are not designed to prevent, temporarily or definitively, that certain data transferred to the memory ~ or certain ~ areas of memory) may be altered by new registrations.
In fact, and in many applications, it is necessary ~ r ~ server area in the memory of predetermined sections, strictly defined. and to prohibit to modify or read, at less temporarily - if not definitively - their content, these ~ -predetermined sections can be:
'"'' 1 ~ 360S83 - either empty of any information, it is in particular the case when for example the portable object comprises, in addition, processing means and associated writing means for keen to write the data from the process into the memory In this case, it is indeed necessary to reserve in memory of sections empty of all information and information -forbid all inscriptions coming from outside the object portable, . ..... ...
- either already contain information that we want to con-server without it being possible to modify or read it.
It is particularly essential (as we will see) to resolve dre such a problem when the memory system is used sé to keep a bank account.
A second series of memory systems is known.
tion of compound data:
- on the one hand, at least one portable object comprising a memory intended to memorize data, - on the other hand, at least one transfer device generally constituted by a peripheral unit connected to a central computer comprising data transfer means between the central computer and the memory of the portable object (and vice versa possibly).
Thanks to such a system, it is possible to memorize in an easily transportable form of data from a central calculator and take them to another location.
Such a system has in particular been described in the patent ~ next: F. 70 07 187. The portable object described in this patent has a magnetic memory; therefore, it presents the same my disadvantages than those just described and which are due to the magnetic structure of memory.
To some extent, US Patent 3,702,464 suggests manages to use as memory a monolithic read only memory at;
~ ~ 6 ~ 5 ~ 33 semiconductors, of a particular type, and to transfer data in such a memory. However, he does not teach the means to carry out this transfer and does not specify the mo-of this transfer.
Furthermore - and whatever the structure of the memory: magneti ~ eu or semiconductor - known systems have another major drawback which is that these systems are not designed to transfer and store (as small a volume as possible) data from different geographic regions arriving in dispersed order. In other words, known systems are not designed to ins-write - while making the most of all sections available from memory - each new data in sec-separate memory options and prevent changes of the contents of the sections already written.
This disadvantage is important, in fact, in good nom-bre of applications, especially in banking applications (we will see it) it is essential to use the maximum capacity useful memory without altering the content of the sec-already programmed. However, precisely, in the case of these ap-bank complaints, the same portable object cooperates with a multitude of transfer devices unrelated to each other, te ~ u'a given transfer device ignores, a priori, the address-se section ~ vier ~ e9 of all inscriptions and in particular that from the blank section adjacent to the last written section.
It is therefore essential to resolve this problem.
The present invention relates more particularly the s ~ tame ~ of storage and data transfer which comes nent to be described (those of the first series as well as those of the second series), and aims to resolve the v ~ nients that they present.
The aim of the present invention is as follows: ~
'~''' ~ 06 ~ 5 ~ 33 create a system for transferring data between a ' trans ~ ert device and a portable object comprising a me-moire and / or, conversely, to transfer data between a memory contained in a portable object and a device for transfer. In addition, the transfer must be made according to the following two additional features, taken separately ment or in combination:
1) The system must allow for these transfers erratically and discontinuously, that is, so than:
- a same portable object can be associated with various -its repeats and without order to several transfer devices, separate, - several portable objects can be associated with ' various times and without order to the same transfer device fert. '' The problem to be solved is as follows:
see a system such as erratic writing of new data- ' n ~ es' in the memory of the portable object does not modify the story;
naked already entered data (which, a priori, we cannot generate not foresee the existence) and is done automatically in blank parts of memory.

2) The system must allow for the transfer in such a way that:
- some data contained in the memory ~ or SU9-likely to be contained in memory) cannot be momentarily or definitively read by the trans-fert ~ t extracted from memory, - some data transferred in the memory does not

3 ~ pui9sent not be temporarily or permanently changed.
The problem to be solved is as follows:
see a system such that some data cannot be ~ L06Q583 reread and / or written and / or rewritten temporarily or definitively memory.
More generally, we can say, by grouping the two additional features above under one formula, that the aim of the present invention is, moreover, perform the transfer so that the content of certain certain determined sections of memory is inaccessible from outside reading or writing, momentarily or indirectly definitely.
Finally, the present invention aims to achieve be a system capable of having, in addition to the characteristics functional ticks above specified, the advantage of being as little fraudulent as possible; that is to say to realize a system such that it is difficult to change irregularly to -favor the contents of the portable object's memory. It is utopian to pretend that a system is completely unbreakable or inviolable, on the other hand, it is justified to maintain that, among ``
several systems, some are less fraudulent than others due to the technical difficulties that the fraudsters to modify them in their favor.
It is pointed out that none of the known systems above ~ sus recall ~ s does not solve the aim of the invention, in particular, the two caract ~ ristique ~ ~ upplémentaires above exposed to point9 1) and 2). The inventor, for the first time, posed and solved a problem of practical importance, we will see, considerable.
To achieve the aim, the system according to the invention ost composed ~
- on the one hand, at least one independent portable object, electronic, - on the other hand, at least one transfer device (also called, moreover, in the text, specific device specific). '' ~.,.; . , ~.,. . ,, ~ - -, ..,, ... . :. . .
~ 06 ~ 583 The portable object, according to the invention, comprises:
- at least one memory intended for memorizing data in an easily transportable form, - coupling means accessible from the outside portable object for temporarily coupling said portati ~ object with said transfer device, - interconnected memory control circuits tees between the coupling means and the memory, allowing access memory and allow data flow into and out of memory.
Preferably, said memory and said circuits of ~; -control are realized in the form of logical microstructures preferably also the portable object is unpowered and ;;
memory is read only memory. More particularly still,;
the ROM is of the semiconductor type, this memory dead semiconductor can be reprogrammable (i.e. '~
erasable) or programmable (i.e. not erasable). Finally, this memory is preferably incorporated in an inaccessible manner inside the portable object.
THESE STRUCTURES AND SPECIAL PROVISIONS OF THE
moire make an essential contribution to making the system lon the invention infraudable.
Said transfer device comprises:
- coupling means complementary to those of the portati object ~, - means ~ of tran ~ fert connected to the means of ac-couplings these transfer means are intended to introduce and / or ~ extract data from memory: these means of tran ~
~ ert are notably composed of means of registration and / or 30 reading. '' According to the main characteristic of the present in-vention, the system is characterized by the fact that it comprises, ~ 6 ~ S83 in addition, means inhibiting transfer means (i.e.
that is to say means inhibiting means of reading and / or inscribing cription), prohibiting the reading and / or any modification of specific sections of memory.
Thanks to these inhibiting means, said sections deter-mined from the memory of the portable object remain in the state where they are found at the time of activation of the inhibitory means and throughout the period in which they are active; he nor is it possible to read the content.
The inhibiting means can be arranged either in the transfer device, either in the portable object, preferably rence however and in order to make the system as foolproof as possible, the inhibiting means are interconnected with memory control means and located in the portable object, moreover they are incorporated as inaccessibly as possible in the latter.
The embodiment of the system according to the invention, more specifically designed so that writing short stories data in the memory of the portable object does not alter the con-given data already entered and sits automatically in blank parts of the memory, is distinguished by the fact than: ';
- The means of transfer include means of ins-data cription in the memory of the portated object, - the memory of the portable object, in cooperation with the control circuit8, is organized ~ Q in a plurality of sec-separate statements intended to each receive a word, - the means inhibiting the means of registration, pre ~ erence located in the portable jet ob, are composed of a guardian of unprogrammed sections of memory:
. prohibiting the activation of the means of registration in the ca8 where the section in question is already programmed, ',' ~ ::
- ~ 3 -:;
~ 060583 . authorizing the activation of the means of registration if the section in question is not programmed, Please enter new data in this section.
In addition, the detector is further designed to memorize be the write authorization for the duration of a cycle registration form.
Thanks to this detector, new data cannot be registered in a section of memory already programmed, whatever the means used, moreover, any new the data is automatically written to an unprogrammed section of the memory.
Preferably, the non-programmed section detector is located in the portable object interconnected with the communication means requires memory. Thanks to this provision, the fraudster, even if he has the firm intention, cannot modify the content naked programmed sections since it does not have the possibility access the detector and eliminate its influence without risking destroy the memory and its control circuits.
Preferably, the non-programmed section detector of memory is composed:
- a first door receiving, in parallel, the given the considered section of memory (for example a carries ~ T in the case where the unwritten bits correspond to the ni-voi logi ~ ue 1), - a second write authorization door active-v ~ e by the first door in the case where the section considered n ~ ~ have no data and authorize the activation of the means of writing, - a memory circuit inserted between the first mi ~ re and the second door, intended to memorize the active state dela first door (at least during the duration of a cycle of enroll-tion).
"'' ~
,, 106 ~) S83 The memory circuit has the function of maintaining, despite writing the first bit affecting the state of the section, write permission. In addition, the unprogrammed section of memory preferably includes in addition, a lock interposed on the addressing circuit of the moire, activated by the first door via the circuit memorized, this lock is intended to freeze the address of the unprogrammed section of memory for the duration of the writing cycle.
Thanks to this provision, the fraudster does not have the pos-ability to address memory as desired, for example on a page already written, during the writing cycle, moreover, this arrangement makes it possible to lock the addressing during the writing, which is desirable in order to avoid any error in electronic gine. ;
The embodiment of the system according to the invention, more particularly conc, u so that certain data contained in memory (or likely to be contained in memory-re) cannot be read and / or written and / or rewritten, mo-mentally or definitively, is distinguished by the fact that:
- means inhibiting transfer means (means of reading and / or writing) are composed:
. a means of coding the ~ determined sections in-prohibited, . a means of ~ detector of ~ coded sections prohibited t ~, - prohibiting the activation of the means of transfer dan3 the case where the section in question is coded prohibited, - authorizing the activation of the transfer means if the section in question is not coded prohibited.
Thanks to such a combination of means, it is possible corn:
- to prohibit reading or writing, before or after 10605 ~ 33 writing, of such or such section of the memory of the object portable, - to ban reading or writing, temporarily or indefinitely, from this or that section of memory, depending on when the coding means are used and detection (before or after writing) and the duration during which they remain active.
With a view to solving the particular problems raised by the banking applications of this system and in particular so to thwart fraud attempts preferably, according to a complementary to the present invention, the means coding and detection are incorporated inside the ob-portable jet inaccessible from the outside.
Thanks to this arrangement, it is impossible whatever are the means implemented by the fraudster, to access the memory and modify or read its content.
The coding and detection means of the pre-determined prohibited may be of different natures.
In the case where the memory is organized in words of n bits and has input - output circuits (for reading and ) composed of n conductors, the coding means can 8tre composed by one of the bits of the word.
Detection mo ~ ens, connected to the conductor of ci ~
cooked input- ~ nettle corresponding to the coding bit, can no-be composed of a write authorization door (one port ~ ~ T if ~ 'state 0 of the coding bit indicates a 9ection prohibited) prohibiting any writing in the event that the ~ -sectlon considered is prohibited. Preferably and according to a CHARACTERISTICS OF THE INVENTION, the coding bit is the nth bit 30 of the word, the useful part of the word comprising nl bits. Thanks to this-; ~
you disposition, the coding of the nth bit does not prohibit the writing only after this has been done on the nl useful bits of the ' - 11 - '' 1060S ~ 33 word. Clearly such a provision solves the problem particular posed by the envisaged banking application. Indeed, therefore ~ ue the bank account number or the identification number fication has been written to the card and the nth bit has been altered (placed in state 0), it is no longer possible to modify it proud.
The coding and detection means of the pre-can be organized in another way. So:
- the coding means can be composed by diode arrays of read only memories, or simply of points connection, - mo ~ ens detection can be composed of minus an address comparator interconnected between the circuit for addressing the memory and the coding means, this comparison address guardian disabling a write authorization door in the case where the address considered is an inter-coded address said.
Preferably and in order to solve the problem, ~ ' particular posed by the banking application, the means of coda-are programmed irreversibly during manufacturing of the card and before being incorporated into the latter, so it is not possible to recode them di erently without deconstructs the map, thus, the addresses of prohibited sections have been completed once for all. In this case, in order to put the inscription in the prohibited sections of the data Qon ~ identifiable and personal (such as account number ~ ancaire or identification data) by the body responsible of le9 ~ establish ~ the bank, etc ~ ..), it is, moreover, provided in ~ ' the portable object a particular means, available to this organism, from ~ tiné to deactivate the inhibitory means tion. This particular means is made up of another inter-cal ~ e between the address comparator and the authorization gate ~ ~ .... ~, ...
- 12 - ;;
:
106C) S83 writing, this other door can be permanently maintained naked passing by irreversible modification of an active circuit vation. The body responsible for establishing the confidential data-the identification therefore has the possibility, thanks to this means par-particular, from:
- deactivate the means of registration inhibitor-tion before entering confidential data.
- activate the inhibitor of the registration means (the coding and detection means) after data entry confidential, The data storage system according to the invention, having the characteristics announced, is likely to large number of practical applications, we will mention no- '~' especially the following applications:
- keeping a bank account, - distribution of banknotes, - keeping a health book. '' For example, in the case of an account in bank, the client has a portable object (in the form of a card for example) containing the following information in memory your: ' - the personal authorization code, - the bank account number, - the name of the client, - the serial number of the card, - the list ~ dat ~ e or not) of the various operations of bit ~, - the list (dated or not) of the various operations of credits.
The merchant has a transfer device;
in the form of a cash register allowing it to read the contents of the card and enter new data, no-~ 06 ~ 3S ~ 3 the date and the amount of the purchase made.
The account is kept as follows:
- the Transfer Device, installed at the point of sale te, review the account supply on the card client by comparing the sum of debits to the sum of credits;
this ~ transfer device then compares this provision to ~;
amount of the projected purchase 'if this is sufficient, the positive transfer changes the memory of the client card to y -recording the amount of the purchase made.
- Then, the transfer device records in a local electronic register the bank account number of the customer as well as the amount of the expenditure made.
~.
- The merchant then regularizes the transaction with of his bank, by communicating to the latter the contact details clients' bank accounts and the amount of their purchases recorded through the transfer device, the bank will have paid by bankers of different customers the amount of their purchases and will credit the merchant's account with its amounts.
It is essential for the maintenance of a bank account.
20 than having a system: '~
- pocketing all modifications (involuntary or fraudulent) of the contents of the memory, in particular of the sec-completed, or include the bank details of the customer ent and its authorization code pf3rsonnefl.
~ detecting the already written sections of the memory of manièrf3 ~ do not modify their content, - detecting the unwritten sections of the memory so as to enter any new data. ~ ';'' The selo system ~ the invention is therefore particularly 3 '~ well suited for such a banking application, and all the more f ~ u'il is di ~ difficult ~ raudable.
We will now describe by way of non-limiting examples 1 ~ 605 ~ 33 tifs some variants of the storage system and data transfer according to the invention with reference to figures which represent:
- Figure 1: the general operating diagram of a application of the system according to the invention to the distribution of Bank notes, - Figure 2: the detailed diagram of the variant of réa-:
reading shown in Figure 1 explaining the operation-memory of the portable object's integrated circuit, - Figure 3: the detail diagram of an adder-subtractor composing one of the elements of the variant of reali-sation shown in Figure l;
- Figure 4: a first alternative embodiment of inhibiting means prohibiting any modification of the content already programmed sections of portable memory;
- Figure 5: another alternative embodiment of the means ens write inhibitors on a section already written;
- Figure 6: the detail of a one-way lock, - Figure 7: a block diagram of the organization of a transfer device capable of cooperating with a card carrying inhibitory means, such as those shown in the ~ igure 5;
- ~ igure a: the detail of the addressing circuits of the di ~ positive repre ~ ent ~ on ~ igure 7,. ~ - ~
~ ure 9: a memory module organized in mn words of 1 blt made by means of a primary memory organized in m words of ~ bits, - Figure 10: a symbolic representation of the module m ~ moire described with reference to Figure 9;
- Figure 11: an alternative embodiment of the circuit timing of the memory module described with reference to the figure 9, ~ 060 ~ 83 - Figure 12: an alternative embodiment of the means inhibitors if memory is organized in mn words 1 bit - Figure 13: another alternative embodiment of inhibiting means in the case where the memory module is of the type described with reference to Figure 9, - Figure 14: an alternative embodiment of means' inhibitors prohibiting modification of the writing of sec-prohibited coded states, - Figure 15: an alternative embodiment of the means inhibitors other than that shown in FIG. 14, - Figure 16: an alternative embodiment of a circuit of activation intended to definitively activate the inhibitory means teurs, - Figure 17: an alternative embodiment of the means inhibitors in the event that memory is addressed by means of a counter, -- Figure 18: an alternative embodiment of the means inhibitors to prohibit addresses from local memory tagged between an upper ~ X limit and an upper limit Y,.
- Figure 19: an alternative embodiment of the means inhibitors, more particularly intended to prohibit the reading ture of certain sections ~ of the memory.
The descriptions which follow call for the begin-the following general silences:
All of the 9 variant embodiments, described below.
~ Memory systems according to the invention are more cu.li ~ rement intended for banking and accounting applications, ~ 0 d ~ ce ~ ait, and in order to ~ facilitate reading, we have largely em-bent to expose their mode of operation and their effects, terminology specific to banks and account maintenance ~ n . '~'''.
, ~ 06 ~) 583 bank. The reallation variants may however have all other applications and can be used in any application where it is necessary to store data including confidential and irreversible.
Electronic circuits of all variants of realization, hereinafter described, are, due to their applica-bank tion, inaccessibly incorporated into an object portable in particular in the form of a flat card rectangular. They are incorporated into it in an inaccessible way, that is, it is not possible to access the circuits without destroying them; we can achieve this result:
in particular by making them in the form of micro-structures logic (integrated circuits) and by drowning them in a resin opaque plastic, but other mechanical solutions are envi-sageable. On all the figures concerning the portable object (the map), we have identified the dotted envelope with a dotted line reducing the parts of the circuits which are electrically or optically only inaccessible from the outside.
The coupling means are the only elements putting electrical or optical access to components electronic content inside the card.
It should be noted, however, that for other plications that do not require intensive protection against attempted fraudulent violation of the contents of the card, certain tains - if not all ~ - of ~ organs making up the means ~ ibiters could be located outside the map, no-especially in the speci ~ ic device. Likewise, for these others applicationq, precautions taken ~ to incorporate so inaccessible circuits in the map are superfluous.
Furthermore, in order to simplify as much as possible the de9cr ~ .ption of electronic circuits, we avoided representing leq supply circuits, etc ..., to keep only the essential functional circuits. However, care was taken to -, -indicate, with regard to the coupling means, by means of landmarks such as VP, VG, mass (which respectively designate the write voltage source, general power source logic circuits and the line O volt), the supply lines statement that should be made between the card and the device specific exterior.
Finally, it will be noted that the dead monolithic memories employed in these variant embodiments can be of different tures, in particular of the programmable or reprogrammed type corn. Such memories require no energy for memorization of information. On the other hand, writing information mations generally require a significant amount of energy (several instantaneous watts), ~ because of this, the manufacturers ga-an extremely long storage time, dre of several decades in the case of memoirs re-programmable. One can cite as references of this type of met moires:
- INTEL 1702 and NATIONAL SEMICONDUCTOR 5203, these mete moires are effa ~ ables by exposure to a source of ultraviolet rays or X-rays, - HARRIS 7620, MONOLOLITHIC MEMORIES 6340, TEXAS INS-TRUM ~ NTS 74 S 3 ~ 7, INT ~ RSIL 5604, these last memories not ef-f ~ çable9 (dostructibles), are of the fuse or breakdown type of ~ unctions.
~ 4096 bit capacities are commonly produced by some manufacturers, particularly in the field of memory r ~ s MOS (erasable). Modern interconnection processes d0s integrated circuit pads allow to realize inexpensively a memory block of 16 kbits or 32 kbits (4 or 8 pellets) over an area of a few tens of mm2 approx.
ron, including the special circuits covered by the pre-invention, so this block can be included in a card with the following dimensions: 2 x 60 x 80 mm.
These monolithic read-only memories of the semi-con-compared to other read only memories such as that magnetic "cassettes", flexible discs, etc ..., appreciable ages. In fact, they are more reliable, their di-mensions are smaller, they do not require movement mechanical elements for reading writing, they are insensitive as they are magnetic fields, they are difficult to counterfeit 10 re and to violate (the fraudster must use electronic means -complex tronic to modify the state of a read-only memory semiconductor type). As a result, these read only memories, semiconductor type, are particularly well suited for be used, in preference to others, in storage according to the invention, in particular, in the applications of these systems concerning banks.
The various embodiments of the metallurgy system moralization according to the invention essentially stand out each other by the structure of the portable object, so as not to not repeat several times (about each variant of reali-sation) the description of the transfer device associated with the ob-portable jet, it has only been described twice:
~ in detail by referring to ~ Figures 1, 3, - in a general and synoptic way with reference to figureg 7, 8.
It is clear to those skilled in the art, however, that none ~ portable objects which are shown in the figures can; ~
~ tre a950ci ~ to a transfer device presenting all or part tie of the characteristics of the transfer devices described.
The system according to the invention, represented in FIG. 1, consists of two separate parts which, in service, are connected by an interface symbolized by a dashed line, - 19 -: '' 106 ~ 583 vo1r:
- on the left: a portable, unpowered object, before-a ring, a card, a pendant, a pen, incorporated carrying a certain number of electronic circuits (for example made according to the technique of integrated circuits), - on the right: a specific device, advantageously a bank machine, or a cash register for direct use at a point of sale in the latter case, the debit operation described below does not not accompanied by a supply of banknotes, but by recording, in the commercial cash register, of a information allowing, subsequently to the latter, to obtain on the part of the bank of the bearer of the ring a consideration in fiduciary or scriptural money. '' For clarity, we will retain in the context of this description the assumption of a ticket distribution of bank, also strictly equivalent on the electro-fuck, assuming a cash register.
Ring circuits include a memory of dentification 40, a flow memory 50 and a creation memory says 51. The system allows during a same use the following operations: ', - identification of the wearer of the ring, operation which '' authorize or refuse the rest of the process, - possible reading of a document assigned to a car ri ~ ation de cr ~ dit et recopie of the amount to be credited with this docu-ment in the ring's credit memory, - debit in cash of a sum requested if, and '~
only qi, the state of the ring bearer's account allows it, . :: ...
30 taking into account the amount of this sum,; ~
- recording of this whole process, for the purposes of accounting and / or possible subsequent control, on a . '~. ~'' ""

~ L ~ 60583 media such as solid state memory, tape or hard disk genetic, cassette, etc ...
The operations to be carried out by the wearer of the ring are the following:
- possible introduction of a credit authorization in player 144, - dialing of the confidential identification number on the keyboard 31, - possible composition of the amount to be debited on the keyboard 63, these first three operations can be performed according to a indifferent chronological order, - then, introduction of a projecting part of the ring in a corresponding housing provided on the housing of the tributor.
When the wearer of the ring makes the last re operation which falls to him, namely the introduction of the ring in the dispenser, all the operations listed above - ~
are done very quickly ~ Almost instantly, the dis-po9itif will have finished operating, allowing one of the following results , possible according to the choice of the wearer of the ring and the condition from his account:
- simple verification of the account status by display digital of the ~ olde on the display member ~ 6 ~, ~
- checking the account status after introduction ' of a sum ~ credit by introduction of an "authorization of cr ~ dit ", which was absorbed, erased or destroyed in a way no xepr ~ 9ent ~ e, after entering the amount to be credited in the ring credit memory, 3Q - checking the account status after introduction credit, and cash debit transaction by the distributor scorer, the state of the new account after these two operations being necessarily positive or zero, :

lO ~ OS83 - checking the account status after transaction cash flow through the ATM, as in the case previous, the flow takes place only if it corresponds to a posi-tif or null of the new balance.
The different operating sequences of the device tif, which serve as a plan for the description below, are the following:
- ring feed, - initiation of the general piloting of the different or-ganes of the device by triggering of the multiplexer 38, - operation of one of the three memories (Figure 2), - operation of one of the two sub-adders sequential tractors (marked AS / S) (Figure 3), - reading of previous credits - writing of the new credit, - reading of previous debits' - writing of the new flow. ;
The cash dispenser device includes a bone power cillator 150 which feeds a winding 151.
When the ring is adapted to the distributor, the main winding mayor 151 is coupled to a secondary winding 105 which makes part of the ring circuits, this winding then provides, through a rectifier assembly comprising a diode 106 and a ~ iltre ~ lectroni ~ eu non capacitive 107, a direct voltage des-tin ~ e to di ~ ferent ring supply circuits. Even-tuellement, this coupla ~ e ~ electromagnetic is replaced by a optical coupling, the members 150 and 151 being replaced by a light source, and winding 105 by a photo-voltai battery ~ eu. The coupling of the ring and the distributor takes place simply by introducing a protruding part that includes the base;
gue danq a corresponding housing provided on the housing of the device;
tributor. This introduction has the effect of closing by pushing : 106C ~; 83 mechanical contact 27 which is part of a device not shown general supply of the distributor circuits of tickets. Simultaneously, the timer 28 is triggered, which which applies a level 1 to a first entry of the door OR 41 this level 1 is maintained for a sufficient time so that the identification of the wearer of the ring can be carried out nor-wrongly, it should be noted that the second entry of gate OR 41, which corresponds to the output of flip-flop 42, is then set to O
by tilting of rocker 42 caused by the appearance of a level 1 on its clear entrance through the OR gate (86). Yes this identification test succeeds (we will see below in what conditions and what this entails), the binding of ali-is maintained until the end of the operation of the device.
tributor, thanks to the presence of a level 1 on a second OR door entry (41), The absence of this signal, which means that the user has used a false identification number, deletes by using the supply link by presence of a zero level on the two OR gate entries (41), level 1 on the first entry having dropped to zero and level 1 on the second entry has not been established, so the distributor cannot be used ~. The material realization of the device (28) is at the reach of, the man of the profession.
Note that all of the dispositi ~ described here is wired in positive logic.
- Start of general piloting:
When a logical level 1 appears at one of ~ two ~ Inputs of door 0U (41), it is transmitted through this por- '-te ~ the AND gate (34) and, in parallel, to the ascending monostable (35), the ascending monostable (35). whose stable state is indi-that next to each of its two outputs by 1 and 0, sends a pulse of additional value (1 on the output marked 0 106 ~) 583 and 0 on the output marked 1) when a rising edge appears both at input, for the duration of the pulse emitted by the monostable (35), the output marked 1 transmits a logic level zero on a second entry of the AND gate (34) which remains thus blocked, the second output of the ascending monostable (35) sends a positive pulse on the counter reset input (36) who is the pilot of the demultiplexer (38). At the end of the impulse:
ion emitted by the ascending monostable (35), stable state 1 ap-appears on the output marked 1 of the latter, which has the e ~ fet open the AND gate (34). This then lets a pre-first pulse supplied by the clock oscillator (33); this im-drive, transmitted to the counter (36), passes the demultiplex-::
. .
eur (38) in its first position, the exit position denoted 0.:.
corresponding to the conductor T noted (160); it is transmitted if-simultaneously with the entry of the descending monostable (37), which works like the ascending monostable (35), unlike close that it sends an output pulse only on the front descending at the entrance; this positive pulse on the output denoted 0 of the organ (37) is transmitted through the demultiplex-eur ~ 38) on its output marked 0, after this pulse, this par-:.
tie of the device remains inert until the impulse appears next emitted by the clock oscillator (33) and the cycle resumes farts, identical to the pr ~ c ~ dent, the counter (36) passing the demultiplexer (3 ~) of the output not ~ e 0 ~ the output noted 1, la-said next pulse ~ set by the oscillator (33) being trans-miRe with delay and after getting back into shape by the monostable des-cendant (37), at the output marked 1 (general reset RG no-t ~ e ~ 161) of the demultiplexer ~ 38)); the operating cycle is thus successively described for the ten output states of the multi-tiplexer ~ 38), the last eight ~ incidentally all transmitting in sequence a positive pulse to the same clock conductor - g ~ n ~ rale ~ 162) through the door OR ~ 39); it should be noted that, ~

.
~ 06 ~) 583 The noted output state (9) of the multiplexer (38) is immediately followed, in the recurring operation previously described, by the output state noted 0; it is through this part of the system that the system is controlled for the entire duration of operation operation, as we will see below.
Besides the power supply to the ring circuits, the transmission of information between ring and distributor is works in one direction as in the other by optical coupling between light emitting diode and photodiode.
- Reading of the confidential identification number ~
Upon the appearance of a positive impulse at the exit tie 0 of the ascending monostable (35), a logic level 1 is tran ~
put through the OR gate (60) and the optical coupling (45) to the memory reset input, which stalls on the first page the credit (50) and debit (51) memories, for initialization of the subsequent reading process (per page means a set of ble of several parallel memory points, each of them corresponding to a non-passing or passing state depending on whether it has been written or not and this in an irreversible way). This level similarly places the sub-adders in counting position 0 sequential tractors (32) and (49) and resets the counter to zero (47), as for m ~ moire (40), it is cal ~ e permanently on;
the first page by a level 1 constant on its entry reset at zero memory (level symbolized by a plus sign in the figure 1), because it only contains one page ~ written in principle and prior to the life of the ring, which contains the identification number of its holder, written to time of account creation. Note that the code con-~ identiel is designed, not shown, in such a way that he represents both the wearer of the ring and his bank.
The memory (40) of the ring (Figure 2) is permanently ...
this in reading position by the presence of a zero level on ~ O ~ OS83 its write-read input, which also involves closing solid contacts (3) and inhibition of the slats (2), the eight-bit counter (1) followed by the latches (2) is used for addressing memory (5) (a single address here, which is that of the first page), for credit and debit memories, the step-wise from one page to another is done at the start of each cycle clock pulse by input RG (161), delay pulse Ded by the descending monostable (88) ~ which advances one step ~ .....
the address counter (1), the first pulse to appear.
on the conductor (16) resets the four-bit counter (6) controlling the output multiplexer (4) and advancing one step the counter (1) after being delayed by the monostable des- ~.
ash (88). As they arrive, the clock pulses detect in the selected page of the memory module the value of the different bits present on the considered output from the most significant bit up to least significant bit, -:
which are transmitted in series through the coupling (104) to the adder-subtractor (32), which displays by counting 30US
binary and in parallel, a number x, which is sent to.
the input of a comparator (30), on the other inputs of this comparator (30) is already displayed in the same form as a number y.
which has been transcoded in a manner not shown from ~ ' identification number previously dialed on the keypad cimal (31) by the wearer of the ring, in case of equality of x and ~, from ~, the comparator (30) sends through the AND gate (85) a level 1 at the "preset" input of the flip-flop (42) which toggles, pli ~ uant by its output a logic level 1 at the entrance of the door:
OR (41), which maintains the clock 33 after the stop of the timer (28). The presence of the door ET ~ 85) obliges the wearer of the ring to enter their confidential code in a lai imposed, corresponding to the timer hold time (28).

-. : ~ i ~; -,. . .
1061 ~ 583 - Operation of the sequencing adder subtractor tiel of i ~ entification (32) (Figure 3):
In this particular case, the member (32) operates uni-only in adder, it is kept in the position of positive counting by the presence of a level 1 permanently on its up-down counting entry noted C / D, symbolized by a sign more on figure 1. It basically includes a counter-16-bit down-counter (ll) (of which only the least eight bits are used here) on which are directed, in presence of a positive information bit at the door entrance AND (10) coming from the memory (40), the pulses coming of the oscillator (15) through the AND gate (14). Delivery to general zero coming from the driver (161) closes the door AND
(14) through the OR gate (16) and the rocker (13) and reset to ~ er the four bit counter (12), which places the multiplexer (9) ~ ur its inert input state noted 0; the first impulse clock advances the multiplexer (9) by one notch, making it switch to its input state 1, by action on the counter (12), and toggles the member (13), which removes the inhibition at the entrance of the AND gate (14), which allows the pulses to pass ~ oscillator ions (15) which is three hundred times faster that the oscillator (33); before the second clock pulse.
1 ~ 8 pulses from the oscillator (15) are. if applicable, intro-duit ~ through the AND gate (lQ) in the up-down counter 16 ~ it ~ (11), ~ the end of the 128th pulse, the frequency divider quence (~ 0) sends a level lo ~ ique 1 on the input state noted 1 of the multiplexer (9), which inhibits the AND gate (14) by rocker-ment of the rocker (13) through the OR gate (16); the system re ~ te inert until the appearance of the second clock pulse-lodge which places the multiplexer (9) on its input state denoted 2 and the previous cycle is repeated; the following information arriving on the door (10) corresponds to the reading of the value of the bit of ',:

~ 060583 rank immediately below the most significant bit of weight (second th bit of the first page ~ e memory (40), the number confi-identification essential is thus read, translated into a number of im-pulses equal to its value, written in binary code sta-ble in the organ (11) and transmitted in parallel to the input x of the comparator (30) (see Figure 1). The shift register at very serial and parallel output (17) (figure 3), followed by the latches (18) and OR gate (19) signals by a logic level 1 in end of page a blank page, that is to say all the bits of which hold information 0, none of which has been written. This arrangement ti ~ zero detector, denoted DZ is not used here, on the other hand, it is in the subtractor adder (49) as we will see below.
- Reading of the previous credit (see figure 1): ' When a logic level 1 appears at the output of the parator (30), it is transmitted through the AND gate (85) (the timer (28) having theoretically not yet stopped ~, la-which corresponds to the preset input marked PR of the flip-flop (42), the latter switches, its output going from level zero to ni-calf 1, which keeps the general clock running until the end of the whole dispenser operation, this calf 1 is transmitted to an input of the AND gate (87), making it thus passing jus ~ u'at the end of the ~ onctionnage of the device, leg organs (50), (51), (49), (~ 7) and consequently (46) and (48) é-so much ~ reset ~ as we saw previously, at the beginning of ~:
0 ~ general clock cycle following the identification cycle of the ring bearer, le9 in ~ ormations contained in the memory of cr ~ dit (50) are introduced into the subtractor adder ~ essential (49) via the output S of the memory (50) and coupling (ll9). According to a process identical to the read-confidential identification number during the first clock cycle, the passage of a page from memory (50) to the next page is done at memory level (S0), by a pulse from the start of the next clock cycle on the con-RG conductor (161) through the coupling (44) the sum of the values of all the credits previously entered in the memory of credit as described below the invention appears from stable way at the output of the sequential adder subtractor (49), in binary form, it is displayed on the device display (69) after transcoding not shown, this type of function being known to those skilled in the art. The same remark surrounding the reverse transformation is also true for keyboards with a decimal number system (31) and (~) it is Please note that during the credit reading operation, the addi- -sequential subtractor (49) is in the correct position counting thanks to the presence of a logic level 1 on its input through the output marked 0 from the decoder (48) and the OR gate (52), after the arrival of the value contained on the last page written from memory, the page that is read at the clock cycle next is a blank page, which is detected, in the addition-:
neur sequential subtractor t49) by the presence of a level logic 1 created on its zero detector output denoted DZ through the shift register with serial input and parallel output (17) (~ igure 3), the eight latche.q tl8) activated at the start of the second clock cycle via output T and gate NQN OR (19). This ni-calf 1 inhibits clock pulse RG ~ 161) through the output not ~ e 0 of the ascending monostable (81) (figure 1) and the AND gate (a2) so as to conserve the addressing of the memory ~ 50) and per-put the ~ writing of a new credit possibly requested by; ~
the wearer of the ring on said blank page.
- Writing of the new credit:
The same logic level 1 of zero detection, cross 5ant the door OR tlo8) advances the counter (47) by one notch, and, consequently, places the multiplexer (46) on its position of ~ ' - 29 _ ~ 06 (: ~ S83 very rated (1) and the decoder (48) on its exit position no-tee 1, which keeps the subtractor adder (49) in posi-positive counting by the presence of a logic level 1 on the other input of the OR gate (52), this same logic level 1 is transmitted through the coupling (57) to the write input read ture of the credit memory (50), which places the latter in write position by removing addressing at the level latches (2) opening solid reading contacts (3):
and unlocking of the AND gate (7). Entering information in:.
serial mode in the page intended to be written then takes place through the multiplexer (113) (Figure 1), both towards the credit memory via the coupling (120) that of the sequential subtractor adder (49) through the mul-:
tiplexer (46), the multiplexer (113) being controlled by the comp-.
teur (115) activated by the general clock, the value the amount to be credited is therefore entered on the first page ~:
blank from the credit memory (50) and added to the previous sum also displayed on the display member (69) through the 16-bit down-counter of the sequencing adder subtractor tiel (49). The end of the written page is detected by the door:
AND (59), the two entries of which are both at a logi that 1 at this instant, the first entry being the exit noted 1 the encoder (~ 8), the second being the highest weight output ~ lev ~ of the counter (115) through the mono ~ descending table (140) whose rale is pr ~ ci ~ ément to detect the passage of the counter (115) from state n ~ 7 to ~ state n ~ 0. When reading and inserting the memory credit (50) for the new credit has ended, the corresponding value is deleted in a way not shown, by the reader of credit vouchers (114) by the appearance on his very rated E of a logic level 1 transmitted by the driver (93), The output of the AND gate (59), brought to logic level 1, then resets the credit and debit memories to zero via the ..., ~. ,,. ,. .-. . . . . .
'1 ~) 6 () 583 te OR (60) and coupling (45), and, via the OR gate (108), advance the counter (47) one notch.
- Reading of previous debits:
The new counter position (47) places the multi-plexer (46) on its input state 2 (reading of the flow memory (151)), establishes the output marked 2 of the decoder (48) in the logi state:
that 1, the outputs noted 0, 1 and 3 of the latter being at ni-:
logic calf 0, which places the sequencing adder subtractor tiel (49) in the counting position by the presence of a level 0 on its C / D input, the reading of the previous debits is then carried out ~:
like that carried out previously in the credit memory (50), via the coupling (122), the number representing the sum of these debits being deducted from the number already entered in representation binary in the adder down counter 16 bits sequential subtractor (49), i.e. subtracted from the number previously displayed in the display member (69). The first-re blank page of flow memory is detected by door AND (109) by the presence at the output of the subtracting adder sequential tor (49) of a logic level 1 on its output DZ; he 20 Please note that at the time this information appears, the outputs ties of the equal subtractor adder (~ 9) are in one;
digital state in stable xepr ~ binary representation, corresponding the operation:
X ~ (~ as previous credits) ~ (new credit) -(so ~ me d ~ bit ~ anterior) this cett value X ~ as necessarily positive ~, even in cases o ~ the new credit is zero, assuming a previous balance zero laughter and writing a new zero credit, the value of X would obviously also be zero, which constitutes a case 3 ~ limit. ;.
The value of the sum intended to be debited, if necessary.
by the distributor, composed before the introduction of the - 31 - ..
t 10 ~ i ~ 583 ring in the distributor by the wearer of the latter on the keyboard (63) in decimal representation, is compared, under its binary form Y, at X by the binal comparator ~ 110), at the mo-ment where the output marked 3 of the decoder (48) is established at the level logic 1, this occurs during the last switchover of the account tor (47) caused by the arrival of a logic level 1 at the output tie the door (109) through the door (108), the comparison of X and Y creates a logic level equal to 1 on the single output of the comparator (110) if and only if X is greater than Y, at At this moment, the counter (115) which controls the successive input states - -~ multiplexer stops (116) being reset to zero when the -counter (47) locks onto its last state, the distributor is in the writing position of the new flow. ~
- Writing of the new flow. -Indeed, the multiplexer (46) being in its position input marked 3 is in communication with the memory of debit (51) via coupling (124) for writing a new de-bit whose value is counted down simultaneously in the same way than previously by the sequential adder subtractor (49) in stable and subtracted binary representation in the organ display (69). It should be noted that the ascending monostable (81) plays the same role for the bit memory (51) that it has jou ~ for the memory of cr ~ said (50), that is to say that the inscription-tion in memory is done well on the first blank page detected, and not on the next page which is also a blank page. From-be paxt, the series denoted by the decoder (48) being at the lo-gi ~ ue 1 places the flow memory well (51) in the writing position re during this last phase of operation of the device via the coupling (123), at the end of this phase, a stop order general is caused by tilting of the rocker (42) by the presence of a logic level 1 on its clear input through the '~
OR gate (86) following the unlocking of the AND gate (111), it ~.:

, ~ 06 ~) 583 even made passable by the presence at its entry of an impulse positive from the output noted 0 of the descending monostable (140) acting in the same way as at the end of writing in the memory (50) of the new credit. The operation of issuing tickets, not shown, happens at the same time as that of ins-writing of the new flow in the flow memory (51), unless recurrence of the sum whose amount has been previously entered in decimal representation by the wearer of the ring thanks to the keyboard (63) and tested as we saw previously.
The transformer coupling mode to supply the ring from the specific device has been chosen and represents felt in Figure 1 so as to ensure galvanic insulation than; the secondary (105) of the transformer constituted by the bearings (151) and (105) during the cooperation is followed by a filter (107) supplying regulated DC voltage at its output power supply, non-capacitive filter for the sake of miniaturization tion, the capacity required for a conventional filter cannot be made small enough compared to other organs electronic, this coupling for power could also be made by optical coupling between a ~ contained light source in said specific device and a photovoltaic cell '~ ue con ~
held in the portable object, thus ensuring galvanic isolation as desirable in order to avoid any short circuit risking truire le ~ m ~ moires contained in the ring, same mame garlic-their ~ than the other optical couplings which have been chosen for the circulation of logical levels of information between the dis:
po ~ itif and the ring. The three memories whose ~ -~ onctuction are in principle of the same type: of the circuit type int ~ re, they have the property of being written on demand 30 of, in an evolutionary and irreversible way (except for certain types:
of memories that can be erased in a non accidental way, but by appropriate processing), these memories, in addition to their capacity i: ''''' : ._ 33 _ ~:
- '' 106 '~ 583 approximately 1000 times greater per unit area than that of mete magnetic memories generally used for this type of use sation have the advantage over the latter of a ease and superior reading and writing flexibility due to the fact that they do not require immediate proximity date of the reading device, their addressing being carried out electronically, sophisticated electromechanical devices expensive and unreliable are thus replaced by simple ductors, the number of which can be reduced by the process known dice of multiplexing. Among this family of memories integrated cooking, preferably non-volatile memories tiles.
The display member (69) is easy to view by the appearance of luminous figures but it can also be replaced placed by a printer, this printer not being able be connected in parallel to its inputs, which allows the ring wearer to keep a written record of operations reading performed by the speci ~ ic device during the proce ~ operating previously described.
The method, applied to a cash dispenser bank, can also be applied directly on a point which allows the wearer of the ring to make a-cats, the amount of the amount due being paid neither in cash neither by check, but simply by the fact that the ring the buyer is debited with the amount of said sum.
The ~ igure 4 shows an alternative embodiment of a section detector not programmed, in case the detector r ~
0 ~ t contained in the 40Q card. This variant embodiment implements a memory 201. whose address is controlled by a lock 205. The door ET 202 constitutes the address detector blank, which activates memory 204. This controls both the writing door 203 and the latch 205.
- 34 -;
~. . ~. . . . . .
... ...
-FIG. 5 represents another alternative embodiment tion of the section detector not programmed in case this the latter is contained in a 400 card.
Memory 209, organized in m words of n ~ its (by example 256 words of 8 bits) is addressed from the outside by the bundle of conductors 207 (8 in the example chosen) through organ 210 (8 latches or latches); (see figure 6 the detail of realization of a lock E, S, C respectively designating the entry, output, load command). In the virgin state, all:
memory points of this organ are at logical level 1. It will be able to:
be an integrated circuit type 1702 (Intel), 5203 or 5204 (National Semiconductor) or 7620 (Harris semiconductor, for example-ple).
The output of this memory is constituted by the fact conductor seal 222 (here 8 conductors) directed outwards laughing.
The entry 211 for invalidation allows, when it is taken to logic level 1, the write operations triggered by increasing the memory supply voltage and the connection at an adequate level of the output bit intended to be crit.
When SOU9 is switched on, the RS flip-flop constituted by doors 217 and 215 is automatically placed on level 1 (conductor 216) thanks to the capacitor 213 connects to the pole posi- ~ ' ti ~ of food. This same capacitor, through the door OR 21 ~ 3 causes conduction of latch 210 for a short time and inhibiting write gate 212.
If the address at that time displayed by the driver 207 is blank (8 output wires 222 at logic level 1), the pre-30 sence of level 1 on the output of the AND gate with 8 inputs 214 forces the RS flip-flop to level 0 at the end of the transmitted pulse by capacitor 213.
This has the final consequence compared to this:
- 35 -; :: ' energizing the portable circuit, locking the organ-ne 210 and the opening of door 212, authorizing writing to this address by the driver 219.
This state is stable, until the next shutdown voltage, i.e. any change of address is now but impossible since the pulse emitted by the capacitor 213 is unique.
If the address displayed during power up is -already occupied (presence of a single zero on conductor 222) the presence of a zero level on the output of gate ET 214 will be without effect on the rocker RS, which will be placed, by ronsé
quent, at level 1 by the capacitor 213. The presence of a level 1 on the exit of OR gate 218 will therefore prohibit writing ture. Addressing will however be possible, authorizing the reading-re of all occupied addresses from memory.
The first blank address addressed will switch to state 0 and the RS flip-flop, authorizing writing and prohibiting addressing until the next power off.
If the user wishes to write to two successive addresses stops. it is essential for him to proceed voltage of the device, then a new start-up.
The device thus con ~ u can be achieved easily ~ ou form of a monolithic integrated circuit and ~ fixed on a sup-port as ~ u ~ a card (format S x 8 cm for example) carrying its 20 access connections ~ q:
- 8 ~ addressing them - 8 information output wires - 3 supply wires (general supply to circuits cooked p ~ ripheri ~ ues VG, VM memory supply, mass) - 1 writing order thread In non-monolithic form, the assembly may consist of six bo ~ thirds of integrated circuits, ~ s separate and a capacitor, - 36 - ' . . .
~ 60S83 assembled on a printed circuit establishing the ne-and serving as mechanical support.
The portable circuit is supplied by the conductors 208, 220 and 221.
The device (the transfer device), susceptible to exchange data with such a card is represented by in a synoptic manner in FIG. 7 which will now be described.
Power is supplied by the VG 240 conductors and ground 238, as well as by the conductor VM 208 during the writing phase ture.
The data received routed by the driver 224 to the processing unit 244, possibly taking into account their respective addresses (routed by driver 252 connected in parallel on conductor 222) are faced with even-external data tiles routed by conductor 248, the outcome of the processing carried out triggering writing operations tures 246 (conductors 254, 256, 226) of recording 250, of af-file 251 and / or edition 253, as well as verification 258.
The writing member 246 serves to coordinate the differences your procedures necessary for writing: increase in the voltage VM (power source particular to the ~ programmable memory 209) at VP level, level 1 on conductor 226 denoted E, disconnected connection of conductors 224 PU9 connection at an adequate level of the thread destined to be written.
The addressing device 242 will advantageously include a modulo n 257 binary counter capable of addressing memory to its successive addresses, and thus always allow writing ~ ur the first available blank address thanks to the presence of ~
NAND gate 260, three-input AND gate 262 and -30 the clock 265 (~ igure 8). '' The door NON-ET 260 is used to indicate to the processing unit 244 that the address activated at the time is blank. This ,, . -~ 06 ~) S83 door 260 could be deleted by providing for automatic reset of counter 257, when powering up the cooperation apparatus.
In the case of a 16 K bit memory (1365 pages of 12 bits), a total of 27 connection points are required for circuit, which may seem prohibitive ~. To decrease the name-bre of the connections one can carry out an input multiplexing and output, and / or use a basic memory organized in words ~
of 1 bit as will now be described with reference to the ~ -10 Figure 9 which represents a memory module organized in mn words of - ~
1 bit con ~ u autou ~ of a primary memory organized in m words of n bits, n being the desired word format. This module includes the different multiplexing circuits required, but also write circuits allowing the storage of a separate bit read (one of the eight bits of one of the "pages" among 256) by sim-full logic command on a single write input.
The writing of such a programmable memory is carried out generally in several stages. An example of a cycle is the following before:
2 ~ 1) Addressing the selected word 2) Disconnecting the memory output stages 3) El ~ vation to the correct value of the supply voltage memory statement

4) Connection to a determined voltage of the bit intended for ~ be ~ written ~ replacement of the initial state by a state 0). This location often corresponds to a memory output known as "to open collector ".
All of these operations must most often be perform by respecting certain time constants.
The memory itself 302 (for example of the type ' 7620 Harris) is connected to its booster resistors 338 to 345, as well as eight collector-type power NAND doors ~ 06 ~) 583 open 304 to 311. One of the entrances to each of these eight doors is connected to point D of the memory (disconnection command output stages). The memory power input, to which each resistor of the recall is connected, is connected to output 352 of an electronic switch.
This is made up of transistors 334 and 336 as well as the inverter 347. In the presence of a logic level O on the con-conductor 350, transistor 336 is blocked, while the reverse sor 347 activates the transistor 334, establishing the connection of the point 352 with the general power supply VG. On the contrary, in pre-level 1, the VP write supply is connected point 352.
The timing device 126, as well as the nes 348 and 303, serve to ensure the correct chronology of orders successive corresponding to the write operation.
Lock 332 ("lacht") is used to freeze the address (by a level zero, created by the inverter 328), on its blocking input ge 356 during a write operation.
Eleven address weights are required in the case of a Use of a memory of 256 x 8 bits in the form of a memory 20 ~ 8 x 1 bit.
- the eight most significant address the pro-actually called ~ "pages"), - the three least signifying3 control the multiplex-read eur 322 and write demultiplexer 320.
~ 'address ~ being chosen on 11 bits, a write order ture positi ~ on the conductor 330 locks the member 332, tan-di9 ~ uc estordonn ~ es successively - the disconnection of the memory (conductor 360) ~ -- the elevation of the supply voltage (conductor 350) ~, - setting ~ the ground of the second door entry -., ,.,. -106D5 ~ 3 ~ ON-ET selected 304 to 311 by the driver 362 authorizing conduction of the demultiplexer 320.
The addressing process is the same for reading, through multiplexer 322, controlling the output conductor tie 366.
The high input threshold inverters 312 to 319 serve wind to isolate the multiplexer 322 and the NI gate 324 during the writing phase.
The eight-input NI gate 324 detects, as a level 1 on driver 370, an eight-bit page entirely vlerge.
Thus con ~ u, the module can be represented schemati-as shown in Figure 10. It includes 17 access connections:
- 11 address weights (Ao - Alo) - 3 VP-VG-Masse power points - 2 outputs: S (bit) and AV (page signaling Virgin) - 1 Eo write command An exemplary embodiment of the timing circuit 320 is shown in fig. 11. It basically consists of three bas-cules RS 373, 374 and 375. actuated successively by four delay lines 376 - 377 - 378 - 379. The inverter 372 gives the end of write order.
A simple modification of the circuitry would allow to use this module from any type of memory: RAM, dead, programmable, or "programmable / reprogrammable". These mo-di ~ lcations are within the reach of ordinary skill in the art.
The ~ igure 12 represents another variant of realization - ~ ' tion of the inhibitor means ~ of the non-programmed section detector mée ~ in the case where ~ the memory is organized in mn words of 1 bit (e.g. 2048 1-bit words). In the case of this variant ~ 060583 the detector is contained in a card 400.
The unit 516 is a module including, around the own memory ~
said, the different circuits necessary for the procedure write, these circuits are activated by a positive command single attacked by driver 503.
The clock 502 successively positions, across the up / down counter 512 lock 514 and doors 504-506-508, ~
the different addresses of the memory. The shift register 530 converts successive information to 8-bit parallel mode sives coming out of memory. The divider 536 by 8 gives, all the 8 clock pulses, an order to examine the content of the re-gistre 530. This command is transmitted through the capacitor 538 and the OR gate 540 to the lock 523 connected to the output of the AND gate and eight inputs 525. In case the output of this-you are at level 0 (page occupied), addressing continues.
As soon as the output of lock 523 is at level 1 (full page-blank), the inverting input of door ET 504 interrupts the arrival of clock pulses, places the counter up / down 512 in the down counting position, and opens the door ET 520 which leaves 20 9th in turn pa99er the pulses from the clock 502 in door 506.
The up / down counter therefore returns backwards until the eighth pulse in this sequence (detected by the divi-8, 526) which, flipping the RS rocker constituted 't,' ~
through doors ~ NI 522 and 524, closes door 520, which puts hor ~ service l ~ orloge 502.
The memory is therefore now placed on the first mi ~ x blank address following a written page. The writing-re is now authorized, through doors 528 and 529 which allow put, respectively, the transmission of the writing order routed from outside by driver 531, and bit addressing per bit routed from outside by conductor 533 via 10 ~ 0S83 doors 506 and 508. Doors 508 and 510 and the inverter 518 are used to lock the address and to freeze the state of the account address generator during write pulses.
The capacitor 542 allows the emission of a pulse single reset of all sequent organs ~ els of the dispo-when the power is turned on.
The RS 548-550 scale is permanently reset to zero by switching the up / down counter 512 to the counting position maximum age CM (conductor 546) establishing a stable level 0 on conductor 552 which has the effect of closing the door 529.
This device prevents the user-fraudster from can return to an occupied address using, beyond the nominal capacity of the counter, the bit addressing input by bit 533.
Thus designed, the device emits on the conductor 517, as soon as it is powered up, all the information it contains keeps in memory, then places itself on the first a-first blank page. in writing position obli-gatorily ascending through door 560 whose inverting entrance seuse forces the command "ascending / descending" from zero to zero at the end of the train of eight down pulses.
Synchronization pulses are transmitted to outside ~ by conductor 509.
It goes without saying that the clock 502 might as well be placed on the outside of the device. The S09 conductor would be used, dan9 this case ~ to synchronize the module from the outside, and should be connected to point 544.
This card therefore does not require, for its good connection '~
with the outside, only six connection points.
The possible verification of the writing is done, at the end of the operation, by brief interruption of the power supply, lectura 10 ~ i0583 new memory content, and comparison with the old content previously entered and / or with the writing message also lement stored.
The divider by eight, 554, as well as the flip-flop 556 -558, allow to limit ~ bit addressing pulses by bit corresponding to writing. Within the same bet when the portable circuit is energized, it is only possible to write on the first blank "page" (an eight-bit word) of memory 516.
We will now describe Figure 13, which represents another alternative embodiment of the inhibitory means of -cription (of the section detector not programmed) in case the memory module is of the type described with reference to the figure 9. In the case of this variant embodiment, the detector is located in card 400. The memory 570 used is organized nized in words of several bits, for example 256 x 8 bits, it includes its own write and read multiplexing circuits.
A door connected to its eight parallel outputs (see fig. 9) allows to detect a blank page (presence of a level l on 'I' all of its entries and consequently on its exit), but the a-dres9age is nevertheless performed by l bit addresses.
The first "page" (first eight bits) will be required rently busy (at least one bit at zero present).
On power up, lock 578 locks on the level z ~ ro ~ premi ~ re occupied adre9se) thus opening. by in-v ~ r ~ eur 579 the gate 573 which lets the impulses come-from clock 574. ;;
The counter 571 then addresses the memory (by words of ~, l bit) while the divider 575 by 8 signals to the lock 578, at through gate 576 and capacitor 577, the changes in page. :
From the first blank page, a level l on the output ~ 06 ~ 3583 lock will close door 573 and open writing door 580 re. Addressing can then continue bit by bit, from the ex-térieur, on conductor 583 through door 572, while that write pulses will be routed from the outside also by conductor 581.
The information is output on the conduc-tor 582, while external synchronization is routed by driver 584.
If the memory has all its pages occupied The addressing will continue indefinitely, informing the user about the state of the device.
Flip-flop 586 - 587, connected to the CM 585 output of counter 571 allows closing of the bit addressing door per bit 580, beyond the nominal capacity of the meter.
The capacitor 588 emits on the conductor denoted Rl a single pulse to reset all sequential organs of the portable circuit, when powering up.
A card thus conceived can represent a mode of reac Advantageous use of a semiconductor recorder. Designed around memories of the programmable / reprogrammable type (erase-electrical or optical) it would allow, connected to a point of sale cash register for example to record to ~ ur and me ~ ure of powering up the device, words of 100 bits representing for example the number of bank deposit of the buyer ~ 84 bit ~) and the amount of the purchase (16 bits).
A card comprising for example sixteen memories of 2048 bits would thus allow the recording of 327 purchases, presenting for example 6 days of operation of a case working 9 hours a day, with one purchase every ten minutes, Regularly brought to the bank for data entry-> ~
mations, erasure and replacement with a blank card, this -:
~ 06 ~) 583 card would play the role of virtual connection between the organ of data collection (point of sale) and the processing unit (bank).
In another context of use (data entry alp ~ anumeric), this card could record the equivalent about 90 typed lines (case of a health book individual, or a passport, or identity document).
We will now describe Figure 14 which represents an alternative embodiment of the inhibitor means intended for prohibit modification of the content of prohibited coded sections .
your. The inhibiting means are contained in a card 400.
The memory 601 is organized in 9-bit words, by example 256 x 9 bits. In a virgin state, all of these points-memories are at logical level 1. The bank account number consisting for example of 21 digits, or 84 bits, is cut out in 11 8-bit words, each word being followed by a Bg bit of va- - ~
their logic 0. The initial writing is done from Bl to Bg, for each of the 11 "pages" occupied by the bank account number, in such a way that the destruction of the ninth bit does not prohibit 20 writing only after this has been done. The door ~;
602, which must eventually be able to support a high voltage ~ at its 605 input, controls the disconnect input we have - 606 - memory (often noted in the tech-pic, CS, ~ or ME). This is addressed by the beam of conductors 604 ~ 8 conductors in the example cited), while le9 9 input / output bits are available at point 603. The dre is given to the driver 607.
This embodiment has the advantage of being able to make ~ possibly irreversible any 8-bit address of the remember, however, it has the disadvantage of requiring a name-important number of connection points to the outside (21 in example), as well as a 608 diode device allowing '. , "

1064) 583 to prevent door 602 from being passed through from the outside.
It is possible to reduce the number of these connections using a memory organized in words of l bit, in a circuit cooked like that shown in Figure 15 that we will main-holding describe.
FIG. 15 shows another alternative embodiment.
inhibiting means intended to prohibit modification -~ content of prohibited coded sections. Inhibiting means are contained in a 400 card.
The address conductors 613 of memory 609 (orga-set in 2048 l bit words) also control comparisons 11-bit parallel tors 611 and 612 connected, on their second- ~ -input, to two networks of connections connecting them to coding points A and B such as diode arrays, memories dead, or simple connection points, determining the "window"
numeric prohibited (in other words the addresses of the co-sections prohibited). The comparators authorize the opening of the '~
door 614, writing can therefore be prohibited, thanks to the entrance door 610 reverser connected to the door outlet 20 61 ~. -It should be noted that 9i 11 address constituting the limit in ~ érieure of the memory corresponds to the first address of the m ~ moire, comparator 612 and gold ~ corresponding coding loop can be deleted ~.
However, a ~ in to be able to aure the initial writing no bank account, entry 615 of door 614 is blocked during the creation of the integrated circuit, then open definitively (logic level l) after the initia-reading. This is made possible by the activation circuit 617, ordered from outside at point 618, only once in the life of the card.
We will now describe, with reference to FIG. 16, 106 {~ 583 an embodiment of the activation circuit 617, capable of memorize permanently for the life of the semiconductor considered, an impulse of correct level and duration.
Such a circuit can be constituted by a transistor 620 mounted in series with a fuse element 621. An inverter 622, constitutes the output of the organ, on the connection point transistor and fuse. a diode 623 is nevertheless inter-so as to avoid that, during the destruction operation tion (which is generally carried out by means of a pulse of VP value greater than the general VG supply of the circuits), current does not flow in the direction of the inverter.
In addition, a resistor 624 is connected between the tr ~ e of the inverter and the positive pole of the VG power supply:
this way, the input of the inverter is well located at the ground potential (LED) when the fuse is blown tact, the output of the inverter therefore being at the lo-pic 1.
When the fuse is destroyed, the input of the reverse seur being connected to the positive pole of food, a level 0 is present on the output. So before the order of destruction-tion be given, a logi ~ ue level 0 is present on the output of the inverter 616 authorizing the writing. As soon as it is performed, a log level 1 of sufficient duration on the com-mande 618 causes the final tilting of the gold ~ donkey 617, consequently blocking door 614 If you want to further reduce the number of points from -connection, it is essential to provide the card with the addresses- ~ -~ e5 in serial mode: either by a shift register or by a ~;
counter. The counter has the advantage of imposing on the device ti ~ an operation based on a determined sequence at ~ address ~ from the address ~ in ~ 0 to the address 2047), which is not the case for shift register. In addition, its integration complexity is - 47 - ~:
106 ~) 583 less than that of the shift register; therefore the solution counter (asynchronous, ascending) is preferable.
FIG. 17 represents an alternative embodiment of the inhibitory means intended to prohibit the modification of the code sections prohibited in the case of a memory equipped with a 626 counter. The inhibitor means are contained in the card 400. This variant embodiment includes, for elsewhere, in addition to memory 9 (organized in 2048 1-bit words) and the write gate 610, a decoder gate circuit 629 of the starting capacitors 627 and 633, a rocker RS constituted killed by doors NI 31 and 32 as well as an activation circuit ~ -617. The decoder door circuit 629 is coded to detect under form of a high level, at output, the upper address y of forbidden coded sections 0-y ~ the address n ~ 83 in the example considered), or the bank account number, includes ~ 1 digit fres -or 84 bits- occupying the first 84 addresses of the met moire). On power-up (member 617 being activated), the output of the rocker is stably positioned in the logi gue 1, due to the (single) pulse emitted by the condensa-633, the output of the organ 617 is at a low level, as well as that of member 629, due to automatic zeroing, ordered by the capacitor 627 of the counter 626. The door 610 is therefore closed in a con, stable manner.
As soon as 84 clock pulses have been received on the addressing conductor s ~ rie 30, the output of decoder 629 spreads blit at level 1, which forces the output of the scale to zero, thus opening the writing door.
The address area 0-83 is therefore well preserved from the writing of ~ a ~ general con since the "maximum counting" output of the counter systematically resets the scale to 1 when the counter reaches address 0 by overflow. The ~
initial writing is made possible by the fact that a level 1 ~ ':. ~ "'' is originally present on the outlet of organ 617, for-~ ant the scale to zero in a stable way. After writing initial has been performed and verified, a logical 1 order on conductor 618, maintained for a sufficient time compared to port to the characteristics of organ 617, allows the release final of the rocker, i.e. definite irreversibility tive of the initial entries.
The variant embodiment shown in FIG. 17 can be used in particular to make a payment card 10 comprising in memory prohibited coded sections containing: ~;
- addresses 0 to 49: the personal authorization code - addresses 50 to 133: the bank account number, - addresses 134 to 233: the name of the user, - addresses 234 to 273: the serial number of the card.
In the example cited from a memory of 2048 bits, 1774 bits remain available to memorize financial operations - ~ -res, for example such as:
- balance amount: 12 bits, - date: 16 bits - validity bit: 1 Thus, 61 operations of 29 bits are capable of being memorized if the date recording is indifferent and if lQ bits are enough to represent the amount of the balance, 161 operations 11-bit rations can be stored in the memory of the payment card.
The modified sch ~ ma of fig. 18 illustrates a variant of realization making it possible to frame the lower border x of the numeric "~ being" is prohibited at a value x different from z ~ roî for example: O ~ x <y ~ 2047. The organs already described in referring to the previous figures have the same references.
This alternative embodiment includes a second decoration address deur 641, a second flip-flop 634 - 635 with 106 () 583 its starting capacitor 636, a decoder 637, constituted by an "OR exclusive" door as well as a door OR 638.
The 637 decoder in combination with the other deco-641, 639 and associated circuits defines the se-following sequence:
O ~ A <x: writing possible x <A ~ y: write prohibited y <A <2047: writing possible (A being the address present on the parallel outputs of the comp-626).
Figure 19 shows an alternative embodiment an inhibitor means intended in particular to prohibit reading the content of certain sections (or zones3 of the memory.
inhibitor means are located in the 400 card.
nations contained in this area never leave the map 400: they are intended to be treated inside the card by a processing means such as 646. In the variant shown in FIG. 19, the ox zone is forbidden to read, zone oy is forbidden to write.
The means inhibitor5 of the writing means have already been described by referring to Figure 1 ~, we will not further describe these means, they carry the same numerical references.
The 64û decoder, the flip-flop 641 - 642, the capacitor d ~ 3 d ~ marrage 643, the exit door 644 constitute the organs e ~ essential inhibitor means of lectllre means. When-that portc 644 is closed the information contained in the memory of the card cannot leave it and reach the reading means located outside the card especially in the specific device.
Confidential information contained in the area memory ox can for example be used to code - thanks to specialized processing means 646- the words intended to be at-written in memory as follows: these words enter in their initial coding by write entry 647 and go out on conductor 649 in the new code defined by the word in-forbidden to read.
A switch member 648 actuated by the input of write request 650 allows smooth operations properly electrical write by isolating weak circuits power during the writing phase.
The activation circuit 617 allows when it is at initial state, writing and reading of all sections of the memory.

Claims (38)

The embodiments of the invention, about which an exclusive right of property or privilege is claimed, are defined as follows: 1. System for storing data; said system being compound:
- on the one hand, at least one portable, independent object, electronic, - on the other hand, at least one transfer device, said portable object comprising:
- at least one memory intended for memorizing the data in an easily transportable form, - coupling means accessible from the outside portable object, allowing temporary coupling said portable object with said device specific, - interconnected memory control circuits between the coupling means and the memory, said memory and said control circuits being produced in the form of logical microstructures, said transfer device comprising:
- means for transferring data into the memory portable object, said system being characterized in that it further comprises:
- means inhibiting means of inter-transfer saying the transfer of content from specific sections from memory. 2. System according to claim 1 characterized in that the inhibitor means are located in the portable object and inter-connected to memory control circuits. 3. System according to claim 1 characterized in that:
- the portable object is not powered, - the memory of the portable object is a read only memory. 4. System according to claim 3, characterized in that the read only memory is of the semiconductor type. 5. System according to claim 3, characterized in that the memory is a programmable read only memory. 6. System according to claim 3, characterized in that the memory is a reprogrammable read only memory. 7. System according to claim 1, characterized in that memory is inaccessibly incorporated inside of the portable object. 8. The system of claim 1 for gathering and memorizing use data from geo-sources on the same portable medium different graphics, such as said transfer means take means of recording data in the memory of portable object; said system being characterized in that the mete memory of the portatof object, in cooperation with the communication circuits is organized in a plurality of separate sections intended born to each receive a word. 9. System according to claim 8 characterized in that:
- the inhibitor means are composed of a detector unprogrammed sections of memory:
. prohibiting the activation of the means of registration in case the section in question is already pro-grammage, . authorizing the activation of the means of registration in case the section considered is unprotected grammage, so as to enter new data In this section. 10. System according to claim 9, characterized in that:
- the detector of unprogrammed sections of the memory-re located in the transfer device, is composed:

. a shift register associated with a lock intended to convert the con-held from each section of memory, . a door connected to the parallel outputs leles of the lock authorizing the activation of means of registration. 11. System according to claim 9, characterized in that the unprogrammed memory section detector located in the portable object is composed of:
- a first door receiving in parallel the contents of the considered section of the memory, - a second write authorization door activated by the first if the sec-tion considered contains no data;
said second door actuating the means registration, - a memory circuit inserted between the first and second doors, intended for me-moralize the active state of the first door at less for the duration of a registration cycle. 12. System according to claim 11, characterized in that that the non-programmed section detector of the memory includes, in addition, a lock interposed on the addressing circuit of the memory activated by the first door via the storage circuit; said lock being intended to freeze the address of the unprogrammed section of the memory at least for the duration of a registration cycle. 13. System according to claim 12, characterized in that that the memory circuit is a flip-flop activated by setting of the portable object. 14. The system of claim 9 such as memory is organized in mn words of 1 bit and addressed, bit by bit, by a clock through a down counter, a register with offset converting the n bits of the same to parallel modes section, said system being characterized in that the section detector unprogrammed memory located in the portable object is composed of a first door receiving in parallel the content of the section considered, said first door, in the case where the section contains no data:
. blocking addressing via a second door, . positioning the down counter in position of count, . activating the countdown to the nth pulse so that the memory is placed on the address se of the first section not programmed, . authorizing the writing bit by bit at the end of the settlement ge. 15. System according to claim 14, characterized in that that said first door activates the countdown to the nth pulse through a divider? and a rocker intended to stop the countdown during the nth pulse. 16. System according to any one of claim 14 or 15, characterized in that the first door actuates the others elements of the section detector not programmed through diary of a lock returned passing all n address pulses wise by means of a divider? . 17. System according to any one of claims 14 or 15, characterized in that the up-down counter includes a maximum closing counting output, via a switch le, a door interposed on the addressing circuit. 18. The system of claim 9, such as memory is organized into m sections of n bits and addressed bit by bit to by means of an electronic circuit composed:
- on the one hand, a counter activated by a clock, - on the other hand, a memory module:
said system being characterized in that the section detector not programmed located in the portable object is composed:
. of a door receiving in parallel the contents of a section considered, . a lock connected in series with the door;
said lock being actuated in its state passing every n addressing pulses using a divider? ;
said door authorizing the implementation of the registration means through the lock in case the section considered contains no data. 19. System according to claim 18, characterized in that that the memory module includes:
- the memory proper organized in m sections n bits; the read and write outputs of the memory being connected to a read multiplexer and a writing demultiplexer, - an addressing circuit, - a lock interposed on the action addressing circuit -born by means of registration;
part of the addressing circuit conductors leaving the ver-rou being directly connected to the memory proper;
another part of the conductors of the outgoing addressing circuit of the lock being connected to the reading multiplexer and to the demul-writing tiplexer. 20. System according to claim 1, said system being characterized in that said means inhibit teurs are composed:
- a means of coding the predetermined cross sections say, - a means of detecting prohibited coded sections:
. prohibiting the activation of the means of transfer in case the section considered is coded prohibited,, . authorizing the activation of the means of transfer in the event that the section consi-derée is not coded prohibited, 21. System according to claim 20, characterized in that that the coding and detection means are incorporated in the object portable jet. 22. System according to claim 21, characterized in that the coding and detection means are incorporated into the object portable, inaccessible from the outside. 23. The system of claim 21 such as memory is organized in n-bit words and has input circuits-output for reading and writing, composed of n conductors:
said system being characterized in that:
- the coding means consist of one of the bits of said word of n bits, - the detection means are connected to the conductor of the input-output circuit corresponding to the bit of coding. 24. System according to claim 23, characterized in that that the coding means consists of the nth bit of the word. 25. System according to claim 23, characterized in that that the detection means is composed by an authorization door writing. 26. System according to claim 21, characterized in that that the detection means is composed of at least one comparator address interconnected between the memory addressing circuit and the coding means; said comparator deactivates an write torisation if the address considered is a coded address prohibited. 27. System according to claim 26, characterized in that the comparator deactivates the write authorization door through another door whose condition can be defi-nitively maintained passing through irreversible modification of a activation circuit connected to the input of this other door. 28. System according to claim 21, characterized in that that the detection and coding means are composed of at least a decoder gate, connected to the memory addressing circuit, encoded to detect the border address of prohibited sections. 29, System according to claim 28, characterized in that that the decoder operates a write authorization gate by through a seesaw. 30. System according to claim 29, characterized in that that the state of the scale is, at will, frozen by modification irreversible of an activation circuit connected to the scale. 31. System according to claim 20 such as the device transfer comprising reading means and such as the means inhibitors of reading means prohibit reading of sec-prohibited coded states;

said system being characterized in that the portable object comprises te, moreover, processing means connected to the circuits of memory command, intended to process inside the map the data contained in the sections prohibited to the reading. 32. The system of claim 1 further designed to process data from the portable object, said system being characterized in that:
- the specific device also includes:
. means of reading the content of the data of portable object, . processing means for processing data, on the one hand, contained in the card and on the other hand, directly supplied to the device specific. 33. The system of claim 32, further designed to control a device based on the data processed, said system being characterized in that:
- the specific device also includes:
. control means actuated by the means of processing and controlling said device. 34, The system of claim 32, further designed to memorize the data processed by the specific device after treatment;
said system being characterized in that:
- the processing means are interconnected with means of recording. 35. The system of claim 32 further designed to treat personal data confidentially and confidentially coming from the portable object:

said system being characterized in that:
- the portable electronic object comprises:
. another memory containing identification data fication programmed once and for all, - the specific device also includes;
. an identification comparator comparing data identification numbers contained in said other memory to data entered in the device specific by the holder of the portable object, self-risking the implementation of other means of specific positive when there is agreement between the compared data. 36. System according to claim 35, characterized in that than:
- the memory of the portable object comprises:
. two subsets of recording sections separate, - the data processing means include, at less:
. an adder-subtractor intended to perform the summation of the data contained in each of the two subsets and possibly data directly supplied to the specific device, then the difference of the sums obtained. 37. The system of claim 32, further designed to view the data contained in the object's memory portable;
said system being characterized in that:
- the specific device also includes:
. a display device. 38. System according to claim 32, characterized in that that the processing means are connected to printing means if we.