EP0059720A1 - Emitterstruktur für leistungstransistoren mit verbessertem funktionsbereich bei inverser polung und mit verbessertem schaltverhalten - Google Patents

Emitterstruktur für leistungstransistoren mit verbessertem funktionsbereich bei inverser polung und mit verbessertem schaltverhalten

Info

Publication number
EP0059720A1
EP0059720A1 EP81902183A EP81902183A EP0059720A1 EP 0059720 A1 EP0059720 A1 EP 0059720A1 EP 81902183 A EP81902183 A EP 81902183A EP 81902183 A EP81902183 A EP 81902183A EP 0059720 A1 EP0059720 A1 EP 0059720A1
Authority
EP
European Patent Office
Prior art keywords
emitter
region
semiconductor device
ring
finger
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP81902183A
Other languages
English (en)
French (fr)
Inventor
Daniel Joseph Sullivan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of EP0059720A1 publication Critical patent/EP0059720A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804Emitter regions of bipolar transistors

Definitions

  • This invention relates to semiconductor power devices, and more specifically to semiconductor power devices which must provide rapid switching and turn-off in the presence of inductive as well as resistive loads.
  • the device In the parlance of the technology, it is desirable that the device have a high Reverse Bias Safe Operating Area (RBSOA).
  • RSOA Reverse Bias Safe Operating Area
  • a power transistor When a power transistor, for example, is used as a switch driving inductive loads, the energy stored in the inductor must be dissipated during the turn-off. High voltage and high current must be sustained simultaneously during turn-off, in most cases with the emitter to base junction reverse biased. This condition results in very high instantaneous power dissipation in the transistor, and unless special precautions are taken in both the circuit and device design, device failure will result.
  • a circuit precaution commonly employed is to place a biased-diode clamp across the collector-emitter terminals of the transistor to limit the maximum voltage which will appear during turn-off to the value of the bias voltage supply plus the diode forward drop, this sum being commonly called the clamp voltage. Clamp voltages are typically in the range of a few tens to a few thousand volts in power circuits.
  • the Reverse Bias Safe Operating Area is customarily defined as that combination of peak collector current and simultaneous collector-emitter voltage that the device can sustain during turn-off without damage, measured under a specified set of standard conditions using an inductive load and high voltage clamp.
  • the device is in forward conduction in the common emitter configuration under the influence of a forward emitter-base drive.
  • Collector current is high and collector-emitter voltage is low.
  • Current density under the emitter is highest at the emitter periphery and lowest at the center of the emitter as a result of the lateral voltage drop due to lateral base current flow in the base under the emitter region.
  • emitter-base bias is suddenly reversed, emitter-collector current initially continues to flow at essentially the same value.
  • the base current is reversed, so that the lateral base voltage drop under the emitter now has the opposite sense. This causes the current distribution under the emitter to decrease at the periphery and increase at the center of the emitter region, furthest from the base contact.
  • a second method of improving RBSOA performance is to utilize emitters with a high perimeter to area * ratio. See for example R. Kaiser, U.S. Patent 3,922,706. In the past it has been customary either to break the emitter up into small islands interconnected by emitter metallization or, to have the emitter in the form of a grid with the base regions interspersed.
  • a further object of this invention is to provide geometric relationships between emitter and control regions including their corresponding metallization which permits the overall semiconductor device dimension to be shrunk or scaled while preserving desirable device properties.
  • Control region refers to the base of a three layer device or the gate of a four layer device.
  • emitter and collector refer respectively to the emitter and collector of a three layer device or the cathode and anode of a four layer device.
  • the foregoing objects are achieved through the use of a particular emitter and control region geometry.
  • the emitter is in the form of a substantially closed ring of predetermined shape, formed in the control region.
  • Emitter metallization contacts the emitter ring substantially along
  • the center of the emitter and covers but does not contact a portion of the control region so that a large area low resistance metal path is available to distribute current to the substantially ring-shaped emitter.
  • Metallization contacts are also provided for the control region and the collector region.
  • the preferred embodiment of the present invention uses an emitter ring in the form of the perimeter of a double comb structure with emitter fingers projecting from a central spine region into the surrounding control region, or the topological inverse wherein the relative positions of the emitter region metal ⁇ lization and control region metallization are interchanged, so that the emitter fingers project toward a central spine region, the spine region in both cases being a part of the control region.
  • Specific desirable relationships exist between the emitter width, emitter separation, emitter metallization width, and the extent of the control region covered by insulated emitter metallization.
  • FIG. 1 is a top view of a preferred device embodiment showing in the upper half the completed device including emitter and base metallization, and in the lower half, the device with emitter and base metal removed so that the emitter and base regions are visible;
  • FIG. 2 is a cross-section through the device of FIG. 1 perpendicular to FIG. 1 along the line 2-2 showing in schematic form the internal structure; and
  • FIG. 3 is a top view similar to FIG. 1 but of an alternative embodiment in which the emitter region has been interrupted.
  • FIG. 1 is a top view of the preferred embodiment of the invention as applied to a power transistor.
  • the upper half of FIG. 1 shows the device substantially finished with emitter metal 12 and control region metal 16 in place.
  • the metal layers In the lower half of FIG. 1, below the cut-line X-X 1 , the metal layers have been removed to show the shape and relative position of the emitter region 9 and control region 14.
  • the upper and lower halves of FIG. 1 are substantially symmetrical, this being a convenient arrangement for distributing current from the external leads.
  • In the lower right position of the FIGURE is a blowup of a portion of the emitter 9 and control region 14 to show the relative positions of the emitter contact surface 7 and the control region contact surface 15.
  • the emitter 9 has the form of a substantially closed loop or ring of tortuous contour which in this embodiment is in the shape of the perimeter of a double sided comb with emitter finger regions 23 extending symmetrically away from a central spine region 8 which is analogous to the spine of the comb.
  • the emitter finger regions 23 analogous to the teeth of the comb consist of emitter region 9 which has been folded so that two portions 10 and 22 of the substantially continuous emitter 9 are adjacent and, as shown on the upper half of FIG. 1 are substantially covered by a common emitter metal finger region 24 which is a part of the substantially continuous emitter metallization 12.
  • the sinuous emitter shape 9 provides a high emitter perimeter to area ratio, and the use of an emitter metal- lization substantially wider than the actual emitter region provides a low resistance current path to the long narrow emitter.
  • the relatively broad low resistance emitter metallization finger region 24 covers substantially the entire emitter finger region 23 wherein the emitter has been folded to place two portions 10 and 22 in contact with metal finger 24.
  • the portion 25 of the control region 14 lying between the emitter portions 10 and 22 is insulated from the emitter metallization 24.
  • FIG. 2 is a portion of the cross section of the preferred embodiment for a power transistor taken along the line 2-2 in FIG. 1 which cuts across the finger regions and shows in schematic form the several regions of the interior of the device.
  • Semiconductor body 20 is doped to form collector contact region 18, collector region 17, control region 14 and emitter region 9 including specific emitter segments 10 and 22.
  • An insulating layer 13 is formed having openings giving access to the exposed emitter contact surface 7 including the specific segments 11 and 21 and to the exposed control region contact surface 15.
  • Emitter metallization 12 is formed to make contact to exposed emitter contact surface 7 including 11 and 21, and control region metallization 16 is formed to make contact to exposed control region contact surface 15.
  • Collector metallization 19 is formed to make contact to collector contact region 18.
  • FIG. 3 shows the top view of another embodiment of a power transistor in which the emitter finger regions 23 have been interrupted at their extremities so that the
  • OMPI e itter regions 10 and 22 are connected only by emitter metal 12. It is obvious that the omission of a small portion of the total emitter region in this or similar manner will not adversely affect the device performance, and thus that the emitter ring need not be absolutely continuous to fall within the scope of this invention and could, for example, be cut into a sequence of closely spaced segments, as long as the emitter metallization provides a low resistance means of interconnecting the segments.
  • ballasting resistance is desired, to further enhance the uniformity of current flow or for other reasons, this is accomplished within the concept of the substantially continuous ring emitter by providing a multiplicity of separate exposed emitter contact surfaces spaced along the emitter, the intervening regions being insulated from the emitter metallization, and the separation being determined by the resistance desired and the sheet resistance of the emitter.
  • Emitter region 9 width is measured in the plane of the emitter ring as the difference between the outside boundary of said emitter ring and the adjacent inside boundary measured along a line perpen ⁇ dicular to and connecting the two boundaries.
  • region width is substantially constant throughout its length.
  • the width, defined as letter (B), of the portion 25 of the control region 14 lying between emitter portions 22 and 10 in FIG. 1 is the distance measured in the plane of the emitter ring between the inside boundary of the emitter portion 22 forming one boundary of the emitter finger region 23 and the inside boundary of the emitter portion 10 forming the opposite boundary of the emitter finger region, measured along a line crossing at right angles to the boundaries and extending from one side of the emitter finger region to the other side.
  • the width, defined as letter (S) of the portion 26 of the control region 14 lying between adjacent emitter finger regions is the distance measured from the emitter region boundary of one emitter finger region to the nearest boundary of the adjacent emitter finger region, along a line crossing at right angles to the boundaries.
  • Reference devices 1 and 2 did not utilize the ring shaped "hollow” emitter ring structure of the present invention.
  • the emitter region in reference devices 1 and 2 were of the same general comb shape, but were "solid” in that the width of the emitter region in the fingers was the same as the finger width, there being no enclosed control region (B) as in the present invention.
  • the E:B:E ratio for the reference devices corresponded to E:0:0 or equivalently E/2:0:E/2.
  • the commercial device had "solid" emitter fingers extending outward from a central "star” or "cross” interdigitated with corresponding base fingers projecting inward from the surrounding base.
  • test device 1 shows a clear improvement of RBSOA over both reference devices and the commercial device. Specific switching times were not recorded, but were noted to be comparable or better.
  • test device 2 shows a significant improvement in both RBSOA and crossover switching time TC over the reference devices and the commercial device.
  • Test device 3 utilized a segmented emitter, wherein the emitter ring was broken into many segments interconnected by the emitter metal. The RBSOA and crossover switching time results are similar and in both cases superior to the reference and commercial devices of the prior art. The ranges of values shown for the test devices correspond to variations in process parameters among different lots.
  • the crossover switching time TC is a measure of the interval during which the device experiences the greatest power dissipation during inductive turn-off when ⁇ E and I c are not in phase. TC is defined as the time interval measured from the instant the collector-emitter voltage has reached 10 percent of the clamp voltage, to the instant the collector current has fallen to 10 percent of its peak value.
  • the crossover switching time TC was measured under the conditions noted in Table I which were chosen to obtain optimum switching performance from the
  • the semiconductor device structure of FIG. 1 illustrates the topological configuration in which the metallized emitter forms the central "spine" and outward facing "teeth” of the double sided comb structure, while the metallized base forms an interlocking set of inward facing "teeth” attached to a "perimeter spine” running around the periphery of the semiconductor device.
  • variables B and S correspond to regions 25 and 26 respectively.
  • the structure can be "inverted", that is, the metallized control region forming the central spine and outward facing teeth, while the metallized emitter forms the inward facing teeth and perimeter spine.
  • the general emitter region shape remains virtually unchanged.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)
EP81902183A 1980-09-12 1981-07-27 Emitterstruktur für leistungstransistoren mit verbessertem funktionsbereich bei inverser polung und mit verbessertem schaltverhalten Withdrawn EP0059720A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US18637980A 1980-09-12 1980-09-12
US186379 1994-01-25

Publications (1)

Publication Number Publication Date
EP0059720A1 true EP0059720A1 (de) 1982-09-15

Family

ID=22684718

Family Applications (1)

Application Number Title Priority Date Filing Date
EP81902183A Withdrawn EP0059720A1 (de) 1980-09-12 1981-07-27 Emitterstruktur für leistungstransistoren mit verbessertem funktionsbereich bei inverser polung und mit verbessertem schaltverhalten

Country Status (4)

Country Link
EP (1) EP0059720A1 (de)
JP (1) JPS57501407A (de)
IT (1) IT1142734B (de)
WO (1) WO1982001103A1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5818964A (ja) * 1981-07-28 1983-02-03 Fujitsu Ltd 半導体装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1514008B2 (de) * 1965-04-22 1972-12-07 Deutsche Itt Industries Gmbh, 7800 Freiburg Flaechentransistor
DE1614800C3 (de) * 1967-04-08 1978-06-08 Telefunken Patentverwertungsgesellschaft Mbh, 7900 Ulm Verfahren zum Herstellen eines Planartransistors mit Tetrodeneigenschaften
US3609474A (en) * 1969-11-10 1971-09-28 Texas Instruments Inc Semiconductor with improved heat dissipation characteristics

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8201103A1 *

Also Published As

Publication number Publication date
WO1982001103A1 (en) 1982-04-01
JPS57501407A (de) 1982-08-05
IT1142734B (it) 1986-10-15
IT8149226A0 (it) 1981-09-03

Similar Documents

Publication Publication Date Title
US5969378A (en) Latch-up free power UMOS-bipolar transistor
US6121633A (en) Latch-up free power MOS-bipolar transistor
US6157049A (en) Electronic device, in particular for switching electric currents, for high reverse voltages and with low on-state losses
EP0697739B1 (de) Bipolartransistor mit isolierter Steuerelektrode
JPS62145777A (ja) 絶縁ゲートトランジスタアレイ
EP0154082B1 (de) Gate-abschaltbarer Thyristor
EP0615292A1 (de) Bipolartransistor mit isoliertem Gate
JP2002540602A (ja) トレンチゲート電界効果型素子を備えた電子装置
US5874751A (en) Insulated gate thyristor
US5936267A (en) Insulated gate thyristor
Yilmaz Cell geometry effect on IGT latch-up
US5939736A (en) Insulated gate thyristor
EP0059720A1 (de) Emitterstruktur für leistungstransistoren mit verbessertem funktionsbereich bei inverser polung und mit verbessertem schaltverhalten
CA1155236A (en) Transistor having improved turn-off time and second breakdown characteristics
JPH10326900A (ja) 電力用ダイオード
JPH05136015A (ja) 半導体装置
US4609933A (en) Gate turn-off thyristor having P+ gate and emitter
US5010384A (en) Gate turn-off thyristor with resistance layers
JP3277701B2 (ja) 横型絶縁ゲートバイポーラトランジスタ
JPS5917547B2 (ja) サイリスタ
JP2504609B2 (ja) 半導体装置
JP2777990B2 (ja) 自己消弧形サイリスタ
KR100320676B1 (ko) 사이리스터 소자
JPS6013311B2 (ja) 半導体制御整流装置
KR100376222B1 (ko) 2차브레이크다운에너지능력이향상된바이폴라트랜지스터

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19820609

AK Designated contracting states

Designated state(s): DE FR NL

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN

18W Application withdrawn

Withdrawal date: 19830218

RIN1 Information on inventor provided before grant (corrected)

Inventor name: SULLIVAN, DANIEL JOSEPH