WO1982001103A1

WO1982001103A1 - Emitter design for improved rbsoa and switching of power transistors

Info

Publication number: WO1982001103A1
Application number: PCT/US1981/001009
Authority: WO
Inventors: Inc Motorola; D Sullivan
Original assignee: Inc Motorola
Priority date: 1980-09-12
Filing date: 1981-07-27
Publication date: 1982-04-01
Also published as: EP0059720A1; JPS57501407A; IT8149226A0; IT1142734B

Abstract

Semiconductor power devices of improved RBSOA and turn-on switching time for use with inductive as well as resistive loads. The emitter (9) of a power transistor has the form of a substantially closed ring of small cross section but great peripheral length, folded into a tortuous configuration so that emitter metallization (12) on the enclosed area can provide low series resistance. In a preferred embodiment the emitter (9) takes the form of the perimeter of a double sided comb with emitter finger regions (23) protruding away from a central spine (8). Improved RBSOA and turn-off times are achieved by the specified emitter geometry and the given width ratios for emitter (10 and 22), base (25 and 26) and metal (24). These ratios permit the device to be scaled to other overall dimensions.

Description

EMITTER DESIGN FOR IMPROVED RBSOA AND SWITCHING OF POWER TRANSISTORS

BACKGROUND OF THE INVENTION

This invention relates to semiconductor power devices, and more specifically to semiconductor power devices which must provide rapid switching and turn-off in the presence of inductive as well as resistive loads. In the parlance of the technology, it is desirable that the device have a high Reverse Bias Safe Operating Area (RBSOA).

When a power transistor, for example, is used as a switch driving inductive loads, the energy stored in the inductor must be dissipated during the turn-off. High voltage and high current must be sustained simultaneously during turn-off, in most cases with the emitter to base junction reverse biased. This condition results in very high instantaneous power dissipation in the transistor, and unless special precautions are taken in both the circuit and device design, device failure will result. A circuit precaution commonly employed is to place a biased-diode clamp across the collector-emitter terminals of the transistor to limit the maximum voltage which will appear during turn-off to the value of the bias voltage supply plus the diode forward drop, this sum being commonly called the clamp voltage. Clamp voltages are typically in the range of a few tens to a few thousand volts in power circuits.

The Reverse Bias Safe Operating Area (RBSOA) is customarily defined as that combination of peak collector current and simultaneous collector-emitter voltage that the device can sustain during turn-off without damage, measured under a specified set of standard conditions using an inductive load and high voltage clamp.

OMPI The principal phenomena involved in device turn-off under inductive load are believed to occur in the following way.

Initially the device is in forward conduction in the common emitter configuration under the influence of a forward emitter-base drive. Collector current is high and collector-emitter voltage is low. Current density under the emitter is highest at the emitter periphery and lowest at the center of the emitter as a result of the lateral voltage drop due to lateral base current flow in the base under the emitter region. When the emitter-base bias is suddenly reversed, emitter-collector current initially continues to flow at essentially the same value. However, the base current is reversed, so that the lateral base voltage drop under the emitter now has the opposite sense. This causes the current distribution under the emitter to decrease at the periphery and increase at the center of the emitter region, furthest from the base contact. As more and more of the emitter current is pinched into the central region of the emitter, a plasma forms, the local tempera¬ ture rises, and thermal carrier generation increases. Beyond a certain point, the process becomes regenerative, thermal run-away results, and the device is destroyed. It has been observed for many years that power transistors fail under operating conditions which are well below the maximum limits that one would calculate assuming homogeneous current flow. This is because the regenerative nature of the failure mechanisms tends to enhance conduc¬ tion at local inhomogeneities, so that more and more of the power is dissipated in a small portion of the device active area.

Numerous attempts have been made to solve the non- uniform conduction problem and thereby improve RBSOA. For example, I. H. Morgan, U.S. Patent 3,619,741, J. Ollendorf, U.S. Patent 3,609,460 and R. Denning et al U.S. Patent 3,988,759 disclose various methods for inserting ballast

resistance in the emitter or base conduction paths of the device which have the effect of promoting more uniform conduction through the negative feedback effects of this series resistance. This significantly increases the power handling capability of the device. However, all other things being equal, adding series resistance in either the emitter or base can decrease the overall power gain and increase the switching time, items of great concern in the application area important to the present invention. A second method of improving RBSOA performance is to utilize emitters with a high perimeter to area^* ratio. See for example R. Kaiser, U.S. Patent 3,922,706. In the past it has been customary either to break the emitter up into small islands interconnected by emitter metallization or, to have the emitter in the form of a grid with the base regions interspersed. Decreasing the lateral dimensions of the emitter region or regions reduces the lateral base bias effect and hence reduces current crowding into the emitter center during turn-off. RBSOA is thus improved. However, the general configuration of the distributed emitter structures of the prior art is such that lengthy metal runs are required to tie together the emitter islands, or the base islands with the result that significant series resistance is added to the emitter or base circuits or both. As noted before, increased series resistance can adversely affect the speed performance of the device, even though it may be desirable from the point of view of promoting homogeneous current flow.

Thus in the prior art, the achievement of high RBSOA and fast switching have been conflicting requirements since the approaches used to improve RBSOA have tended to degrade switching time through increased series resistance, all other things being equal. It should be noted that there are other factors which are believed to affect switching speed and RBSOA such as base and collector doping profiles, concentration and thickness. These are believed to be substantially independent of the emitter geometry effects discussed here.

In view of the foregoing, it is an object of this invention to provide a semiconductor device structure in which RBSOA and switching speed, particularly turn-off time, are simultaneously improved.

It is a further object of this invention to provide a device structure in which either RBSOA or switching speed is substantially preserved at a favorable value while the other is improved.

Another object of this invention is to provide an emitter base configuration having simultaneously high emitter perimeter to area ratio and low emitter and base metallization series resistance. Another object of this invention is to provide a device structure in which the base emitter drive voltage required to optimally switch the device off under inductive load is reduced compared to the prior art.

A further object of this invention is to provide geometric relationships between emitter and control regions including their corresponding metallization which permits the overall semiconductor device dimension to be shrunk or scaled while preserving desirable device properties.

"Control region" as used herein refers to the base of a three layer device or the gate of a four layer device. Similarly "emitter" and "collector" as used herein refer respectively to the emitter and collector of a three layer device or the cathode and anode of a four layer device.

SUMMARY

The foregoing objects are achieved through the use of a particular emitter and control region geometry. The emitter is in the form of a substantially closed ring of predetermined shape, formed in the control region. Emitter metallization contacts the emitter ring substantially along

OMPI the center of the emitter, and covers but does not contact a portion of the control region so that a large area low resistance metal path is available to distribute current to the substantially ring-shaped emitter. Metallization contacts are also provided for the control region and the collector region. For transistors, the preferred embodiment of the present invention uses an emitter ring in the form of the perimeter of a double comb structure with emitter fingers projecting from a central spine region into the surrounding control region, or the topological inverse wherein the relative positions of the emitter region metal¬ lization and control region metallization are interchanged, so that the emitter fingers project toward a central spine region, the spine region in both cases being a part of the control region. Specific desirable relationships exist between the emitter width, emitter separation, emitter metallization width, and the extent of the control region covered by insulated emitter metallization.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top view of a preferred device embodiment showing in the upper half the completed device including emitter and base metallization, and in the lower half, the device with emitter and base metal removed so that the emitter and base regions are visible;

FIG. 2 is a cross-section through the device of FIG. 1 perpendicular to FIG. 1 along the line 2-2 showing in schematic form the internal structure; and FIG. 3 is a top view similar to FIG. 1 but of an alternative embodiment in which the emitter region has been interrupted.

OMPI DETAILED DESCRIPTION OF THE INVENTION

The various processing techniques needed to fabricate semiconductor devices of the types considered in this invention are well known per se in the art and need not be repeated here.

FIG. 1 is a top view of the preferred embodiment of the invention as applied to a power transistor. The upper half of FIG. 1 shows the device substantially finished with emitter metal 12 and control region metal 16 in place. In the lower half of FIG. 1, below the cut-line X-X¹, the metal layers have been removed to show the shape and relative position of the emitter region 9 and control region 14. The upper and lower halves of FIG. 1 are substantially symmetrical, this being a convenient arrangement for distributing current from the external leads. In the lower right position of the FIGURE is a blowup of a portion of the emitter 9 and control region 14 to show the relative positions of the emitter contact surface 7 and the control region contact surface 15.

The emitter 9 has the form of a substantially closed loop or ring of tortuous contour which in this embodiment is in the shape of the perimeter of a double sided comb with emitter finger regions 23 extending symmetrically away from a central spine region 8 which is analogous to the spine of the comb. The emitter finger regions 23 analogous to the teeth of the comb consist of emitter region 9 which has been folded so that two portions 10 and 22 of the substantially continuous emitter 9 are adjacent and, as shown on the upper half of FIG. 1 are substantially covered by a common emitter metal finger region 24 which is a part of the substantially continuous emitter metallization 12. The sinuous emitter shape 9 provides a high emitter perimeter to area ratio, and the use of an emitter metal- lization substantially wider than the actual emitter region provides a low resistance current path to the long narrow emitter. For example, the relatively broad low resistance emitter metallization finger region 24 covers substantially the entire emitter finger region 23 wherein the emitter has been folded to place two portions 10 and 22 in contact with metal finger 24. The portion 25 of the control region 14 lying between the emitter portions 10 and 22 is insulated from the emitter metallization 24.

It has been found, as will be discussed subsequently, that there are desirable ratios for the width of the typical emitter region portions 10 and 22 with respect to the width of the typical control region portion 25 lying between emitter portions 10 and 22. These desirable ratios together with limitations on the width of the emitter region itself insure that there will be adequate metal width 24 over each emitter finger region 23 to provide low series resistance.

FIG. 2 is a portion of the cross section of the preferred embodiment for a power transistor taken along the line 2-2 in FIG. 1 which cuts across the finger regions and shows in schematic form the several regions of the interior of the device. Semiconductor body 20 is doped to form collector contact region 18, collector region 17, control region 14 and emitter region 9 including specific emitter segments 10 and 22. An insulating layer 13 is formed having openings giving access to the exposed emitter contact surface 7 including the specific segments 11 and 21 and to the exposed control region contact surface 15. Emitter metallization 12 is formed to make contact to exposed emitter contact surface 7 including 11 and 21, and control region metallization 16 is formed to make contact to exposed control region contact surface 15. Collector metallization 19 is formed to make contact to collector contact region 18.

FIG. 3 shows the top view of another embodiment of a power transistor in which the emitter finger regions 23 have been interrupted at their extremities so that the

OMPI e itter regions 10 and 22 are connected only by emitter metal 12. It is obvious that the omission of a small portion of the total emitter region in this or similar manner will not adversely affect the device performance, and thus that the emitter ring need not be absolutely continuous to fall within the scope of this invention and could, for example, be cut into a sequence of closely spaced segments, as long as the emitter metallization provides a low resistance means of interconnecting the segments.

Should the addition of ballasting resistance be desired, to further enhance the uniformity of current flow or for other reasons, this is accomplished within the concept of the substantially continuous ring emitter by providing a multiplicity of separate exposed emitter contact surfaces spaced along the emitter, the intervening regions being insulated from the emitter metallization, and the separation being determined by the resistance desired and the sheet resistance of the emitter. The following is a more detailed description of the semiconductor device dimensions and ratios which may be utilized in order to achieve the desired effect.

It has been found through experiment that improved performance with respect to RBSOA can be obtained by preserving certain ratios between emitter width and spacing in the double sided comb structure illustrated in FIG. 1. At the same time turn-off switching times were preserved at favorable values or improved. Examples are given in the following table for several combinations of emitter widths and emitter finger region ratios. Several variables are defined as follows.

Emitter region 9 width, defined as letter (E), is measured in the plane of the emitter ring as the difference between the outside boundary of said emitter ring and the adjacent inside boundary measured along a line perpen¬ dicular to and connecting the two boundaries. The emitter

region width is substantially constant throughout its length.

The width, defined as letter (B), of the portion 25 of the control region 14 lying between emitter portions 22 and 10 in FIG. 1 is the distance measured in the plane of the emitter ring between the inside boundary of the emitter portion 22 forming one boundary of the emitter finger region 23 and the inside boundary of the emitter portion 10 forming the opposite boundary of the emitter finger region, measured along a line crossing at right angles to the boundaries and extending from one side of the emitter finger region to the other side. The total width, defined as letter (M) , of a typical emitter finger region is therefore given by M=2E+B. The width, defined as letter (S) of the portion 26 of the control region 14 lying between adjacent emitter finger regions is the distance measured from the emitter region boundary of one emitter finger region to the nearest boundary of the adjacent emitter finger region, along a line crossing at right angles to the boundaries.

Several series of "test devices" were fabricated according to the teachings of this invention. These were compared with "reference devices" processed in a generally like manner, but with emitter geometries omitting key features of this invention so as to have, insofar as was possible, otherwise substantially similar structures. The emitter geometries used in the "reference devices" are representative of the prior art. Comparison was also made with "commercial devices" (2N6678) representative of the prior art. Process parameters for the "commercial devices" were unknown. TABLE I COMPARISON OF RBSOA AND SWITCHING TIME RESULTS

Reference Reference Test Test Test Commercial

Parameter Device 1 Device 2 Device 1 Device 2 Device 3 Device (Units)

Total Emitter 0.36 0.20 0.20 0.20 0.20 0.18 (mm) Finger Region Width M

Metal Width 0.36 0.20 0.20 0.20 0.20 0.076 (mm)

Ratio E:B:E 7:0:7 4:0:4 3:2:3 2:4:2 2:4:2 not applicable

Structure Single Emitter per Comb Folded Ring CFR with Single emitter comb finger (SEF) (CFR) Segmented per finger.

Emitter "star" shape

Test - I

RBSOA ΘIc=5A 450 650 840 450 (volts) VBEoff-=5V

Test - II

RBSOA @Ic=5A 450 503 948-1100* 803-1062 450 (volts) VBEoff @5V

RBSOA @Ic=10A 405 561-800 508-548 (volts)

@ Ic 10.0 10.0 10.0 10.0 10.0 (amps)

5.0 5.0 3.5 3.5 5.0 (volts)

1.5 1.5 2.0. 2.0 1.5 (amps) itation at 1100 volts, actual RBSOA higher,

Reference devices 1 and 2 did not utilize the ring shaped "hollow" emitter ring structure of the present invention. The emitter region in reference devices 1 and 2 were of the same general comb shape, but were "solid" in that the width of the emitter region in the fingers was the same as the finger width, there being no enclosed control region (B) as in the present invention. Thus the E:B:E ratio for the reference devices corresponded to E:0:0 or equivalently E/2:0:E/2. The commercial device had "solid" emitter fingers extending outward from a central "star" or "cross" interdigitated with corresponding base fingers projecting inward from the surrounding base.

In Test I, test device 1 shows a clear improvement of RBSOA over both reference devices and the commercial device. Specific switching times were not recorded, but were noted to be comparable or better. In Test II, test device 2 shows a significant improvement in both RBSOA and crossover switching time TC over the reference devices and the commercial device. Test device 3 utilized a segmented emitter, wherein the emitter ring was broken into many segments interconnected by the emitter metal. The RBSOA and crossover switching time results are similar and in both cases superior to the reference and commercial devices of the prior art. The ranges of values shown for the test devices correspond to variations in process parameters among different lots.

The crossover switching time TC is a measure of the interval during which the device experiences the greatest power dissipation during inductive turn-off when ς_E and I_c are not in phase. TC is defined as the time interval measured from the instant the collector-emitter voltage has reached 10 percent of the clamp voltage, to the instant the collector current has fallen to 10 percent of its peak value. The crossover switching time TC was measured under the conditions noted in Table I which were chosen to obtain optimum switching performance from the

OMPI different devices,, From the circuit point of view, the smaller value of VBE-off required for optimum switching of the test devices is an additional advantage.

It has been found that the objectives of this invention are met by the preferred embodiment in which the emitter width E is less than or equal to 0.0076cm, more specifically in the range of 0.0025 to 0.0076 cm, and in which the variables E and B are in the ratio E:B:E = 2+1 to 4+ to 2+1 respectively, the sum of the ratios remaining approximately constant, and in which M=2E+B and S have ratios in the range M:S = 5+ to 5+1, the sum of the ratios remaining approximately constant.

The relationships illustrated above have the virtue that they provide guidelines for the scaled reduction or shrinking of device size as processing technology improves, while preserving the essential features of the geometry relationship among the key elements of the structure.

The semiconductor device structure of FIG. 1 illustrates the topological configuration in which the metallized emitter forms the central "spine" and outward facing "teeth" of the double sided comb structure, while the metallized base forms an interlocking set of inward facing "teeth" attached to a "perimeter spine" running around the periphery of the semiconductor device. In this configuration, variables B and S correspond to regions 25 and 26 respectively. It is obvious that the structure can be "inverted", that is, the metallized control region forming the central spine and outward facing teeth, while the metallized emitter forms the inward facing teeth and perimeter spine. The general emitter region shape remains virtually unchanged. However, to preserve the numerical relationships among E, B, and S discussed earlier, the definitions of B and S must be interchanged in the inverted structure so that B would now correspond to region 26 and S to region 25, and emitter metallization would overlie 26 and control region metallization would be present in region 25. With these substitutions the same numerical relationships apply.

Thus it is apparent that there has been provided in accordance with the invention an improved emitter, control region, and metallization structure for semiconductor power devices that fully meets the objectives and advantages set forth above. While the invention has been described in terms of examples in the form of the perimeter of double sided comb structures for the emitter configuration, with emitter metallization contacting adjacent emitter portions and bridging over the control region surface lying between the emitter portions, it is also useful with other geometries which may have different shape, but preserve the basic topological relationships among the emitter region, the control region, the emitter metallization, and the control region metallization. Such modifications and optimizations will be apparent to those skilled in the art in the light of the foregoing description. Accordingly, it is intended to encompass all such variations as fall within the scope of the appended claims.

OMPI

Claims

1. In a semiconductor device having within the body of the semiconductor a region for collecting charge carriers and a region for controlling charge carriers, and external contact means thereto, the improvement comprising: an emitter region formed in said control region in the shape of a substantially closed ring of predetermined shape with at least one exposed emitter contact surface for making electrical contact; an emitter metallization region electrically contacting said emitter ring on said exposed emitter contact surface, and substantially covering but not electrically contacting regions of the semiconductor device interior to said emitter ring.

2. The semiconductor device of claim 1 wherein said emitter ring has been folded to give the form of the perimeter of a double sided comb with emitter finger regions extending away from a central spine region.

3. The semiconductor device of claim 1 wherein the semiconductor body is silicon.

4. The semiconductor device of claim 1 wherein the ring shaped emitter has a lateral dimension measured in the plane of the ring being defined as the difference between the outside boundary of said emitter ring and the adjacent inside boundary measured along a line perpendicular to and connecting the two boundaries, which is less than 0.0076 cm.

5. The semiconductor device of claim 4 wherein the lateral dimension is in the range 0.0025 to 0.0076 cm.

OMPI

6. The semiconductor device of claim 2 wherein the lateral dimensions in the emitter finger regions measured in the plane of the comb along a line crossing at right angles from one side of an emitter finger region to the other side, have the ratios 2 + 1 to 4 + 2 to 2 + 1 for respectively, the emitter width forming one boundary of the finger, the width of the control region lying within the finger and the emitter width forming the other boundary of the emitter finger, the ratios being selected so that the emitter regions have the same width, and the sum of the three ratios remains substantially constant.

7. The semiconductor device of claim 1 wherein the emitter ring comprises at least two segments.

8. The semiconductor device of claim 2 wherein the width of the emitter finger regions and the separation of adjacent emitter finger regions have ratios in the range 5 + 1 to 5 + 1, the sum of the ratios remaining substantially constant.

9. In a semiconductor device having within the body of the semiconductor a region for collecting charge carriers and a region for controlling charge carriers, and external contact means thereto, the improvement comprising: an emitter region formed in said control region in the shape of a substantially closed ring of predetermined shape with at least one exposed emitter contact surface for making electrical contact; an emitter metallization region electrically contacting said emitter ring on said exposed emitter contact surface, and substantially covering but not electrically contacting regions of the semiconductor device exterior to said emitter ring.

10. The semiconductor device of claim 9 wherein said emitter ring has been folded to give the form of the perimeter of a double sided comb with emitter finger regions extending toward a central spine region.

11. The semiconductor device of claim 9 wherein the semiconductor body is silicon.

12. The semiconductor device of claim 9 wherein the ring shaped emitter has a lateral dimension measured in the plane of the ring being defined as the difference between the outside boundary of said emitter ring and the adjacent inside boundary measured along a line perpendicular to and connecting the two boundaries, which is less than 0.0076 cm.

13. The semiconductor device of claim 12 wherein the lateral dimension is in the range 0.0025 to 0.0076 cm.

14. The semiconductor device of claim 10 wherein the lateral dimensions in the emitter finger regions measured in the plane of the comb along a line crossing at right angles from one side of an emitter finger region to the other side, have the ratios 2 +_ 1 to 4 + 2 to 2 + 1 for respectively, the emitter width forming one boundary of the finger, the width of the control region lying within the finger and the emitter width forming the other boundary of the emitter finger, the ratios being selected so that the emitter regions have the same width, and the sum of the three ratios remains substantially constant.

15. The semiconductor device of claim 9 wherein the emitter ring comprises at least two segments.

16. The semiconductor device of claim 10 wherein the width of the emitter finger regions and the separation of adjacent emitter finger regions have ratios in the range 5 _+ 1 to 5 +_ 1, the sum of the ratios remaining substantially constant.

OMPI