EP0036960B1 - Méthode et circuits pour la réception et la transmission de blocs de données, en particulier pour des systèmes de chemin de fer - Google Patents

Méthode et circuits pour la réception et la transmission de blocs de données, en particulier pour des systèmes de chemin de fer Download PDF

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Publication number
EP0036960B1
EP0036960B1 EP81101556A EP81101556A EP0036960B1 EP 0036960 B1 EP0036960 B1 EP 0036960B1 EP 81101556 A EP81101556 A EP 81101556A EP 81101556 A EP81101556 A EP 81101556A EP 0036960 B1 EP0036960 B1 EP 0036960B1
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EP
European Patent Office
Prior art keywords
data
recording
delivering means
address
blocks
Prior art date
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Expired
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EP81101556A
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German (de)
English (en)
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EP0036960A1 (fr
Inventor
Wilhelm Ing.-(Grad) Diedrich
Horst Ing.-(Grad) Forstreuter
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Siemens AG
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Siemens AG
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Priority to AT81101556T priority Critical patent/ATE6616T1/de
Publication of EP0036960A1 publication Critical patent/EP0036960A1/fr
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B61—RAILWAYS
    • B61L—GUIDING RAILWAY TRAFFIC; ENSURING THE SAFETY OF RAILWAY TRAFFIC
    • B61L27/00—Central railway traffic control systems; Trackside control; Communication systems specially adapted therefor
    • B61L27/70—Details of trackside communication

Definitions

  • the invention relates to a method for receiving and delivering data blocks, in particular for railway systems, according to the preamble of claim 1 and to a circuit arrangement for performing the method.
  • a telecommunication system with a time multiple line connecting a plurality of subscriber stations and with a timer station (clock generator) is already known (DE-AS 1 804 624) which has multiple time multiple lines on the time multiple line. channels and sends out a synchronization character.
  • the multiple time line is closed in a loop.
  • Each subscriber station is synchronized with the time grid of the timer station on the basis of the synchronization symbol sent out by the timer station in a synchronization channel. Any subscriber station occupies any time multiple channel marked as free by the timer station to establish an outgoing connection.
  • Such a calling subscriber station will place the identifier of the subscriber station to be called, ie the recipient address, on the line in the occupied channel during the establishment of the connection. All unassigned subscriber stations monitor all channels for the receipt of their own license plate, i.e. their own address.
  • a method and a circuit arrangement for transmitting digital message signals from signal transmitters to signal receivers are also known (DE-AS 2446696), for which purpose the message signals are emitted together with an address signal preceding them and specifying an address signal intended for receiving the message signals.
  • a transmission process takes place only when the number of message signals intended for transmission are present in a signal transmitter.
  • the known method in question is a packet switching and transmission system. In this case, too, the address of the only signal receiver for which the relevant message signals are intended is provided with the message signals specified in each case.
  • the relevant message signal block with a number of addresses corresponding to the number of signal receivers in question must also be emitted several times in this case, which sometimes involves a considerable amount of effort.
  • a data exchange method between several processors is known from DE-A 2805705 and GB-A 2013452, in which the individual processors can be connected in succession in a given order.
  • the processor sending in each case optionally calls, after intermittent calls to inactive processors with neighboring addresses, the next processor in the cyclic address sequence that is registered as active.
  • each message also contains information about the sender of the message and the type of message. Knowing the type of this message, possibly in conjunction with the sender address, the receiving partners decide which messages are intended for them and which are not. All receiving partners confirm the error-free receipt of a message, regardless of whether this message was intended for them or not.
  • each reception partner passes a so-called access release to another reception partner in an address-oriented manner, so that the acknowledgment messages caused thereby are issued in a staggered manner in time.
  • the transmitter and the other processors recognize a faulty processor; messages destined for this are subsequently redirected to another processor, which then has to perform the functions of the faulty processor.
  • This known method for data exchange has the advantage that a message can also address several receiving partners at the same time.
  • the receiving partners determine from the analysis of the message whether it is relevant to them; A separate addressing of the receiving partner is no longer necessary.
  • this obvious advantage of the known data exchange method is largely nullified by the fact that with every message all possible receiving partners have to acknowledge correct reception.
  • the functionality of the transmitting / receiving devices integrated into a transmission path is admittedly continuously checked in an advantageous manner via the acknowledgment messages, so that faults can be recognized at an early stage;
  • the time-multiplexed output of the acknowledgment messages the time taken for the transmission paths is extremely high, that is, depending on the time The volume of messages that can be transmitted is limited.
  • the object of the invention is to provide a method according to the preamble of patent claim 1 and a circuit arrangement suitable for carrying out this method, with which data of different amounts can be transmitted between any number of data recording / data output devices integrated into a transmission path while using the shortest transmission times, in which Cyclic addressing of the individual data acquisition / data output devices is possible without the individual data acquisition / data delivery devices having to be called up centrally or decentrally and in the event of a fault individual data acquisition / data delivery devices at least temporarily excluded from the data transmission network, but also effortlessly if required can be phased in again.
  • each data acquisition / data delivery device analyzes the transmitted data blocks with regard to the respectively attached sender address and, upon detection of a data acquisition / data delivery device upstream of it in the transmission cycle, connects to the transmission link after the end of reception as a data delivery device.
  • the particular advantage of the invention can be seen in the fact that the individual data recording / data output devices can automatically recognize and decide when they have to be connected to the transmission link. This makes a continuous functional test of the data acquisition / data output devices possible without the individual data acquisition / data output devices having to call each other for this purpose.
  • the point in time for the connection of a data recording / data output device is determined from the recognition of the sender address of a data recording / data output device upstream in the transmission cycle.
  • the delivery of a data block is carried out only after a certain defined security period after the acquisition of a data block, the address of which in the address sequence of the address of the data acquisition / data delivery device concerned. goes ahead.
  • This advantageously ensures that the processing times of connection devices (modems) connected to the individual data recording / data output devices are taken into account with regard to the task and delivery of data blocks, without causing difficulties in the timing of the transmission of the individual data blocks.
  • This measure has the advantage that when the failed or inoperable data recording / data output devices are put back into operation, there is a simple possibility of accommodating the data blocks to be delivered by these data recording / data output devices in a timely manner in the intended transmission time grid.
  • the last measure considered has the advantage that the operation of the data recording / data output devices which initially failed can be easily synchronized with the transmission time pattern used when they are put back into operation.
  • Each additional time period is preferably chosen to be shorter than the safety time period. As a result, a time gain is achieved in the event of failure of individual data recording / data output devices with regard to the time period after which data blocks are delivered by one and the same data recording / data output device.
  • Each data acquisition / data output device has a data processing device (CPU) with a buffer (FIFO / RAM) and program and data memory (ROM), which analyzes the sender addresses of the data blocks supplied from the transmission link using at least that of its data acquisition / data output device associated address and held in this in a non-destructive readable memory.
  • CPU data processing device
  • FIFO / RAM buffer
  • ROM program and data memory
  • the address transmitted with the respective data block can control the respective data acquisition / data under the control of a microprocessor the input device can be changed by a value of 1 or 2, in order then to be compared with the address of the relevant data acquisition / data output device; if such a comparison shows a correspondence of the addresses compared with one another, then the result obtained can be used to indicate the usability of the data block in question.
  • Usability is understood here to mean that the respective data block in the data acquisition / data output device in question can be used for processing.
  • a display device is expediently provided in each data acquisition / data output device, which allows data to be displayed in the data blocks to be taken into account and data provided by the associated data generation device.
  • This has the advantage that the data information that is important at the location of the respective data acquisition / data output device can be made visible in each data acquisition / data output device. This measure is particularly important for railway systems in which data blocks are transmitted between individual train monitoring areas, which contain train numbers, for example.
  • each data block to be delivered by the respective data acquisition / data delivery device is expediently recorded in a non-destructive readable memory of the data acquisition / data delivery device concerned. This has the advantage that even if the operation of the entire circuit arrangement fails, the addresses of the individual data recording / data output devices are not lost. In the same way, you will also save the information that specifies in the respective data acquisition / data delivery device which addresses of the data blocks from other data acquisition / data delivery devices actually release a detection in the respective data acquisition / data delivery device.
  • the aforementioned memory associated with the respective data recording / data output device preferably also contains an end signal indicating the end of the data block to be transmitted; this end signal is read out from the buffer after the data to be given after the associated address has been given or, in the absence of such data, after the associated address in question and sent to the transmission link.
  • This measure has the advantage that it is not necessary to provide a rigid time grid for the transmission of the data blocks, but rather that data blocks with a different number of data signals can be transmitted.
  • the data processing device of the data recording / data output device can be put into such a control state from the transmission path when a data block is supplied that the data block in question is first buffered in a converter (SPC) and the sender address of this data block is assigned Determination of a recording release can be determined.
  • the data processing device for example a microprocessor of the data acquisition / data delivery device in question, controls the delivery of this data block to the associated data evaluation device upon the determination of a recording release with respect to a data block that has just been recorded. In this way, a relatively simple and nevertheless safe operational sequence is made possible in the respective data recording / data output device with regard to the data blocks supplied to it.
  • a central monitoring arrangement receiving all data blocks is expediently connected to the transmission link, which may in particular be a two-wire transmission line, via a data acquisition / data delivery device, via which the central monitoring arrangement may be able to selectively deliver data blocks to individual data acquisition / data delivery devices.
  • the data blocks or information for the data acquisition / data output device in question that have occurred prior to such a failure are not lost when these are put into operation again.
  • the relevant information or data blocks can be delivered selectively by the central monitoring arrangement to the data recording / data output devices which have been put back into operation.
  • FIG. 1 shows a circuit arrangement in accordance with an embodiment of the invention in a block diagram.
  • This circuit arrangement is used in particular for railway systems in order to transmit data blocks between individual train monitoring areas, which are indicated in FIG. 1 with B51 to Bfn.
  • train monitoring areas may be, for example, stations located on a railway line.
  • the data blocks mentioned preferably include train numbers if the circuit arrangement is a computer train monitoring system or a train number reporting system.
  • the stations or train monitoring areas Bf1 to Bfn to be understood as data generation devices are each connected to an associated data acquisition / data output device MC1 to MCn.
  • the relevant data generation devices Bf1 to Bfn deliver data to the respectively associated data recording / data output device MC1 to MCn, which data are to be transmitted to other data recording / data output devices.
  • this data is information data that is compiled in the form of data blocks or data bytes. This will be discussed in more detail below.
  • the data acquisition / data output devices MC1 to MCn are connected via their individually associated modems Md1 to Mdn to a connection circuit As1 to Asn which establishes a connection to a transmission link, which in the present case may be a two-wire transmission line L1, all of which Connects connection circuits As1 to Asn in the manner indicated in FIG. 1.
  • a connection circuit As1 to Asn which establishes a connection to a transmission link, which in the present case may be a two-wire transmission line L1, all of which Connects connection circuits As1 to Asn in the manner indicated in FIG. 1.
  • the individual connection circuits As1 to Asn can be formed by simple connection circuits via which the modems Md1 to Mdn can be connected directly to the transmission line L1, for example.
  • modems Md1 to Mdn can be formed by conventional modems which convert the data signals fed to them from the data acquisition / data output devices MC1 to MCn into a signal form which is particularly suitable for transmission via the transmission line L1 .
  • the modems Md1 to Mdn convert the transmission signals supplied to them via the transmission line L1 into a form which can be processed by the data acquisition / data output devices MC1 to MCn.
  • a connection circuit Asz is also connected to the transmission line L1 via a transmission line Ln, to which a central monitoring arrangement Uw is connected, specifically via a separate data acquisition / data output device MCz and a modem Mdz.
  • This central monitoring arrangement Uw can be an operating control center in which all data signals are collected which are transmitted via the transmission line L1 and thus via the transmission line Ln.
  • the central monitoring arrangement Uw thus contains, as it were, a mirror image of the data signals supplied to all decentralized data acquisition / output devices MC1 to MCn.
  • FIG. 2 illustrates in a block diagram a possible structure of one of the data acquisition / data output devices MC1 to MCn, MCz indicated in FIG. 1.
  • the dot receiving / data delivery device shown in FIG. 2 is generally designated MC. It has a buffer and evaluation circuit, which includes a buffer FIFO or RAM and a microprocessor CPU with associated program and data memory ROM.
  • the memory FIFO or RAM is a memory which allows the first data signal fed to it on the input side to be output again as the first data signal on the output side.
  • the microprocessor CPU, the memory FIFO / RAM and the memory ROM are connected together to a bus line system which comprises an address bus line AB, a data bus line DB and a control bus line C8.
  • a bus line system which comprises an address bus line AB, a data bus line DB and a control bus line C8.
  • each of these bus lines AB, DB, CB has a plurality of individual lines, for example eight individual lines each.
  • the memory FIFO / RAM is connected in the present case with an access control circuit AC3 on the input side to the address bus line AB, on the input and output sides of the data bus line DB and on the input side to a control line of the control bus line CB.
  • the memory ROM is connected with an access control circuit AC4 on the input side to the address bus line AB and to a control line of the control bus line CB and on the output side to the data bus line DB.
  • the microprocessor CPU serving as a central unit is connected on the output side to both the address bus line AB and the control bus line CB and on the input and output sides to the data bus line DB.
  • a conversion circuit SPC is also connected to the bus line system, which permits a parallel-to-serial conversion and a serial-to-parallel conversion of the signals supplied to the input side thereof in each case.
  • This conversion circuit SPC is connected to the bus line system in FIG. 2 with its parallel signal receiving / output side. With its series signal output / recording side, the conversion circuit SPC is connected to a level conversion circuit or level adjustment circuit LC, which is connected on the input side to a signal input Di and on the output side to a signal output Do of the data recording / data output device MC. With a separate control output So the conversion circuit SPC is connected to a control input INT of the microprocessor CPU. In the present case, this control input is the interrupt input of the microprocessor CPU.
  • the register Reg1 is used to receive the data signals supplied by a data signal input in the data recording / data output device MC.
  • the register Reg2 serves to receive data signals which are fed to this register via the bus line system.
  • the data signals collected in the register Reg1 are routed through the bus line system upon activation of this register Reg1 by the microprocessor CPU in order to also be collected in the FIRO / RAM memory. Data signals received in this memory FIFO / RAM from other data acquisition / data output devices are stored in the associated register Reg2 under the control of the microprocessor CPU.
  • a display device DP is connected to the two registers Reg1 and Reg2, which is indicated as a display device with a series of display fields I ⁇ 2, I ⁇ 1, I, I + 1 and i + 2.
  • the display field 1 for example, data are shown that have been stored in the register Reg1.
  • the other display fields of the display device DP on the other hand, data are displayed that have been stored in the register Reg2. It can be done in such a way that data is displayed in the display field 1-1, which data are emitted by a data acquisition / data output device, which is to be regarded as the data acquisition / data output device MC immediately preceding the data acquisition / data output device MC indicated in FIG.
  • a data block transmitted via the transmission lines comprises a start character STA, which may optionally include a synchronization signal, then a station number or address ADR, which represents the address of the data acquisition / data output device from which the data block in question is output.
  • a block start identifier BAK is provided, which is followed by a block identifier BLK, which may give an indication of the meaning of the subsequent data block area.
  • this data block area comprises z. B.
  • FIG. 3 shows a possible normal case for a data block that contains data information
  • FIG. 4 illustrates the format in the event that no data signals are available for transmission.
  • the data block to be used for a transmission comprises the start character STA, the address ADR of the sending data acquisition / data output device and the end identifier END.
  • the bits forming these characters, but in particular the address ADR are securely stored in at least one memory of the data acquisition / data output device, even after the 3 n data input / data output device in question has been out of operation.
  • the start character STA and the address ADR of this device are stored securely in the memory ROM; the relevant information can be read out of this memory in a non-destructive manner.
  • the end identifier END is stored in accordance with FIG. 2 in the memory ROM so that it can be used as a closing character for the respective transmission.
  • the completely variable addresses of those data acquisition / data output devices whose data are actually to be taken into account in the data acquisition / data output device containing the relevant memory ROM can also be stored.
  • Fig. 5 the normal case is illustrated that all the data acquisition / data output devices provided deliver data blocks ben. According to the assumption, these are eight data recording / data output devices, the data blocks of which are designated by 1,2,3,4,5,6, 7 and 8 in FIG. 5. It can be seen that the data blocks delivered by the individual data acquisition / data output devices can have different lengths. For example, data blocks 2 and 6 have a greater length than each of the other data blocks. The operation may otherwise proceed in such a way that after a data block has been sent out by the eighth data recording / data output device - this data block is designated by 8 - a data block is again sent out by the first data recording / data output device; this data block is indicated in FIG. 5 by 1 '.
  • a security period t1 which may be, for example, 20-60 ms, must have elapsed since the end of the data block that occurred immediately before. This period of time serves to bridge the switching on and switching off processes of the individual data output devices.
  • the following principle is used to have data blocks output in the manner shown in FIG. 5 by the data acquisition / data output devices of the circuit arrangement shown in FIG. 1.
  • the delivery of the data blocks from all data acquisition / data output devices MC1 to MCn takes place in an order which is determined by the order of the addresses which are associated with the individual data acquisition / data output devices.
  • the numbers 1 to 8 used to designate the data blocks in FIG. 5 are also the addresses of the data acquisition / data output devices from which these data blocks are sent, this means that, for example, the data acquisition / data output device with the Address 4 can only send out a data block when the data acquisition / data output device with address 3 has sent out a data block.
  • a data block supplied to the data acquisition / data output device MC via the signal input Di is fed to the conversion circuit SPC after it has been stirred through the level conversion circuit LC.
  • the associated microprocessor CPU is informed of the presence of a data block at its interrupt input INT.
  • the microprocessor CPU then issues an address addressing the converter SPC in order to take over the address of the data block still contained in this converter SPC.
  • the microprocessor CPU can then store this address in one of its internal registers.
  • the microprocessor CPU then fetches the address ADR of its data acquisition / output device from the memory ROM as a further address.
  • Further data blocks can be collected in this memory FIFO / RAM before these data blocks are issued to the register Reg2 by issuing a command corresponding to the previously mentioned command from the memory FIFO / RAM.
  • the microprocessor CPU effects the mapping of the data signals stored in the register Reg1 into the memory FIFO / RAM in order to deliver the relevant data signals at the given time via the conversion circuit SPC and the level converter LC to the transmission line.
  • the last-mentioned point in time for the transmission of a data block from the respective data acquisition / data output device is determined by means of the microprocessor CPU associated with this device. This can be done in the following way. Since each of the data acquisition / data output devices connected to the transmission line according to FIG. 1 is supplied with all data blocks transmitted via the transmission line in question, the microprocessor CPU of the respective data acquisition / data output device can obtain information on which of the other data acquisition / Data delivery devices have delivered data blocks. On the basis of the relevant addresses, the microprocessor CPU of the respective data acquisition / data output device can then decide whether and when it will read the FIFO / RAM readout in the associated memory released data signals.
  • the microprocessor CPU of the respective data acquisition / data output device records the result of the address comparison carried out by it in order to cause the aforementioned readout process when determining an address difference of, for example, 1.
  • the data blocks are delivered by the individual data acquisition / data delivery devices with a safety margin t1 between the end of the data block delivered by any data acquisition / data delivery device and the beginning of the next one in question Data recording / data delivery device to be delivered data block.
  • Adherence to this safety period t1 is effected under the control of the microprocessor CPU of the respective data acquisition / data output device.
  • the microprocessor CPU of the respective data acquisition / data output device can carry out a number of idle cycles after it has determined that the address of the data block last recorded in its data acquisition / data output device is the address which immediately corresponds to the address of its data acquisition / data output device goes ahead.
  • FIG. 6 it is assumed that out of the eight data acquisition / data output devices provided (see FIG. 5), the data acquisition / data output devices with the addresses 5, 7 and 8 have failed. Instead of the data blocks from the relevant data acquisition / data output devices, time periods t2 are observed in FIG. 6, which are to be regarded as additional time periods or transmission delay time periods and which may each have a duration of 20 ms, for example.
  • Additional time periods t2 are observed in a number that corresponds to the number of failed data recording / data output devices. While there is only one additional time period t2 between the data blocks with the addresses 4 and 6, two time periods t2 are maintained between the data blocks with the addresses 6 and 1 (the latter data block is denoted by 1 ').
  • Compliance with the additional time periods t2 can. also z. B. by handling empty cycles by the microprocessor CPU of the respective
  • Data acquisition / data delivery device can be ensured. This can be done as follows. If one starts from a data acquisition / data output device with the address No. 6, the following processes may take place in this device if a data block with the address No. 4 is recorded in it. First of all, the associated microprocessor of the data acquisition / output device No. 6 may execute a number of empty cycles corresponding to the time period t1. If a data block with the address 5 occurs after this time period t1, the microprocessor CPU of the data acquisition / data output device No. has to evaluate this address. On the other hand, if a data block with the address No.
  • the microprocessor CPU of the relevant data acquisition / data output device may carry out a further number of empty cycles corresponding to the time period t2. After this period of time t2, the microprocessor in question then initiates a readout process in the course of which data signals are read out from the associated memory FIFO / RAM.
  • the microprocessor CPU of the intact data recording / data output device can carry out empty cycles with regard to all addresses, as previously explained.
  • Fig. The case is now illustrated that, starting from the conditions according to Fig. 6, the data acquisition / data output device No. is put into operation again.
  • This data recording / data output device No. 7 releases its data block after the safety period t1 has elapsed following the occurrence of the data block 6.
  • the data acquisition / data output device No. 1 only releases a data block 1 'after the two time periods t1 and t2 have elapsed since the data acquisition / data output device No. 8 has still failed.
  • FIGS. 8 and 9 illustrate the case where the transmission line on which the aforementioned eight data acquisition / Data delivery devices are connected, and such an interruption has just occurred that four data acquisition / data delivery devices are connected to each line section.
  • these are the data acquisition / data output devices 1, 2, 3 and 4 and in the case of FIG. 9, the data acquisition / data output devices 5 to 8.
  • the individual data generation devices according to FIG. 1 can contain normal data input devices or teletype machines.
  • the circuits used in the data acquisition / data output devices can be commercially available components which are to be used in connection with microprocessors. USART modules, for example, can be used as conversion circuit SPC.
  • the level conversion circuit LC can, for example, contain a level conversion circuit with transistors which perform level conversion between levels required for MOS circuits and levels required for TTL circuits.
  • the monitoring device Uw then only needs to be supplied with the addresses of the data blocks in question that are to be sent.

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  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Communication Control (AREA)
  • Train Traffic Observation, Control, And Security (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Claims (8)

1. Procédé pour la réception et l'émission de blocs de données dans ou par l'intermédiaire de dispositifs de réception/de transmission de données (MC1, MCn) reliés entre eux par l'intermédiaire d'une voie de transmission (L1), avec des dispositifs associés pour le traitement de données en vue de la formation de signaux de commande pour transmettre et traiter des données de même que pour saisir les adresses (ADR), les adresses désignant au moins l'émetteur correspondant des données et tous les dispositifs de réception de données/d'émission de données étant interrogés et étant susceptibles d'être cycliquement branchés, éventuellement par l'intermédiaire des adresses d'autres dispositifs de réceptionide transmission de données de la voie de transmission, en particulier pour des installations ferroviaires en vue de la transmission de blocs de données entre les différentes régions de surveillance des trains, caractérisé par le fait que chaque dispositif de réception de données/de transmission de données (MC1, MCn) analyse les blocs de données transmis du point de vue de l'adresse de l'émetteur adjointe (ADR) et se branche sur la ligne de transmission en tant que dispositif d'émission de données, après la fin de la réception, lors de l'identification d'un dispositif de réception de données/d'émission de données qui le précède dans le cycle de transmission.
2. Procédé selon la revendication 1, caractérisé par le fait que dans le dispositif de réception de données/d'émission de données concerné (MC1, MCn) on ne procède à l'émission d'un bloc de données qu'après un intervalle de temps de sécurité donné (t1) se soit écoulé après la réception d'un bloc de données, dont l'adresse de l'émetteur (ADR) précède dans l'ordre d'adresses l'adresse du dispositif de réception de données/d'émission de données (MC1, MCn) concernée.
3. Procédé selon la revendication 2, caractérisé par le fait qu'en cas de défection du dispositif de réception de données/d'émission de données (par exemple MC1) qui doit, selon l'ordre d'adresses, être le prochain dispositif de réception de données/d'émission de données à émettre un bloc de données, et qu'en cas de défection éventuelle d'autres dispositifs d'émission de données/réception de données, dans l'ordre d'adresses, on procède à l'émission d'un bloc de données par le premier dispositif de réception de données/d'émission de données capable de fonctionner dans l'ordre d'adresses correspondant, avec un retard d'un nombre d'intervalles de temps supplémentaires (t2) qui correspond au nombre de dispositifs de réception de données/d'émission de données qui ont fait défaut, après l'écoulement de l'intervalle de temps (t1) qui tient compte de l'apparition du dernier bloc de données.
4. Montage pour la mise en oeuvre du procédé selon l'une des revendications 1à 3, caractérisé par le fait que le dispositif de réception de données/d'émission de données (MC) comporte un dispositif pour le traitement de données (CPU) avec mémoire intermédiaire (FIFO/RAM) et mémoire de programme et de données (ROM), qui procèdent à l'analyse des adresses d'émetteur (ADR) des blocs de données amenés par la voie de transmission (L1, Ln), à l'aide d'au moins l'adresse associée à son dispositif de réception de données/d'émission de données (MC) et retenue dans ce dernier, dans une mémoire (ROM) lisible dans effa oement.
5. Montage selon la revendication 4, caractérisé par le fait que le dispositif de réception de données/d'émission de données (MC) comporte un dispositif d'affichage pour afficher des données contenues dans le bloc de données dont il faut tenir compte et des données préparées par le dispositif de production de données (Bf1 à Bfn; Reg1 ).
6. Dispositif selon la revendication 4, caractérisé par le fait que dans la mémoire lisible sans effacement (ROM) est également mémorisé un signal terminal indiquant la fin d'un bloc de données transmis qui est susceptible d'être lu et d'être transmis à la voie de transmission (L1, Ln), à la suite des donnees à transmettre après la transmission de l'adresse correspondante (ADR), ou, en l'absence de telles données, après l'adresse associée correspondante (ADR).
7. Montage selon l'une des revendications 4 à 6, caractérisé par le fait que le dispositif de traitement de données du dispositif de réception de données/d'émission de données est, lors de la fourniture d'un bloc de données à partir de la voie de transmission (L1, Ln), susceptible d'être placé dans un état de commande qui est tel que le bloc de données correspondant est d'abord mémorisé temporairement dans un convertisseur (SPC) et que l'adresse d'émission de ce bloc de données est susceptible d'identification pour déterminer une réception/libération, et que le dispositif de traitement des données (CPU) du dispositif de réception de données/d'émission de données concerné (MC), à la suite de la constatation d'une réception/libération relative d'un bloc de données précisément pris en charge, commande la mémorisation de ce bloc de données dans la mémoire intermédiaire (FIFO/RAM) ou l'envoie de ce bloc de données au dispositif d'évaluation de données correspondant (Reg2, DP).
8. Montage selon l'une des revendications 4 à 7, caractérisé par le fait qu'à la voie de transmission (Ln) est relié, par l'intermédiaire d'un dispositif de réception de données/d'émission de données (MCz), un dispositif central de surveillance (Uw) recevant tous les blocs de données, et par l'intermédiaire duquel le dispositif central de surveillance (Uw) est capable de transmettre, éventuellement de façon sélective, les blocs de données aux différents dispositifs de réception de données/ d'émission de données (MC1 à MCn).
EP81101556A 1980-03-26 1981-03-04 Méthode et circuits pour la réception et la transmission de blocs de données, en particulier pour des systèmes de chemin de fer Expired EP0036960B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT81101556T ATE6616T1 (de) 1980-03-26 1981-03-04 Verfahren und schaltungsanordnung zum aufnehmen und abgeben von datenbloecken, insbesondere fuer eisenbahnanlagen.

Applications Claiming Priority (2)

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DE3011759 1980-03-26
DE19803011759 DE3011759A1 (de) 1980-03-26 1980-03-26 Verfahren und schaltungsanordnung zum aufnehmen und abgeben von datenbloecken, insbesondere fuer eisenbahnanlagen

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EP0036960A1 EP0036960A1 (fr) 1981-10-07
EP0036960B1 true EP0036960B1 (fr) 1984-03-14

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EP (1) EP0036960B1 (fr)
AT (1) ATE6616T1 (fr)
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GB2193022B (en) * 1986-07-24 1990-08-22 Westinghouse Brake & Signal A railway signalling system
CN107819763B (zh) * 2017-11-13 2020-07-31 北京全路通信信号研究设计院集团有限公司 一种基于状态传输数据的交互通信方法
CN114633781A (zh) * 2022-03-07 2022-06-17 湖南中车时代通信信号有限公司 一种高速磁浮列车车载数据控车的方法及相关组件

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GB1187488A (en) * 1967-10-25 1970-04-08 Int Standard Electric Corp Telecommunication System
DE2446696C3 (de) * 1974-09-30 1979-07-26 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren und Schaltungsanordnung zur Übertragung von digitalen Nachrichtensignalen von Signalsendern zu Signalempfängern über eine Koppeleinrichtung
CH632365A5 (de) * 1978-01-30 1982-09-30 Patelhold Patentverwertung Datenaustauschverfahren zwischen mehreren partnern.
DE2805705C2 (de) * 1978-02-10 1987-01-29 Patelhold Patentverwertungs- und Elektro-Holding AG, Glarus Datenübertragungsverfahren zwischen mehreren gleichberechtigten Teilnehmern

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DE3011759A1 (de) 1982-01-21
DE3162566D1 (en) 1984-04-19
ATE6616T1 (de) 1984-03-15
EP0036960A1 (fr) 1981-10-07
DK135381A (da) 1981-09-27

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