EP0036960A1 - Méthode et circuits pour la réception et la transmission de blocs de données, en particulier pour des systèmes de chemin de fer - Google Patents

Méthode et circuits pour la réception et la transmission de blocs de données, en particulier pour des systèmes de chemin de fer Download PDF

Info

Publication number
EP0036960A1
EP0036960A1 EP81101556A EP81101556A EP0036960A1 EP 0036960 A1 EP0036960 A1 EP 0036960A1 EP 81101556 A EP81101556 A EP 81101556A EP 81101556 A EP81101556 A EP 81101556A EP 0036960 A1 EP0036960 A1 EP 0036960A1
Authority
EP
European Patent Office
Prior art keywords
data
recording
output device
address
data output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP81101556A
Other languages
German (de)
English (en)
Other versions
EP0036960B1 (fr
Inventor
Wilhelm Ing.-(Grad) Diedrich
Horst Ing.-(Grad) Forstreuter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to AT81101556T priority Critical patent/ATE6616T1/de
Publication of EP0036960A1 publication Critical patent/EP0036960A1/fr
Application granted granted Critical
Publication of EP0036960B1 publication Critical patent/EP0036960B1/fr
Expired legal-status Critical Current

Links

Images

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B61—RAILWAYS
    • B61L—GUIDING RAILWAY TRAFFIC; ENSURING THE SAFETY OF RAILWAY TRAFFIC
    • B61L27/00—Central railway traffic control systems; Trackside control; Communication systems specially adapted therefor
    • B61L27/70—Details of trackside communication

Definitions

  • the invention relates to a method and a circuit arrangement for receiving and delivering data blocks in or of data acquisition / data output devices connected to one another via a transmission link, each of which is associated with a separate data generation device which outputs data to its data acquisition / data output device, from which the data in question are delivered to the transmission link in the form of data blocks containing at least one address, via which the data blocks are received at least by data recording / data output devices intended for the recording of the data blocks, in particular for railway systems for the transmission of data blocks between individual train monitoring areas.
  • Such a calling subscriber station will place the identifier of the subscriber station to be called, ie the address of the subscriber station to be called, on the line in the channel being used instead of a message. All unassigned subscriber stations then monitor all channels for the receipt of their own identification, that is, their own address. This means that with the data blocks delivered by a calling subscriber station, only one address is given in each case to designate a further subscriber station to be controlled. If data blocks are to be delivered from one calling subscriber station to several subscriber stations to be called, this can only be done in the known telecommunication system in that the relevant message signals or data blocks are issued with a plurality of addresses, that is to say several times. The total occupancy required on the time division line and the circuitry outlay are therefore relatively high.
  • a method and a circuit arrangement for transmitting digital message signals from signal transmitters to signal receivers are also known (DE-AS 24 46 696), for which purpose the message signals are emitted together with an address signal preceding them and specifying an address signal intended for receiving the message signals.
  • a transmission process takes place only when the number of message signals intended for transmission are present in a signal transmitter.
  • the known method in question is a packet switching and transmission system. In this case, too, the address of the only signal receiver for whom the message concerned is provided is provided with the message signals that are emitted Message signals are determined.
  • the relevant message signal block with a number of addresses corresponding to the number of signal receivers in question must also be issued several times in this case, which sometimes involves a not inconsiderable effort.
  • the invention is therefore based on the object of showing a simple way of how one and the same data block can be recorded by a definable number of data signal recording / data signal output devices.
  • the object outlined above is achieved according to the invention in a method of the type mentioned at the outset in that data blocks are delivered by all data acquisition / data output devices in an order determined by the sequence of the addresses associated with the data acquisition / data output devices concerned, in that each data acquisition / data output device Data delivery device that this individually associated address is delivered as part of the data block to be delivered in each case and that in each data acquisition / data delivery device only data blocks with such addresses are added which have a specific, fixed relationship to the address of the respective data acquisition / data delivery device.
  • the invention has the advantage that it is ensured in a relatively simple manner by sending a data block once from a sending data recording / data output device that this data block can be received by desired data signal recording / data signal output devices acting as a receiver without having to do with the relevant one Separate information must also be transmitted to the data block designate the inclusion of this data block in question data signal recording / data signal output devices.
  • the invention makes it possible in a particularly simple manner to determine the data signal recording / data signal output devices intended for the recording of data blocks from certain data signal recording / data signal output devices, and only in the data recording / data output devices to be provided for the recording of the relevant data blocks.
  • the addresses contained in the data blocks supplied in each case are expediently checked in each data recording / data output device in order to determine an actual recording of the relevant data blocks.
  • This measure has the advantage that all the transmitted data blocks can first be recorded in each data recording / data output device in order to then determine by checking whether the data block just recorded should actually be recorded and processed or not.
  • the delivery of a data block is preferably carried out only after a certain defined security period after the acquisition of a data block, the address of which immediately precedes the address sequence of the address of the data acquisition / data output device concerned.
  • This measure has the advantage that when the failed or inoperable data recording / data output devices are put back into operation, there is a simple possibility of accommodating the data blocks to be delivered by these data recording / data output devices in a timely manner in the intended transmission time grid.
  • the expedient measure considered last has the advantage that the operation of the data recording / data output devices which initially failed can be easily synchronized with the transmission time pattern used when they are restarted.
  • Each additional time period is preferably chosen to be shorter than the safety time period.
  • each of the data recording / data output devices connected to a transmission link has a microprocessor-containing intermediate Has memory and evaluation circuit, which is connected to a buffer on the input side of the transmission link and to a data generation device and which is connected on the output side to the transmission link and to a data evaluation device of the relevant data recording / data output device.
  • each data recording / data output device preferably takes over the checking of the addresses of the data blocks supplied from the transmission link. on the basis of at least the address belonging to its data acquisition / data output device and recorded in it.
  • the address transmitted with the respective data block can be changed by a value of 1 or 2 under the control of the microprocessor of the respective data acquisition / data output device, in order then to be compared with the address of the data acquisition / data output device concerned; if such a comparison shows a correspondence of the addresses compared with one another, then the result obtained can be used to indicate the usability of the data block in question.
  • Usability is understood here to mean that the respective data block in the data acquisition / data output device in question can be used for processing.
  • a display device is expediently provided in each data acquisition / data output device, which allows data to be displayed in the data blocks to be taken into account and data provided by the associated data generation device.
  • This has the advantage that the data information that is important at the location of the respective data acquisition / data output device can be made visible in each data acquisition / data output device. This measure is particularly important for railway systems in which data blocks are transmitted between individual train monitoring areas, which contain train numbers, for example.
  • each data block to be delivered by the respective data acquisition / data delivery device is expediently recorded in a non-destructively readable memory of the data acquisition / data delivery device concerned. This has the advantage that even if the operation of the entire circuit arrangement fails, the addresses of the individual data recording / data output devices are not lost. In in the same way, one will also save the information that specifies in the respective data acquisition / data delivery device which addresses of the data blocks from other data acquisition / data delivery devices actually release a detection in the respective data acquisition / data delivery device.
  • the memory associated with the respective data recording / data output device preferably also contains an end signal, which indicates the end of the data block to be transmitted, stored; this end signal is read out from the buffer after the data to be given after the associated address has been given or, in the absence of such data, after the associated address in question and sent to the transmission link.
  • the microprocessor of the respective buffer and evaluation circuit can be set to a separate control input when a data block is supplied from the transmission path into such a control state that the data block in question can first be stored in the associated buffer and the address of this data block Determination of a recording release can be determined.
  • the microprocessor of the relevant data recording / data output device controls the release of this data block to the associated data evaluation device upon the determination of a recording release with respect to a data block that has just been recorded. In this way, a relatively simple and nevertheless safe operational sequence is made possible in the respective data acquisition / data output device with regard to the data blocks supplied to it.
  • Each data delivery / data acquisition device is connected to the transmission line by means of a series-parallel or parallel-series conversion device. This advantageously makes it possible to work in parallel in the respective buffer and evaluation circuit and thus relatively quickly. In addition, this measure does justice to the construction of conventional microprocessors that receive or emit signals in parallel format.
  • the microprocessor of the respective data acquisition / data delivery device allows the transmission of a data block from the data acquisition / data delivery device in question triggering or releasing trigger signals for specified periods of time after the acquisition of a data block by the data acquisition / data delivery device concerned.
  • This has the advantage that the time periods mentioned for the delay in the delivery of data blocks can be provided in a particularly simple manner in the respective data recording / data delivery device.
  • the relevant time periods are expediently provided by including the respective microprocessor in individual program or time loops or by operating a separate payer.
  • separate registers are provided for the recording of data from the associated data generation device and for the recording of the data blocks recorded from other data recording / data output devices in the respective data recording / data output device, which together with the buffer and the microprocessor of the relevant data recording / data output device are connected to a bus line system, on which a memory containing program and control data and a connection circuit connected to the transmission link are also provided are closed.
  • a bus line system on which a memory containing program and control data and a connection circuit connected to the transmission link are also provided are closed.
  • a central monitoring arrangement receiving all data blocks is expediently connected to the transmission link, which may in particular be a two-wire transmission line, via a data acquisition / data delivery device, via which the central monitoring arrangement may be able to selectively deliver data blocks to individual data acquisition / data delivery devices.
  • the data blocks or information for the data acquisition / data output devices concerned which occurred before such a failure, are not lost when these are put into operation again.
  • the relevant information or data blocks can be delivered selectively by the central monitoring arrangement to the data recording / data output devices which have been put back into operation.
  • FIG. 1 shows a circuit arrangement in accordance with an embodiment of the invention in a block diagram.
  • This circuit arrangement is used in particular for railway systems in order to transmit data blocks between individual train monitoring areas, which are indicated in FIG. 1 with Bf1 to Bfn.
  • train monitoring areas may be, for example, train stations located on a railway line.
  • the data blocks mentioned preferably include train numbers if the circuit arrangement is a computer train monitoring system or a train number reporting system.
  • the stations or train monitoring areas Bf1 to Bfn to be understood as data generation devices are each connected to an associated data acquisition / data output device MC1 to MCn.
  • the relevant data generation devices Bf1 to Bfn deliver data to the respectively associated data recording / data output device MC1 to MCn, which data are to be transmitted to other data recording / data output devices.
  • this data is information data that is compiled in the form of data blocks or data bytes. This will be discussed in more detail below.
  • the data acquisition / data output devices MC1 to MCn are connected via them individually associated modems Md1 to Mdn to a connection circuit As1 to Asn which establishes a connection to a transmission link, which in the present case may be a two-wire transmission line L1, which connects all the connection circuits As1 to Asn to one another in the manner indicated in FIG. 1.
  • a transmission link which in the present case may be a two-wire transmission line L1
  • the individual connection circuits As1 to Asn can be formed by simple connection circuits via which the modems Md1 to Mdn can be connected directly to the transmission line L1, for example.
  • modems Md1 to Mdn can be formed by conventional modems which convert the data signals fed to them from the data acquisition / data output devices MC1 to MCn into a signal form which is particularly suitable for transmission via the transmission line L1 .
  • the modems Md1 to Mdn convert the transmission signals supplied to them via the transmission line L1 into a form which can be processed by the data acquisition / data output devices MC1 to MCn.
  • a connection circuit Asz is also connected to the transmission line L1 via a transmission line Ln, to which a central monitoring arrangement Uw is connected, specifically via a separate data acquisition / data output device MCz and a modem Mdz.
  • This central monitoring arrangement Uw can be an operational control center in which all data signals are collected which are transmitted via the transmission line L1 and thus via the transmission line Ln.
  • the central monitoring arrangement Uw thus contains, as it were, a mirror image of the data signals supplied to all the "decentralized" data acquisition / data output devices MC1 to MCn.
  • FIG. 2 is a block diagram of a possible structure of one of the data acquisition / data indicated in Fig. 1 Gabe worn MC1 to MCn, MCz illustrated.
  • the data acquisition / data output device shown in FIG. 2 is generally designated MC. It has a buffer and evaluation circuit, which includes a buffer FIFO or RAM and a microprocessor CPU with associated program and data memory ROM.
  • the memory FIFO or RAM is a memory which allows the first data signal fed to it on the input side to be output again as the first data signal on the output side.
  • the microprocessor CPU, the memory FIFO / RAM and the memory ROM are connected together to a bus line system which comprises an address bus line AB, a data bus line DB and a control bus line CB.
  • a bus line system which comprises an address bus line AB, a data bus line DB and a control bus line CB.
  • each of these bus lines AB, DB, CB has a plurality of individual lines, for example eight individual lines each.
  • the memory FIFO / RAM is connected with an access control circuit AC3 on the input side to the address bus line AB, on the input and output side to the data bus line DB and on the input side to a control line of the control bus line CB.
  • the memory ROM is connected with an access control circuit AC4 on the input side to the address bus line AB and to a control line of the control bus line CB and on the output side to the data bus line DB.
  • the microprocessor CPU serving as the central unit is connected on the output side to both the address bus line AB ′ and the control bus line CB and on the input and output sides to the data bus line DB.
  • a conversion circuit SPC is also connected to the bus line system, which permits a parallel-to-series conversion and a series-to-parallel conversion of the signals fed to it on the input side.
  • This conversion circuit SPC is here with its parallel signal receiving / output side with the bus line system in FIG. 2 connected. With its series signal output / recording side, the conversion circuit SPC is connected to a level conversion circuit or level adjustment circuit LC, which is connected on the input side to a signal input Di and on the output side to a signal output Do of the data recording / data output device MC. With a separate control output So the conversion circuit SPC is connected to a control input INT of the microprocessor CPU. In the present case, this control input is the interrupt input of the microprocessor CPU.
  • the register Reg1 is used to receive the data signals supplied by a data signal input in the data recording / data output device MC.
  • the register Reg2, serves to receive data signals which are fed to this register via the bus line system.
  • the data signals collected in the register Reg1 are passed through the bus line system when the register Reg1 is driven by the microprocessor CPU in order to also be collected in the memory FIFO / RAM. Data signals received in this memory FIFO / RAM from other data acquisition / data output devices are stored in the associated register Reg2 under the control of the microprocessor CPU.
  • a display device DP is connected to the two registers Reg1 and Reg2, which is indicated as a display device with a number of display fields 1-2, 1-1, I, 1 + 1 and 1 + 2.
  • the display field I for example, data are shown that have been stored in the register Reg1.
  • the other display fields of the display device DP on the other hand, data is displayed that has been stored in the register Reg2. It can be done in such a way that in the display field I-1 data are displayed, which are emitted by a data acquisition / data output device which is to be regarded as the data acquisition / data output device MC immediately preceding the data acquisition / data output device MC indicated in FIG. 2.
  • a data block transmitted via the transmission lines comprises a start character STA, which may optionally include a synchronization signal, then a station number or address ADR, which represents the address of the data acquisition / data output device from which the data block in question is output.
  • a block start identifier BAK is provided, which is followed by a block identifier BLK, which may give an indication of the meaning of the subsequent data block area.
  • this data block area comprises, for example, 6 data bytes which are designated with 1.DB, 2.DB, 3.DB, 4.DB, 5.DB and 6.DB.
  • the last character of the data block shown in FIG. 3 is an end identifier END. All of the above-mentioned characters or bytes each contain a fixed one set number of bits; in general, however, it is also possible for the different characters to have a different number of bits.
  • FIG. 3 shows a possible normal case for a data block that contains data information
  • FIG. 4 illustrates the format in the event that no data signals are available for transmission.
  • the data block to be used for a transmission comprises the start character STA, the address ADR of the sending data acquisition / data output device and the end identifier END.
  • the bits forming these characters, but in particular the address ADR are securely stored in at least one memory of the data recording / data output device in order to remain available even after the data recording / data output device concerned has failed.
  • the start character STA and the address ADR of this device are stored securely in the memory ROM; the relevant information can be read from this memory in a non-destructive manner.
  • the end identifier END is stored in accordance with FIG. 2 in the memory ROM so that it can be used as a closing character for the respective transmission. Ables addresses of the data acquisition / data delivery devices to be stored, the data in the memory ROM containing relevant information recording /äbgabe heard actually be taken into account - in this ROM, moreover, completely va can.
  • FIG. 5 illustrates the normal case that all of the data acquisition / data delivery devices provided deliver data blocks. According to the assumption, these are eight data recording / data output devices, the data blocks of which are denoted by 1, 2, 3, 4, 5, 6, 7 and 8 in FIG. 5. It can be seen that the data blocks delivered by the individual data acquisition / data output devices can have different lengths. For example, data blocks 2 and 6 have a greater length than each of the other data blocks. The operation may otherwise proceed in such a way that, after a data block has been sent out by the eighth. Data recording / data output device - this data block is designated by 8 - a data block is again sent out by the first data recording / data output device; this data block is indicated in FIG. 5 by 1 '.
  • a security period t1 which may be, for example, 20-60 ms, must have elapsed since the end of the data block that occurred immediately before. This period of time serves to bridge the switch-on and switch-off processes of the individual data output devices.
  • the following principle is used to have data blocks output in the manner shown in FIG. 5 by the data acquisition / data output devices of the circuit arrangement shown in FIG. 1.
  • the delivery of the data blocks from all data acquisition / data output devices MC1 to MCn takes place in an order which is determined by the order of the addresses which are associated with the individual data acquisition / data output devices.
  • the numbers 1 to 8 used to designate the data blocks in FIG. 5 are also the addresses of the data acquisition / data output devices from which these data blocks are sent, this means that, for example, the data acquisition / data output device with the Address 4 can only send out a data block when the data acquisition / data output device with address 3 has sent out a data block.
  • a data block supplied to the data recording / data output device MC via the signal input Di is fed to the conversion circuit SPC after it has been passed through the level conversion circuit LC.
  • the associated microprocessor CPU is informed of the presence of a data block at its interrupt input INT.
  • the microprocessor CPU then issues an address addressing the converter SPC in order to take over the address of the data block still contained in this converter SPC.
  • the microprocessor CPU can then store this address in one of its internal registers.
  • the microprocessor CPU then fetches the address ADR of its data acquisition / output device from the memory ROM as a further address.
  • the last-mentioned point in time for the transmission of a data block from the respective data acquisition / data output device is determined by means of the microprocessor CPU associated with this device. This can be done in the following way. Since each of the data acquisition / data output devices connected to the transmission line according to FIG. 1 is supplied with all data blocks transmitted via the transmission line in question, the microprocessor CPU of the respective data acquisition / data output device can obtain information on which of the other data acquisition / Data delivery devices have delivered data blocks. On the basis of the relevant addresses, the microprocessor CPU of the respective data acquisition / data output device can then decide whether and when it should release the reading of the data signals stored in the associated memory FIFO / RAM.
  • the microprocessor CPU of the respective data acquisition / data output device records the result of the address comparison carried out by it in order to determine an address difference of for example 1 to effect the previously mentioned readout process.
  • the data blocks are delivered by the individual data acquisition / data delivery devices while maintaining a safety margin t1 between the end of the data block delivered by any data acquisition / data delivery device and the start of the data block issued by the customer Question coming next data recording / data delivery device to be delivered data block.
  • Adherence to this safety period t1 is effected under the control of the microprocessor CPU of the respective data acquisition / data output device.
  • the microprocessor CPU of the respective data acquisition / data output device can carry out a number of idle cycles after it has determined that the address of the data block last recorded in its data acquisition / data output device is the address which immediately corresponds to the address of its data acquisition / data output device goes ahead.
  • FIG. 6 assumes that of the eight data acquisition / data output devices provided (see FIG. 5), the data acquisition / data output devices with the addresses 5, 7 and 8 have failed. Instead of the data blocks from the relevant data acquisition / data output devices, time periods t2 are observed in FIG. 6, which are to be regarded as additional time periods or transmission delay time periods and which may each have a duration of, for example, 20 ms. These additional time periods t2 are observed in a number that corresponds to the number of failed data recording / data output devices. While there is only one additional time period t2 between the data blocks with addresses 4 and 6, two time periods t2 are maintained between the data blocks with addresses 6 and 1 (the latter data block is denoted by 1 ').
  • Compliance with the additional time periods t2 can also be ensured, for example, by handling empty cycles by the microprocessor CPU of the respective data acquisition / data output device. This can be done as follows. If one starts from a data acquisition / data output device with the address No. 6, the following processes may take place in this device if a data block with the address No. 4 is recorded in it. First of all, the associated microprocessor of the data acquisition / output device No. 6 may execute a number of empty cycles corresponding to the time period t1. If a data block with the address 5 occurs after this time period t1, the microprocessor CPU of the data acquisition / data output device No. 6 has to evaluate this address. If, on the other hand, a data block with address no.
  • the microprocessor CPU of the data acquisition / data output device concerned may carry out a further number of empty cycles corresponding to the time period t2. After this period t2, the The microprocessor in question then carries out a readout process in the course of which data signals are read out from the associated memory FIFO / RAM.
  • the microprocessor CPU of the intact data acquisition / data output device can carry out empty cycles with respect to all addresses, as previously explained.
  • FIG. 7 now illustrates the case in which, on the basis of the conditions according to FIG. 6, the data acquisition / output device No. 7 is put into operation again.
  • This data recording / data output device No. 7 releases its data block after the safety period t1 has elapsed following the occurrence of the data block 6.
  • the data acquisition / data output device No. 1 only releases a data block 1 ′ after the two time periods t1 and t2 have elapsed, since the data acquisition / data output device No. 8 has still failed.
  • FIG. 8 Illustrated in Figs. 8 and 9 is the case where the transmission line to which the above-mentioned eight data acquisition / data output devices are connected is interrupted, and such an interruption has just occurred that with each line off Cut four data acquisition / data output devices are connected.
  • these are the data acquisition / data output devices 1, 2, 3 and 4 and in the case of FIG. 9, the data acquisition / data output devices 5 to 8.
  • switch-off process and the switch-on process carried out from a central point, for example by the central monitoring arrangement Uw indicated in FIG. 1.
  • the data recording / data output devices are then switched on again automatically or by bringing one of these devices into the transmission state.
  • the individual data generation devices according to FIG. 1 can be normal data input devices or teletype machines. contain.
  • the circuits used in the data acquisition / data output devices can be commercially available components which are to be used in connection with microprocessors. USART modules, for example, can be used as conversion circuit SPC.
  • the level conversion circuit LC can, for example, contain a level conversion circuit with transistors which perform level conversion between levels required for MOS circuits and levels required for TTL circuits.
  • the monitoring device Uw then only needs to be supplied with the addresses of the relevant data blocks that are to be sent.

Landscapes

  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Communication Control (AREA)
  • Train Traffic Observation, Control, And Security (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
EP81101556A 1980-03-26 1981-03-04 Méthode et circuits pour la réception et la transmission de blocs de données, en particulier pour des systèmes de chemin de fer Expired EP0036960B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT81101556T ATE6616T1 (de) 1980-03-26 1981-03-04 Verfahren und schaltungsanordnung zum aufnehmen und abgeben von datenbloecken, insbesondere fuer eisenbahnanlagen.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3011759 1980-03-26
DE19803011759 DE3011759A1 (de) 1980-03-26 1980-03-26 Verfahren und schaltungsanordnung zum aufnehmen und abgeben von datenbloecken, insbesondere fuer eisenbahnanlagen

Publications (2)

Publication Number Publication Date
EP0036960A1 true EP0036960A1 (fr) 1981-10-07
EP0036960B1 EP0036960B1 (fr) 1984-03-14

Family

ID=6098438

Family Applications (1)

Application Number Title Priority Date Filing Date
EP81101556A Expired EP0036960B1 (fr) 1980-03-26 1981-03-04 Méthode et circuits pour la réception et la transmission de blocs de données, en particulier pour des systèmes de chemin de fer

Country Status (4)

Country Link
EP (1) EP0036960B1 (fr)
AT (1) ATE6616T1 (fr)
DE (2) DE3011759A1 (fr)
DK (1) DK135381A (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2193022A (en) * 1986-07-24 1988-01-27 Westinghouse Brake & Signal Railway signalling system
CN107819763A (zh) * 2017-11-13 2018-03-20 北京全路通信信号研究设计院集团有限公司 一种基于状态传输数据的交互通信方法
CN114633781A (zh) * 2022-03-07 2022-06-17 湖南中车时代通信信号有限公司 一种高速磁浮列车车载数据控车的方法及相关组件

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1804624A1 (de) * 1967-10-25 1969-07-03 Int Standard Electric Corp Fernmelde-,insbesondere Fernsprechanlage
DE2446696A1 (de) * 1974-09-30 1976-04-01 Siemens Ag Verfahren und schaltungsanordnung zur uebertragung von digitalen nachrichtensignalen von signalsendern zu signalempfaengern ueber eine koppeleinrichtung
GB2013452A (en) * 1978-01-30 1979-08-08 Patelhold Patentverwertung System of data exchange between a number of processors
DE2805705A1 (de) * 1978-02-10 1979-08-16 Patelhold Patentverwertung Datenaustauschverfahren zwischen mehreren prozessoren

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1804624A1 (de) * 1967-10-25 1969-07-03 Int Standard Electric Corp Fernmelde-,insbesondere Fernsprechanlage
DE2446696A1 (de) * 1974-09-30 1976-04-01 Siemens Ag Verfahren und schaltungsanordnung zur uebertragung von digitalen nachrichtensignalen von signalsendern zu signalempfaengern ueber eine koppeleinrichtung
GB2013452A (en) * 1978-01-30 1979-08-08 Patelhold Patentverwertung System of data exchange between a number of processors
DE2805705A1 (de) * 1978-02-10 1979-08-16 Patelhold Patentverwertung Datenaustauschverfahren zwischen mehreren prozessoren

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
AUTOMATION AND REMOTE CONTROL, Band 34, Nr. 4, April 1973, Seiten 573-580 New York, U.S.A. G.G. STETSYURA: "Large-scale systems and operations management decentralized coalitional control in data processing systems" *
SIEMENS-ZEITSCHRIFT, Band 48, Nr. 4, Heft 11, 1974, Seiten 856-860 Erlangen, DE. R. BEYERSDORFF: "DUS700, ein neues Fernwirksystem für die Eisenbahnsignaltechnik" *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2193022A (en) * 1986-07-24 1988-01-27 Westinghouse Brake & Signal Railway signalling system
EP0254492A2 (fr) * 1986-07-24 1988-01-27 Westinghouse Brake And Signal Holdings Limited Système de signalisation pour chemin de fer
US4860977A (en) * 1986-07-24 1989-08-29 Westinghouse Brake & Signal Co. Ltd. Railway signalling system
EP0254492A3 (fr) * 1986-07-24 1990-05-23 Westinghouse Brake And Signal Holdings Limited Système de signalisation pour chemin de fer
GB2193022B (en) * 1986-07-24 1990-08-22 Westinghouse Brake & Signal A railway signalling system
CN107819763A (zh) * 2017-11-13 2018-03-20 北京全路通信信号研究设计院集团有限公司 一种基于状态传输数据的交互通信方法
CN107819763B (zh) * 2017-11-13 2020-07-31 北京全路通信信号研究设计院集团有限公司 一种基于状态传输数据的交互通信方法
CN114633781A (zh) * 2022-03-07 2022-06-17 湖南中车时代通信信号有限公司 一种高速磁浮列车车载数据控车的方法及相关组件

Also Published As

Publication number Publication date
DE3011759A1 (de) 1982-01-21
DK135381A (da) 1981-09-27
ATE6616T1 (de) 1984-03-15
DE3162566D1 (en) 1984-04-19
EP0036960B1 (fr) 1984-03-14

Similar Documents

Publication Publication Date Title
DE2503111B2 (de) Verfahren und schaltungsanordnung zur zeitmultiplexen uebertragung von nutzinformationen aus voneinander unabhaengigen quellen
DE2908316A1 (de) Multikonfigurierbares modulares verarbeitungssystem, das mit einem vorverarbeitungssystem integriert ist
EP0329005B1 (fr) Procédé pour l'établissement de circuits virtuels à travers les commutateurs d'un dispositif de commutation à plusieurs étages
CH656275A5 (de) Verfahren und schaltungsanordnung zum uebertragen von datensignalen zwischen datensignalsendern und datensignalempfaengern.
DE2362010A1 (de) Fehleralarm- und -ueberwachungsanlage und verfahren zur fehleralarmausloesung und fehlerueberwachung
DE4221841C2 (de) Überwachungs-Kontrollsystem zur Überwachung mehrerer überwachter Geräte
EP0197312A1 (fr) Méthode d'exploitation de circuit pour centraux de télécommunication, en particulier centraux téléphoniques avec des sous-centraux, en particulier des concentrateurs connectés à des centraux par des canaux de connexion
EP0290894B1 (fr) Méthode de diffusion des tables d'adresses actuelles sur un réseau comportant "n" boucles
EP0426739B1 (fr) Procede d'acquisition d'informations concernant le reseau dans un reseau de transmission numerique et un tel reseau de transmission numerique
EP0036960A1 (fr) Méthode et circuits pour la réception et la transmission de blocs de données, en particulier pour des systèmes de chemin de fer
EP0215276B1 (fr) Procédé et disposition pour transmettre des signaux de données à un groupe de dispositifs de commande appartenant à un système en anneau
DE2810434A1 (de) Zwischenschaltung zwischen synchronen fuehl- und steuermatrizen fuer fernmelde- schaltkennzeichen und einem rechner fuer fernmeldedaten
DE3136495C2 (fr)
DE2601702A1 (de) Verbindungs- und ueberwachungssystem fuer fernmeldevermittlungsstelle
DE2816286C2 (de) Schaltungsanordnung für zentralgesteuerte Fernmeldevermittlungsanlagen, insbesondere Fernsprechvermittlungsanlagen, mit Zentralsteuerwerk und Teilsteuerwerken
DE2813016A1 (de) Vorrichtung zum verarbeiten von fernmeldesignalisierungen
EP0046259B1 (fr) Procédé pour établir des connections de postes d'abonnés ou lignes de transmission reliés à une centrale de commutation de données à convertisseurs de signaux
EP0392245B1 (fr) Adressage automatique d'unités de traitement d'un système numérique de transmission d'informations en assurant la surveillance et/ou la commande
DE3012133A1 (de) Verfahren und schaltungsanordnung zur aufnahme und abgabe von informationsdaten und signalisierungsdaten bei einer programmgesteuerten datenvermittlungsanlage
DE602004005166T2 (de) Verfahren und System zur Handhabung von Ausfällen auf Routerniveau
EP0392246B1 (fr) Système de surveillance et de commande pour systèmes de transmission d'informations numériques avec maître et maître de substitution
DE3012527C2 (fr)
EP0214475A1 (fr) Circuit pour transmettre des signaux de données entre des dispositifs de commande reliées entre eux par un système en anneaux
DE1512443C3 (de) Verfahren zur Weiterleitung von auf mehreren Eingangskanälen eingehenden Informationen auf bestimmte Ausgangskanäle
DE2846130A1 (de) Fernschreib-nebenstellenanlage

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Designated state(s): AT CH DE IT NL

17P Request for examination filed

Effective date: 19811028

ITF It: translation for a ep patent filed

Owner name: STUDIO JAUMANN

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Designated state(s): AT CH DE IT LI NL

REF Corresponds to:

Ref document number: 6616

Country of ref document: AT

Date of ref document: 19840315

Kind code of ref document: T

REF Corresponds to:

Ref document number: 3162566

Country of ref document: DE

Date of ref document: 19840419

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: AT

Payment date: 19850227

Year of fee payment: 5

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: NL

Payment date: 19850331

Year of fee payment: 5

26N No opposition filed
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AT

Effective date: 19860304

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LI

Effective date: 19860331

Ref country code: CH

Effective date: 19860331

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Effective date: 19861001

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Effective date: 19861202

NLV4 Nl: lapsed or anulled due to non-payment of the annual fee