EP0036960A1 - Method and circuitry for reception and transmission of data blocks, especially for railway systems - Google Patents

Abstract

1. Method for recording and delivering of data blocks in or from data recordin/data delivering means (MC1, MCn), connected to each other through a transmission line (L1) with associated data processing means for forming control signals adapted to index and treat data and to take up addresses (ADR), the addresses designating at least the appropriate sender of the data and/or data recording/data delivering means are inter alia informed of the addresses of further data recording/data delivering means of the transmitting line and can be cyclicly switched thereto, more particularly in railway systems for the transmission of data blocks between individual train monitoring ranges, characterized in that each data recording/data delivering means (MC1, MCn) analyzes the transmitted data blocks with regard to the sender address (ADR) attached in each case and on recognizing one of the data recording/data delivering means, which precedes in the transmission cycle, switches itself as data delivering means on to the transmission line after the end of reception.

Description

The invention relates to a method and a circuit arrangement for receiving and delivering data blocks in or of data acquisition / data output devices connected to one another via a transmission link, each of which is associated with a separate data generation device which outputs data to its data acquisition / data output device, from which the data in question are delivered to the transmission link in the form of data blocks containing at least one address, via which the data blocks are received at least by data recording / data output devices intended for the recording of the data blocks, in particular for railway systems for the transmission of data blocks between individual train monitoring areas.

There is already a telecommunication system with a time multiplex line connecting a plurality of subscriber stations and with a timer station (clock generator) known (DE-AS 18 04 624), which determines multiple time multiplex channels on the time multiplex line and for this purpose sends out a synchronization character. The multiple time line is closed in a loop. Each subscriber station is synchronized with the time grid of the timer station on the basis of the synchronization symbol sent out by the timer station in a synchronization channel. Any subscriber station will use any of to establish an outgoing connection the timer position as a freely marked time multiple channel. Such a calling subscriber station will place the identifier of the subscriber station to be called, ie the address of the subscriber station to be called, on the line in the channel being used instead of a message. All unassigned subscriber stations then monitor all channels for the receipt of their own identification, that is, their own address. This means that with the data blocks delivered by a calling subscriber station, only one address is given in each case to designate a further subscriber station to be controlled. If data blocks are to be delivered from one calling subscriber station to several subscriber stations to be called, this can only be done in the known telecommunication system in that the relevant message signals or data blocks are issued with a plurality of addresses, that is to say several times. The total occupancy required on the time division line and the circuitry outlay are therefore relatively high.

A method and a circuit arrangement for transmitting digital message signals from signal transmitters to signal receivers are also known (DE-AS 24 46 696), for which purpose the message signals are emitted together with an address signal preceding them and specifying an address signal intended for receiving the message signals. A transmission process takes place only when the number of message signals intended for transmission are present in a signal transmitter. In principle, the known method in question is a packet switching and transmission system. In this case, too, the address of the only signal receiver for whom the message concerned is provided is provided with the message signals that are emitted Message signals are determined. In order to supply a specific p ^- message signal block to a plurality of signal receivers, the relevant message signal block with a number of addresses corresponding to the number of signal receivers in question must also be issued several times in this case, which sometimes involves a not inconsiderable effort.

The invention is therefore based on the object of showing a simple way of how one and the same data block can be recorded by a definable number of data signal recording / data signal output devices.

The object outlined above is achieved according to the invention in a method of the type mentioned at the outset in that data blocks are delivered by all data acquisition / data output devices in an order determined by the sequence of the addresses associated with the data acquisition / data output devices concerned, in that each data acquisition / data output device Data delivery device that this individually associated address is delivered as part of the data block to be delivered in each case and that in each data acquisition / data delivery device only data blocks with such addresses are added which have a specific, fixed relationship to the address of the respective data acquisition / data delivery device.

The invention has the advantage that it is ensured in a relatively simple manner by sending a data block once from a sending data recording / data output device that this data block can be received by desired data signal recording / data signal output devices acting as a receiver without having to do with the relevant one Separate information must also be transmitted to the data block designate the inclusion of this data block in question data signal recording / data signal output devices. In addition, the invention makes it possible in a particularly simple manner to determine the data signal recording / data signal output devices intended for the recording of data blocks from certain data signal recording / data signal output devices, and only in the data recording / data output devices to be provided for the recording of the relevant data blocks.

The addresses contained in the data blocks supplied in each case are expediently checked in each data recording / data output device in order to determine an actual recording of the relevant data blocks. This measure has the advantage that all the transmitted data blocks can first be recorded in each data recording / data output device in order to then determine by checking whether the data block just recorded should actually be recorded and processed or not.

In the respective data acquisition / data output device, the delivery of a data block is preferably carried out only after a certain defined security period after the acquisition of a data block, the address of which immediately precedes the address sequence of the address of the data acquisition / data output device concerned. This advantageously ensures that the processing times of connection devices (modems) connected to the individual data recording / data output devices are taken into account with regard to the recording and delivery of data blocks, without causing difficulties in the timing of the transmission of the individual data idiots.

It is also of particular advantage if, in the event of failure of the data recording / data output device, which after the address sequence must send out a data block as the next data recording / data output device, and in the event of failure of any further data recording / data output devices in the address sequence, the transmission of a data block from the first operational data recording / data output device in the relevant address sequence by one the number of additional time periods corresponding to the number of the failed data acquisition / data output devices in question is delayed after the end of the safety time period considered after the occurrence of the last data block. This measure has the advantage that when the failed or inoperable data recording / data output devices are put back into operation, there is a simple possibility of accommodating the data blocks to be delivered by these data recording / data output devices in a timely manner in the intended transmission time grid. In other words, this means that the expedient measure considered last has the advantage that the operation of the data recording / data output devices which initially failed can be easily synchronized with the transmission time pattern used when they are restarted. Each additional time period is preferably chosen to be shorter than the safety time period. As a result, a time gain is achieved in the event of failure of individual data acquisition / data output devices with regard to the period of time after which data blocks are delivered by one and the same data acquisition / data output device.

To carry out the method according to the invention, it is expedient to use a circuit arrangement which is characterized in that each of the data recording / data output devices connected to a transmission link has a microprocessor-containing intermediate Has memory and evaluation circuit, which is connected to a buffer on the input side of the transmission link and to a data generation device and which is connected on the output side to the transmission link and to a data evaluation device of the relevant data recording / data output device. This results in the advantage of a relatively low outlay in terms of circuitry for the respective data acquisition / data output device. In principle, one then needs an intermediate storage arrangement and an evaluation arrangement in order to initially record the data blocks transmitted over the transmission link and to check their usability in the relevant data recording / data output device. On the other hand, the relevant arrangements also serve to provide the data blocks to be released from the relevant data acquisition / data output device to the transmission link.

The microprocessor of each data recording / data output device preferably takes over the checking of the addresses of the data blocks supplied from the transmission link. on the basis of at least the address belonging to its data acquisition / data output device and recorded in it. This brings the advantage of a particularly involve effort in determining the usability of the data blocks initially recorded in the respective data recording / data output device over the transmission link. For example, it is easily possible to determine the usability of the data blocks initially recorded in the respective data acquisition / data output device by determining whether the addresses transmitted with these data blocks refer to the addresses A in relation to the address A of the data acquisition / data output device concerned -1, A-2, A + 1 and A + 2, respectively. To make this check too For example, the address transmitted with the respective data block can be changed by a value of 1 or 2 under the control of the microprocessor of the respective data acquisition / data output device, in order then to be compared with the address of the data acquisition / data output device concerned; if such a comparison shows a correspondence of the addresses compared with one another, then the result obtained can be used to indicate the usability of the data block in question. Usability is understood here to mean that the respective data block in the data acquisition / data output device in question can be used for processing.

A display device is expediently provided in each data acquisition / data output device, which allows data to be displayed in the data blocks to be taken into account and data provided by the associated data generation device. This has the advantage that the data information that is important at the location of the respective data acquisition / data output device can be made visible in each data acquisition / data output device. This measure is particularly important for railway systems in which data blocks are transmitted between individual train monitoring areas, which contain train numbers, for example.

The address of each data block to be delivered by the respective data acquisition / data delivery device is expediently recorded in a non-destructively readable memory of the data acquisition / data delivery device concerned. This has the advantage that even if the operation of the entire circuit arrangement fails, the addresses of the individual data recording / data output devices are not lost. In in the same way, one will also save the information that specifies in the respective data acquisition / data delivery device which addresses of the data blocks from other data acquisition / data delivery devices actually release a detection in the respective data acquisition / data delivery device.

The memory associated with the respective data recording / data output device preferably also contains an end signal, which indicates the end of the data block to be transmitted, stored; this end signal is read out from the buffer after the data to be given after the associated address has been given or, in the absence of such data, after the associated address in question and sent to the transmission link. This measure has the advantage that it is not necessary to provide a rigid time grid for the transmission of the data blocks, but rather that data blocks with a different number of data signals can be transmitted.

It is also advantageous if the microprocessor of the respective buffer and evaluation circuit can be set to a separate control input when a data block is supplied from the transmission path into such a control state that the data block in question can first be stored in the associated buffer and the address of this data block Determination of a recording release can be determined. The microprocessor of the relevant data recording / data output device controls the release of this data block to the associated data evaluation device upon the determination of a recording release with respect to a data block that has just been recorded. In this way, a relatively simple and nevertheless safe operational sequence is made possible in the respective data acquisition / data output device with regard to the data blocks supplied to it.

Each data delivery / data acquisition device is connected to the transmission line by means of a series-parallel or parallel-series conversion device. This advantageously makes it possible to work in parallel in the respective buffer and evaluation circuit and thus relatively quickly. In addition, this measure does justice to the construction of conventional microprocessors that receive or emit signals in parallel format.

The microprocessor of the respective data acquisition / data delivery device allows the transmission of a data block from the data acquisition / data delivery device in question triggering or releasing trigger signals for specified periods of time after the acquisition of a data block by the data acquisition / data delivery device concerned. This has the advantage that the time periods mentioned for the delay in the delivery of data blocks can be provided in a particularly simple manner in the respective data recording / data delivery device. The relevant time periods are expediently provided by including the respective microprocessor in individual program or time loops or by operating a separate payer.

Expediently, separate registers are provided for the recording of data from the associated data generation device and for the recording of the data blocks recorded from other data recording / data output devices in the respective data recording / data output device, which together with the buffer and the microprocessor of the relevant data recording / data output device are connected to a bus line system, on which a memory containing program and control data and a connection circuit connected to the transmission link are also provided are closed. This has the advantage that conventional microprocessor connection structures can be used in a particularly simple manner.

A central monitoring arrangement receiving all data blocks is expediently connected to the transmission link, which may in particular be a two-wire transmission line, via a data acquisition / data delivery device, via which the central monitoring arrangement may be able to selectively deliver data blocks to individual data acquisition / data delivery devices.

This can advantageously ensure that in the event of failure of the individual decentralized data acquisition / data output devices, the data blocks or information for the data acquisition / data output devices concerned, which occurred before such a failure, are not lost when these are put into operation again. In this case, the relevant information or data blocks can be delivered selectively by the central monitoring arrangement to the data recording / data output devices which have been put back into operation. Although this presupposes that the central monitoring arrangement has knowledge of the failure of the individual data acquisition / data output devices, this is, however, possible by simple monitoring of the addresses of all data blocks transmitted over the transmission link.

The invention is explained in more detail below with reference to drawings.

• Fig. 1 shows in a block diagram a circuit arrangement according to the invention.
• FIG. 2 shows in a block diagram a possible structure of one of the circuit arrangements shown in FIG
• Fig. 1 used data acquisition / data output devices.
• FIG. 3 shows a diagram of a possible structure of one of the data blocks transmitted in the circuit arrangement according to FIG. 1.
• Fig. 4 is a diagram showing the structure of a _possible, further data block.
• 5 to 9 illustrate the transmission of individual data blocks in a circuit arrangement according to FIG. 1 on the basis of time diagrams.

1 shows a circuit arrangement in accordance with an embodiment of the invention in a block diagram. This circuit arrangement is used in particular for railway systems in order to transmit data blocks between individual train monitoring areas, which are indicated in FIG. 1 with Bf1 to Bfn. These train monitoring areas may be, for example, train stations located on a railway line. In this case, the data blocks mentioned preferably include train numbers if the circuit arrangement is a computer train monitoring system or a train number reporting system.

In the circuit arrangement shown in FIG. 1, the stations or train monitoring areas Bf1 to Bfn to be understood as data generation devices are each connected to an associated data acquisition / data output device MC1 to MCn. The relevant data generation devices Bf1 to Bfn deliver data to the respectively associated data recording / data output device MC1 to MCn, which data are to be transmitted to other data recording / data output devices. In the present case, this data is information data that is compiled in the form of data blocks or data bytes. This will be discussed in more detail below.

The data acquisition / data output devices MC1 to MCn are connected via them individually associated modems Md1 to Mdn to a connection circuit As1 to Asn which establishes a connection to a transmission link, which in the present case may be a two-wire transmission line L1, which connects all the connection circuits As1 to Asn to one another in the manner indicated in FIG. 1. This means that the individual connection circuits As1 to Asn can be formed by simple connection circuits via which the modems Md1 to Mdn can be connected directly to the transmission line L1, for example. With regard to the modems Md1 to Mdn, it should be noted that these can be formed by conventional modems which convert the data signals fed to them from the data acquisition / data output devices MC1 to MCn into a signal form which is particularly suitable for transmission via the transmission line L1 . On the other hand, the modems Md1 to Mdn convert the transmission signals supplied to them via the transmission line L1 into a form which can be processed by the data acquisition / data output devices MC1 to MCn.

A connection circuit Asz is also connected to the transmission line L1 via a transmission line Ln, to which a central monitoring arrangement Uw is connected, specifically via a separate data acquisition / data output device MCz and a modem Mdz. This central monitoring arrangement Uw can be an operational control center in which all data signals are collected which are transmitted via the transmission line L1 and thus via the transmission line Ln. The central monitoring arrangement Uw thus contains, as it were, a mirror image of the data signals supplied to all the "decentralized" data acquisition / data output devices MC1 to MCn.

In Fig. 2 is a block diagram of a possible structure of one of the data acquisition / data indicated in Fig. 1 Gabeeinrichtung MC1 to MCn, MCz illustrated. The data acquisition / data output device shown in FIG. 2 is generally designated MC. It has a buffer and evaluation circuit, which includes a buffer FIFO or RAM and a microprocessor CPU with associated program and data memory ROM. The memory FIFO or RAM is a memory which allows the first data signal fed to it on the input side to be output again as the first data signal on the output side.

The microprocessor CPU, the memory FIFO / RAM and the memory ROM are connected together to a bus line system which comprises an address bus line AB, a data bus line DB and a control bus line CB. In the present case, each of these bus lines AB, DB, CB has a plurality of individual lines, for example eight individual lines each. In the present case, the memory FIFO / RAM is connected with an access control circuit AC3 on the input side to the address bus line AB, on the input and output side to the data bus line DB and on the input side to a control line of the control bus line CB. The memory ROM is connected with an access control circuit AC4 on the input side to the address bus line AB and to a control line of the control bus line CB and on the output side to the data bus line DB. The microprocessor CPU serving as the central unit is connected on the output side to both the address bus line AB ′ and the control bus line CB and on the input and output sides to the data bus line DB.

A conversion circuit SPC is also connected to the bus line system, which permits a parallel-to-series conversion and a series-to-parallel conversion of the signals fed to it on the input side. This conversion circuit SPC is here with its parallel signal receiving / output side with the bus line system in FIG. 2 connected. With its series signal output / recording side, the conversion circuit SPC is connected to a level conversion circuit or level adjustment circuit LC, which is connected on the input side to a signal input Di and on the output side to a signal output Do of the data recording / data output device MC. With a separate control output So the conversion circuit SPC is connected to a control input INT of the microprocessor CPU. In the present case, this control input is the interrupt input of the microprocessor CPU.

Two registers Reg1 and Reg2 are also connected to the bus line system via access control circuits AC1 and AC2, respectively. The register Reg1 is used to receive the data signals supplied by a data signal input in the data recording / data output device MC. The register Reg2, on the other hand, serves to receive data signals which are fed to this register via the bus line system. The data signals collected in the register Reg1 are passed through the bus line system when the register Reg1 is driven by the microprocessor CPU in order to also be collected in the memory FIFO / RAM. Data signals received in this memory FIFO / RAM from other data acquisition / data output devices are stored in the associated register Reg2 under the control of the microprocessor CPU.

A display device DP is connected to the two registers Reg1 and Reg2, which is indicated as a display device with a number of display fields 1-2, 1-1, I, 1 + 1 and 1 + 2. In the display field I, for example, data are shown that have been stored in the register Reg1. In the other display fields of the display device DP, on the other hand, data is displayed that has been stored in the register Reg2. It can be done in such a way that in the display field I-1 data are displayed, which are emitted by a data acquisition / data output device which is to be regarded as the data acquisition / data output device MC immediately preceding the data acquisition / data output device MC indicated in FIG. 2. In the display field 1-2, data are displayed which have been delivered by a data recording / data output device which is still preceding. In contrast, in the display field 1 + 1 and in the display field 1 + 2, data can be displayed which are emitted by two data acquisition / data output devices which follow the present data acquisition / data output device. As the terms used above, "go ahead" and "followers" are understood to be from the following functional description of erläuter _- are still seen th circuitry.

Before going into the mode of operation of the circuit arrangements explained, first consider the format in which data signals can be transmitted via the transmission lines L1, Ln according to FIG. 1. A possible data format is illustrated in FIG. Thereafter, a data block transmitted via the transmission lines comprises a start character STA, which may optionally include a synchronization signal, then a station number or address ADR, which represents the address of the data acquisition / data output device from which the data block in question is output. Following the address ADR, a block start identifier BAK is provided, which is followed by a block identifier BLK, which may give an indication of the meaning of the subsequent data block area. According to FIG. 3, this data block area comprises, for example, 6 data bytes which are designated with 1.DB, 2.DB, 3.DB, 4.DB, 5.DB and 6.DB. The last character of the data block shown in FIG. 3 is an end identifier END. All of the above-mentioned characters or bytes each contain a fixed one set number of bits; in general, however, it is also possible for the different characters to have a different number of bits.

While FIG. 3 shows a possible normal case for a data block that contains data information, FIG. 4 illustrates the format in the event that no data signals are available for transmission. In this case, the data block to be used for a transmission comprises the start character STA, the address ADR of the sending data acquisition / data output device and the end identifier END. With regard to the last-mentioned characters, it should also be noted that the bits forming these characters, but in particular the address ADR, are securely stored in at least one memory of the data recording / data output device in order to remain available even after the data recording / data output device concerned has failed. Thus, in the circuit arrangement shown in FIG. 2, the start character STA and the address ADR of this device are stored securely in the memory ROM; the relevant information can be read from this memory in a non-destructive manner. The end identifier END is stored in accordance with FIG. 2 in the memory ROM so that it can be used as a closing character for the respective transmission. Ables addresses of the data acquisition / data delivery devices to be stored, the data in the memory ROM containing relevant information recording / Datenäbgabeeinrichtung actually be taken into account _- in this ROM, moreover, completely va can.

The mode of operation of the circuit arrangement according to the invention is explained below with reference to the diagrams shown in FIGS. 5 to 9. The course of data blocks (plotted in the ordinate direction S) as a function of time (in the abscissa direction t) is illustrated in these diagrams.

FIG. 5 illustrates the normal case that all of the data acquisition / data delivery devices provided deliver data blocks. According to the assumption, these are eight data recording / data output devices, the data blocks of which are denoted by 1, 2, 3, 4, 5, 6, 7 and 8 in FIG. 5. It can be seen that the data blocks delivered by the individual data acquisition / data output devices can have different lengths. For example, data blocks 2 and 6 have a greater length than each of the other data blocks. The operation may otherwise proceed in such a way that, after a data block has been sent out by the eighth. Data recording / data output device - this data block is designated by 8 - a data block is again sent out by the first data recording / data output device; this data block is indicated in FIG. 5 by 1 '. Before each data acquisition / data output device begins to transmit a data block, a security period t1, which may be, for example, 20-60 ms, must have elapsed since the end of the data block that occurred immediately before. This period of time serves to bridge the switch-on and switch-off processes of the individual data output devices.

The following principle is used to have data blocks output in the manner shown in FIG. 5 by the data acquisition / data output devices of the circuit arrangement shown in FIG. 1. The delivery of the data blocks from all data acquisition / data output devices MC1 to MCn takes place in an order which is determined by the order of the addresses which are associated with the individual data acquisition / data output devices. Assuming that the numbers 1 to 8 used to designate the data blocks in FIG. 5 are also the addresses of the data acquisition / data output devices from which these data blocks are sent, this means that, for example, the data acquisition / data output device with the Address 4 can only send out a data block when the data acquisition / data output device with address 3 has sent out a data block.

According to the method principle explained at the outset, which is used in the present case, only data blocks with very specific addresses are now recorded in each data recording / data output device, i.e. with addresses that are in a certain fixed relationship to the address of the respective data acquisition / data output device. For this purpose, the addresses of the data blocks supplied to the respective data acquisition / data output device are checked. To explain the sequence of such a process, reference is made again to FIG. 2.

2, a data block supplied to the data recording / data output device MC via the signal input Di is fed to the conversion circuit SPC after it has been passed through the level conversion circuit LC. In addition, the associated microprocessor CPU is informed of the presence of a data block at its interrupt input INT. The microprocessor CPU then issues an address addressing the converter SPC in order to take over the address of the data block still contained in this converter SPC. The microprocessor CPU can then store this address in one of its internal registers. The microprocessor CPU then fetches the address ADR of its data acquisition / output device from the memory ROM as a further address. These two addresses can then be compared in the arithmetic and logic unit of the microprocessor CPU in accordance with a program, the program steps of which the microprocessor CPU may take from the memory ROM. If it is established in the course of such a comparison that the address taken from the conversion circuit SPC belongs to a data block that can be used in the present data acquisition / data output device, the microprocessor CPU issues a command with an address designating the conversion circuit SPC as a data output device and with one the address designating the memory FIFO / RAM as the data signal recording device. After execution of the relevant command, the data block that was previously recorded by the conversion circuit SPC is then stored in the memory FIFO / RAM. Further data blocks can be collected in this FIFO / RAM memory before these data blocks are issued to the register Reg2 by issuing a command corresponding to the previously mentioned command from the FIFO / RAM memory. By means of an analog command control, the microprocessor CPU effects the mapping of the data signals stored in the register Reg1 into the memory FIFO / RAM in order to deliver the relevant data signals at the given time via the conversion circuit SPC and the level converter LC to the transmission line.

The last-mentioned point in time for the transmission of a data block from the respective data acquisition / data output device is determined by means of the microprocessor CPU associated with this device. This can be done in the following way. Since each of the data acquisition / data output devices connected to the transmission line according to FIG. 1 is supplied with all data blocks transmitted via the transmission line in question, the microprocessor CPU of the respective data acquisition / data output device can obtain information on which of the other data acquisition / Data delivery devices have delivered data blocks. On the basis of the relevant addresses, the microprocessor CPU of the respective data acquisition / data output device can then decide whether and when it should release the reading of the data signals stored in the associated memory FIFO / RAM. For this it is sufficient if the microprocessor CPU of the respective data acquisition / data output device records the result of the address comparison carried out by it in order to determine an address difference of for example 1 to effect the previously mentioned readout process. With reference to the diagram shown in FIG. 5, this means that, for example, if a data block with the address 4 has just been recorded in the data acquisition / data output device with the address 4, no read-out operation has yet been carried out with regard to the associated memory FIFO / RAM will, however, that such a read-out process is carried out if a data block with the address 3 has been recorded in the relevant data recording / data output device (No. 4).

As already mentioned above in connection with FIG. 5, the data blocks are delivered by the individual data acquisition / data delivery devices while maintaining a safety margin t1 between the end of the data block delivered by any data acquisition / data delivery device and the start of the data block issued by the customer Question coming next data recording / data delivery device to be delivered data block. Adherence to this safety period t1 is effected under the control of the microprocessor CPU of the respective data acquisition / data output device. For this purpose, the microprocessor CPU of the respective data acquisition / data output device can carry out a number of idle cycles after it has determined that the address of the data block last recorded in its data acquisition / data output device is the address which immediately corresponds to the address of its data acquisition / data output device goes ahead.

In the circuit arrangement shown in FIG. 1, it can happen that at least one of the data acquisition / data output devices MC1 to MCn fails, so that even a data block with the format shown in FIG. 4 cannot be delivered by this device. Such a case is illustrated in FIG. 6. According to

FIG. 6 assumes that of the eight data acquisition / data output devices provided (see FIG. 5), the data acquisition / data output devices with the addresses 5, 7 and 8 have failed. Instead of the data blocks from the relevant data acquisition / data output devices, time periods t2 are observed in FIG. 6, which are to be regarded as additional time periods or transmission delay time periods and which may each have a duration of, for example, 20 ms. These additional time periods t2 are observed in a number that corresponds to the number of failed data recording / data output devices. While there is only one additional time period t2 between the data blocks with addresses 4 and 6, two time periods t2 are maintained between the data blocks with addresses 6 and 1 (the latter data block is denoted by 1 ').

Compliance with the additional time periods t2 can also be ensured, for example, by handling empty cycles by the microprocessor CPU of the respective data acquisition / data output device. This can be done as follows. If one starts from a data acquisition / data output device with the address No. 6, the following processes may take place in this device if a data block with the address No. 4 is recorded in it. First of all, the associated microprocessor of the data acquisition / output device No. 6 may execute a number of empty cycles corresponding to the time period t1. If a data block with the address 5 occurs after this time period t1, the microprocessor CPU of the data acquisition / data output device No. 6 has to evaluate this address. If, on the other hand, a data block with address no. 5 does not occur, the microprocessor CPU of the data acquisition / data output device concerned may carry out a further number of empty cycles corresponding to the time period t2. After this period t2, the The microprocessor in question then carries out a readout process in the course of which data signals are read out from the associated memory FIFO / RAM.

The operations fully described above are performed in the data acquisition / output device No. 1, the microprocessor CPU of which, following the occurrence of a data block with the address No. 6, executes empty cycles corresponding to the time periods t1 + t2 + t2 before it executes effectively controls or releases a readout process.

In order to be able to take into account the time periods t1 and t2 given above even in the event that a large number of data acquisition / data output devices has failed, the microprocessor CPU of the intact data acquisition / data output device can carry out empty cycles with respect to all addresses, as previously explained.

FIG. 7 now illustrates the case in which, on the basis of the conditions according to FIG. 6, the data acquisition / output device No. 7 is put into operation again. This data recording / data output device No. 7 releases its data block after the safety period t1 has elapsed following the occurrence of the data block 6. The data acquisition / data output device No. 1 only releases a data block 1 ′ after the two time periods t1 and t2 have elapsed, since the data acquisition _/ data output device No. 8 has still failed.

Illustrated in Figs. 8 and 9 is the case where the transmission line to which the above-mentioned eight data acquisition / data output devices are connected is interrupted, and such an interruption has just occurred that with each line off Cut four data acquisition / data output devices are connected. In the case of FIG. 8, these are the data acquisition / data output devices 1, 2, 3 and 4 and in the case of FIG. 9, the data acquisition / data output devices 5 to 8. Analogously to the relationships explained in connection with FIGS. 5 and 6, 8 and 9 between the individual data blocks the time period t1 or multiple times the time period t2. It should be apparent here that the groups of data recording / data output devices located on the two line sections each represent a functional arrangement. If the relevant line sections are then connected to one another again, as can be seen from a comparative examination of FIGS. 8 and 9, two data blocks from different data recording / data output devices occur on the common transmission line at certain times. In order to eliminate this malfunction and to bring about conditions again, as illustrated in FIG. 5, it is expedient to proceed in such a way that all the data recording / data output devices connected to the transmission line are first switched off, in order then to be put into operation again in succession. Switching off can take place in that triggering commands can be formed in all data acquisition / data output devices by plausibility checks, for example of the addresses that occur, or by determining multiple faults. However, it is also possible to have the switch-off process and the switch-on process carried out from a central point, for example by the central monitoring arrangement Uw indicated in FIG. 1. The data recording / data output devices are then switched on again automatically or by bringing one of these devices into the transmission state.

In conclusion, it should also be noted that all the arrangement or circuits used to implement the circuit arrangements described above can be formed by commercially available components or devices. For example, the individual data generation devices according to FIG. 1 can be normal data input devices or teletype machines. contain. The circuits used in the data acquisition / data output devices can be commercially available components which are to be used in connection with microprocessors. USART modules, for example, can be used as conversion circuit SPC. The level conversion circuit LC can, for example, contain a level conversion circuit with transistors which perform level conversion between levels required for MOS circuits and levels required for TTL circuits. The monitoring device Uw indicated in FIG. 1 can comprise a register arrangement, which may represent an input / output register, in which all data blocks recorded via the associated data recording / data output device MCz can be stored, in order to be able to use the relevant data recording / data output device MCz if necessary to be delivered again. For the selective delivery of such data blocks, the monitoring device Uw then only needs to be supplied with the addresses of the relevant data blocks that are to be sent.

Claims (14)

1.Method for receiving and delivering data blocks in or of data acquisition / data delivery devices connected to one another via a transmission link, each of which is associated with a separate data generation device which delivers the data to its data acquisition / data delivery device, of which the relevant data in the form of at least data blocks containing an address are delivered to the transmission link, via which the data blocks are received at least by data recording / data delivery devices intended for the recording of the data blocks, in particular for railway systems for the transmission of data blocks between individual train monitoring areas, characterized in that all data recording / data delivery devices (MC1, MCn) data blocks are delivered in an order determined by the order of the relevant data acquisition / data output devices (MC1, MCn) associated addresses,
that from each data acquisition / data delivery device (MC1, MCn) the address assigned to this individually as part of the data block to be delivered in each case and that in each data acquisition / data delivery device (MC1, MCn) only data blocks with addresses that are recorded in a certain one fixed relationship to the address of the respective data acquisition / data output device (MC1, MCn). 2. The method according to claim 1, characterized in that in each data recording / data output device (MC1, MCn) the addresses contained in the respectively supplied data blocks are checked to determine an actual recording of the data blocks in question. 3. The method according to claim 1 or 2, characterized in that in the respective data recording / data output device (MC1, MCn) the delivery of a data block is made only after a certain defined security period (t1) after the inclusion of a data block, the address of which in the addresses -The sequence of the address of the relevant data acquisition / data output device (MC1, MCn) immediately precedes. 4. The method according to claim 3, characterized in that in the event of failure of the data recording / data output device (for example MC1), which has to send out a data block as the next data recording / data output device according to the address sequence, and in the event of failure of any further data recording / data output devices in the address order, the transmission of a data block from the first operational data recording / data output device in the relevant address order by a number of additional time periods (t2) corresponding to the number of the relevant data recording / data output devices (MC) after the occurrence of the security period (t1) taken into account in the last data block. 5. Circuit arrangement for performing the method according to one of claims 1 to 4, characterized in that each of the data acquisition / data output devices (MC1 to MCn; MC) connected to a transmission link (L1, Ln) has a buffer memory containing a microprocessor (CPU). and evaluation circuit (FIFO / RAM, CPU), which is connected to a buffer (FIFO / RAM) on the input side on the transmission path (L1, Ln) and to a data generation device (Bf1 to Bfn; Reg1) and which is connected on the output side to the transmission path ( L1, Ln) and is connected to a data evaluation device (Reg2, DP) of the relevant data acquisition / data output device (MC). 6. Circuit arrangement according to claim 5, characterized in that the microprocessor (CPU) of each data acquisition / data output device (MC) checking the addresses of the data blocks supplied by the transmission link (L1, Ln) forth based on at least that of its data acquisition / data output device (MC ) associated and recorded in this address (ADR). 7. Circuit arrangement according to claim 6, characterized in that in each data acquisition / data output device (MC) a display device (DP) is provided which contains data contained in the data blocks to be taken into account and data provided by the associated data generation device (Bf1 to Bfn; Reg1) allowed to display. 8. Circuit arrangement according to claim 6 or 7, characterized in that the address of each of the respective data acquisition / data delivery device (MC) to be delivered data block in a non-destructively readable memory (ROM) of the relevant data acquisition / data delivery device (MC) is securely held. 9. Circuit arrangement according to claim 8, characterized in that said memory (ROM) also contains an end signal (END) indicating the end of the respective data block to be transmitted, which is stored following the data to be emitted after the associated address (ADR) has been emitted or in the absence of such data afterwards can be read from the intermediate memory (FIFO) to the relevant associated address (ADR) and can be output to the transmission link (L1, Ln). 10. Circuit arrangement according to one of claims 5 to 9, characterized in that the .Microprocessor (CPU) at a separate control input (INT) when a data block is supplied from the transmission path (L1, Ln) can be put into such a control state that the the data block in question is first buffered and the address of this data block can be determined for determining a recording release, and that the microprocessor (CPU) of the data recording / data delivery device (MC) concerned determines the recording of a recording release with respect to a data block just recorded Controls data block in the associated buffer (FIFO / RAM) or the delivery of this data block to the associated data evaluation device (Reg2, DP). 11. Circuit arrangement according to one of claims 5 to 10, characterized in that each data acquisition / data output device (MC) by means of a series-parallel or parallel-series conversion device (SPC) connected to the transmission link (L'1, Ln) is. 12. Circuit arrangement according to one of claims 5 to 11, characterized in that the microprocessor (CPU) of the respective data acquisition / data output device (MC) the release of a data block from the relevant data acquisition / data output device (MC) releasing or effecting trigger signals by specified Time periods (t1, t2) after recording a data block by the relevant data recording / data output device (MC) can be effectively controlled. 13. Circuit arrangement according to one of claims 5 to 12, characterized in that for the recording of data from the associated data generating device (Bf1 to Bfn) and for the recording of data blocks received by other data recording / data output devices forth in the respective data recording / data output device (MC) separate registers (Reg1, Reg2) are provided, which are connected to a bus line system (AB, DB, CB) together with the buffer (FIFO / RAM) and the microprocessor (CPU) of the relevant data acquisition / data output device (MC) , to which a memory (ROM) containing program and control data and a connection circuit (SPC, LC, MD1 to MDn) connected to the transmission link (L1, Ln) are also connected. 14. Circuit arrangement according to one of claims 5 to 13, characterized in that with the transmission path (Ln) a central monitoring arrangement (Uw) receiving all data blocks is connected via a data acquisition / data output device (MCz) via which the central monitoring arrangement (Uw) if necessary, it can selectively deliver data blocks to individual data acquisition / data output devices (MC1 to MCn).

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