EP0001038A1 - Procédé de fabrication d'un masque de silicium et son utilisation - Google Patents

Procédé de fabrication d'un masque de silicium et son utilisation Download PDF

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Publication number
EP0001038A1
EP0001038A1 EP78100294A EP78100294A EP0001038A1 EP 0001038 A1 EP0001038 A1 EP 0001038A1 EP 78100294 A EP78100294 A EP 78100294A EP 78100294 A EP78100294 A EP 78100294A EP 0001038 A1 EP0001038 A1 EP 0001038A1
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EP
European Patent Office
Prior art keywords
mask
layer
substrate
silicon
thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP78100294A
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German (de)
English (en)
Other versions
EP0001038B1 (fr
Inventor
Ingrid Emese Magdo
Steven Magdo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
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International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP0001038A1 publication Critical patent/EP0001038A1/fr
Application granted granted Critical
Publication of EP0001038B1 publication Critical patent/EP0001038B1/fr
Expired legal-status Critical Current

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/20—Masks or mask blanks for imaging by charged particle beam [CPB] radiation, e.g. by electron beam; Preparation thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching

Definitions

  • the invention relates to a mask made of silicon for use in the production of, in particular, integrated circuits, which consists of a thin layer which has openings in accordance with the mask pattern and a framework formed from ribs supporting the thin layer, a method for producing such a layer Mask and the use of such a mask in particular.
  • Integrated circuits are typically created using photolithographic fabrication techniques.
  • a photoresist pattern must be generated on the substrate in which the integrated circuit is to be produced before each manufacturing step, in which the substrate is only changed in certain areas according to a defined pattern.
  • the photoresist pattern can define various types of metallic patterns which are produced by means of photolithographic etching techniques, or it can serve to produce patterns in insulating layers which have the task of preventing the penetration of conductivity-determining impurities into the substrate limit or define the areas of electrical insulation.
  • the fabrication of any conventional state-of-the-art integrated circuit requires dozens of such photolithographic masking steps. Each of these masking steps is complex.
  • a mask which can be separated from the substrate and through which the photoresist layer is irradiated, such a mask being, for example, a conventional metal mask on a glass substrate.
  • a mask being, for example, a conventional metal mask on a glass substrate.
  • each of these steps! in which the photoresist is exposed requires a fairly difficult alignment of the glass mask with the substrate.
  • Part of the difficulty with such alignment is that an alignment mark on the substrate must be aligned with a corresponding mark on the underside of the glass mask.
  • the image of these alignment indicators must pass through a 1.27 to 1.524 mm layer of glass before it reaches the objective lens of the alignment microscope. This considerable distance between the alignment mark and the objective lens causes an aberration in the alignment.
  • the image of the alignment indicator on the substrate must pass through the photoresist layer covering the substrate, which also causes some aberration due to dispersion of the light in the photoresist.
  • a particular advantage of the mask according to the invention is that, unlike the photoresist masks, it can often be used, as a result of which process irregularities, which are caused by the individual errors of the individual photoresist masks, which differ from one another, are eliminated.
  • the mask according to the invention allows the manufacturing tolerances to be reduced, since the mask according to the invention can be aligned more precisely with the semiconductor circuit in production than is possible with the conventional photoresist masks.
  • the fluctuations in the mask dimensions can be kept very small during the production of the mask. This is also true if, as is necessary for the manufacture of highly integrated circuits, the mask pattern is very complicated and has many small, closely spaced openings.
  • the mask according to the invention has such good stability that it can also be used for the production of highly integrated, ie covering relatively large-area chips, without the mask stabilizing reinforcements, which would prevent the optimal use of the mask, being necessary in the chip area.
  • the unsupported areas of the mask according to the invention have lateral dimensions which are at least of the order of 1.25 mm and preferably of the order of 12.5 mm. It is sufficient that the mask remains self-supporting even with such large lateral dimensions that the thin silicon layer has a thickness of the order of 3 ⁇ m.
  • the method according to the invention for producing the mask according to the invention decisively influences the accuracy with which the mask can be produced according to specified specifications.
  • the manufacturing method according to the invention is also decisive in order to give the mask the training and its great mechanical stability that is suitable for the manufacture of highly integrated, densely packed circuits.
  • approximately 3 pm thick silicon layers can be produced very precisely and reproducibly.
  • the mask openings are produced, which are then no longer subjected to a process step in which they are changed in an uncontrolled manner, so that pattern accuracy can be achieved within small tolerances.
  • the typical thickness of the mask structure consisting of the reinforcing framework and the thin layer is between 0.127 and 0.381 mm and the silicon substrates used to manufacture the mask also have such thicknesses.
  • the masks according to the invention can be used practically in all process steps in which photoresist masks are used in the known processes, in particular for the production of integrated circuits.
  • the mask according to the invention is very advantageous in ion implantation, in sputter etching and even when ions of a reactive gas are added to the gas atmosphere, in the lift-off process for producing patterns from metals or insulating materials, and also in the case of process sections in which a lift-off process immediately follows the sputter etching.
  • Figures 1 and 1A show part of a silicon mask which has been produced according to the method according to the invention.
  • the mask includes thin silicon regions 10 which have lateral dimensions in the order of magnitude of 1.27 to 12.7 mm and thus essentially the size of a chip on a silicon wafer which is subjected to the manufacturing process; in which a number of masks, such as those shown in Figures 1 and 1A, are used. Between the thin silicon areas 10, the mask has thicker, supportive areas 11, which are preferably in their distance and in il. The dimensions correspond to those of the cut areas between the chips of the silicon wafer, the mask of which is used when it is converted into integrated circuits.
  • the thin silicon layer 10 has a thickness which is preferably on the order of between approximately 3 and approximately 5 ⁇ m, while the thickness of the thicker supporting regions or ribs 11 is on the order of approximately 127 and approximately 381 ⁇ m.
  • the mask having the surface 12, which is substantially planar is placed in contact with the integrated circuit to be manufactured during the fabrication steps in which the mask is used.
  • the thin masking layer 10 forms the bottom of the recesses 13.
  • the openings 14 in the thin silicon layer 10 serve to cover the areas which are affected during the operation in the production of integrated circuits in which the present mask is used define.
  • Such an operation can include ion implantation, the etching of the silicon substrate or of metallic or insulating layers on the substrate and also the formation of metallic patterns or patterns of electrically insulating material on the substrate by means of the lift-off technique .
  • FIGS. 2A to 2E The preferred manufacturing method for the mask according to the invention will now be described with reference to FIGS. 2A to 2E.
  • a number of lithographic masking steps are carried out during the production of the mask, but these are not discussed in detail because of their use in semiconductor technology is well known. Details of such photolithographic masking and manufacturing steps can be found in representative U.S. Patents 3,589,876 and 3,904,454 and in RM Warner et al. "Integrated Circuits, Design Principles and Fabrication", published by McGraw Hill Book Company in 1965 , can be read.
  • an approximately 5000 ⁇ thick silicon dioxide layer 21 is grown on a surface of a ⁇ 100> crystallographic orientation of a P-type silicon die 20 having a resistivity of 10 ⁇ cm by thermal oxidation .
  • This layer serves as a diffusion-preventing mask.
  • the other surface of the wafer is subjected to boron capsule diffusion for about 64 hours and carried out at 1100 ° C. to produce a silicon layer 22 of the P + type, which has a surface concentration C O of 3 ⁇ 10 20 atoms / cm 3 and at that Boundary layer 23 has a doping concentration of 7 x 10 19 atoms / cm 3 .
  • a layer 24 of silicon dioxide which is about 5000 ⁇ thick, is formed over the P + type silicon layer 22.
  • the P + layer 22 is approximately 5 ⁇ m thick. If, as in the present example, the P + layer 22, which will later become the thin region of the silicon mask, is 5 ⁇ m or thinner, the silicon dioxide layer 24 should not be produced by thermal oxidation, but scondering by another method. If one were to thermally oxidize the presence of such a thin layer, the thin silicon area would be the Mask, which is generated from the layer 22, especially if it has large lateral dimensions, ie! those in the range between 1.27 and 12.7 mm, between the ribs, are deformed. As a result, silicon layer 24 is preferably grown using a non-thermal growth technique, such as e.g. B. by means of conventional sputtering or: conventional chemical vapor deposition.
  • a non-thermal growth technique such as e.g. B. by means of conventional sputtering or: conventional chemical vapor
  • the silicon nitride layer 25 'and the silicon dioxide layer 26' are deposited on the lower silicon dioxide layer 21.
  • a composite mask consisting of layers 21 ', 25' and 26 ' is then produced on the underside of substrate 20 using known photolithographic etching techniques.
  • the openings 27 in this mask serve to define the pattern of the depressions 28 which are to be produced in the substrate in the following process step illustrated in FIG. 2C.
  • the depressions 28 are produced in the substrate 20 by means of an anisotropic etching technique, in which the less heavily doped P substrate 20 is selectively etched away and the etching on the lower surface 23 of the P + layer 22 practically stops.
  • the anisotropic etch serves to minimize undesirable lateral etch, which would otherwise be significant if etched through a silicon substrate that is between about 127 and about 381 microns thick.
  • a mixture is formed during the anisotropic etching to produce the depressions 28 from ethylenediamine, pyrocatechol and water.
  • a mixture containing 25 ml ethylene diamine, 4 g of pyrocatechol and 4 mL of water can be used contains at 118 0 C, being allowed to bubble through the solution nitrogen to prevent oxidation.
  • Such a mixture selectively etches silicon poorly doped with boron, of which the substrate 20 is made, for example, while silicon heavily doped with boron, for example the layer 22, in which etching remains essentially unchanged. Since this mixture etches so that the remaining masked silicon ribs 20 '- provided the silicon has a ⁇ 100> crystallographic orientation - an angle 29 of 54.7 ° with the horizontal! unwanted lateral etching will be quite limited. Details of the etching with the ethylenediamine-pyrocatechol-water mixture can be found in an article in IEEE Transactions on Electronic Development, Volume ED23, No. 6, June 1976, pages 579-583.
  • FIG. 2D shows, a pattern of openings 30 is produced through the silicon nitride layer 24 and the silicon dioxide layer 25 using photolithographic fabrication techniques customary in semiconductor technology.
  • the pattern of openings 30 corresponds to the pattern of openings which are to be created in the silicon mask.
  • FIG. 2E the corresponding pattern of openings 31 passes through the thin silicon layer 22! etched.
  • silicon etching processes customary in semiconductor technology such as eg. B. etching with a mixture of dilute hydrofluoric acid and nitric acid acid can be applied.
  • the silicon layer 22 which has to be etched through is relatively thick, ie on the order of 3 to 5 ⁇ m, it is desirable to minimize the lateral etching. Therefore, it is preferred to etch openings 31 through silicon layer 22 using sputter etching, using conventional sputter etching devices and methods, such as those described in U.S. Patent 3,598,710, and in particular sputter etching with the addition of reactive gases.
  • U.S. Patent 3,471,396 contains a list of inert or reactive gases or combinations of such gases that can be used with cathode sputtering sets.
  • a preferred reactive sputter etch atmosphere is e.g. B. a Cl 2 plasma.
  • the openings 31, as shown in FIG. 2E when carrying out the method according to the invention, it is preferred to etch the openings 31, as shown in FIG. 2E, from the surface 32 of the layer 22 and not from the lower surface 23 of the layer 22.
  • the etching, as shown in FIG. 2E will create an opening 31 whose side walls face towards; taper the lower edge of the opening at an angle of approximately 5 °.
  • Such a taper is particularly desirable because when the mask is used in a lifting-off step in the production of metallic or other patterns on the substrate, there is an overhang or a negative slope in the mask openings.
  • the patterning of openings 31 as shown in Fig. 2E is complete, it is desirable that the silicon dioxide layers 21 and 24 and the silicon nitride layers 25 and 25 'be removed, thereby removing the self-supporting silicon mask is left.
  • the pattern of openings 31 in this mask corresponds to a special lateral pattern which defines the regions which are selectively changed during a special method step in the course of the production of the integrated circuit.
  • These process steps include the introduction of impurities into the substrate, the etching of metallic or insulating layers or patterns into the substrate, the selective oxidation of the substrate or the deposition of metallic or insulating patterns on the substrate by means of the lift-off -Technology. Representative examples of some of these methods in which the silicon mask of the present invention is used in the manufacture of integrated circuits will now be described.
  • FIG. 3 shows the use of the silicon mask 33 as a mask when implanting positive boron ions by means of the ion beam 34, regions 35 of the P type being generated in the substrate 36 of the N type.
  • the mask 33 lies flush on the surface 37 of the substrate 36.
  • a distance 38 the thickness of which lies between approximately 4000 and approximately 10000 ⁇ , becomes the substrate from the mask 33 separate.
  • the alignment of alignment marks on the mask e.g. B. the L-shaped alignment 1, with the substrate using optical means, since the alignment mark is at most a few ⁇ m away from a corresponding alignment indicator (not shown) on the substrate.
  • this arrangement alleviates or eliminates all mask alignment problems which are typical for the alignment of photoresist masks in photolithographic process steps in the production of integrated circuits (see the statements on the prior art in the introduction to the description).
  • alignment tolerances with respect to the substrate in the order of magnitude of +0.5 ⁇ m are possible with the silicon masks according to the invention, while the alignment tolerances are +2 ⁇ m with the known alignment of photoresist masks.
  • resistances generated by ion implantation such as e.g. B. resistors 35 in Figure 3, in their lateral dimensions less than when using the known masks, and it is possible with the inventive masks to produce resistors whose parameters within very.
  • FIG. 4 shows the application of the silicon mask 41 as a mask in a sputter etching operation in a high frequency sputtering system in which the ions 42 including reactive ions are directed onto an insulating layer 43 on an integrated circuit substrate 44 by a plurality of openings 45 to be etched through this insulating layer.
  • the high frequency sputtering system which operates using reactive ions, can be the same known system that is described above in conjunction ; hang described with the production in front of Sillciummasken has been.
  • the silicon mask When the silicon mask is used as a mask in a high frequency sputtering system, particularly one which uses reactive ions, it has been recognized as desirable that the silicon mask be provided with a thin layer 46, which is of the order of 2000 ⁇ thick, from a protective Metal such as B. made of aluminum. This coating can be applied in a known manner after the protective layers of insulating material, which have been used in connection with the mask opening method step explained with reference to FIG. 2A, have been removed.
  • the self-supporting silicon mask according to the invention is a valuable aid in such a production of integrated circuits, which includes process steps, in which patterns, either made of electrically insulating material or of metal, are deposited on a substrate through the openings in a mask and then the mask is lifted off to remove excess Remove material.
  • Such a ver! Driving step is shown in FIG. 5.
  • Thin areas 51 and thick areas or supporting mask ribs 52 can be seen in the detail from the silicon mask 50.
  • the mask layer 51 is in contact with the substrate 53, on which a metallization pattern is to be produced, and a metal deposition over the entire surface, such as the aluminum layer 54, is applied over the entire masked substrate.
  • the side walls 55 of the 56 have openings bhang in the mask a slight negative A, causing a mask overhang or a mask lip 57 at the edge of the mask openings 56, all the conditions, which as in the liftoff technique necessary to prevent the metal pattern 58 from being deposited in the openings such that it continuously merges into the metal 54 deposited on the mask surface. Thanks to this discontinuity, the mask 51 can easily be lifted off, taking the separated, continuous aluminum layer 54 with it and leaving behind the aluminum pattern 58, which corresponds to the pattern of the openings 56. After completion of the process step, the metal layer 54 can be selectively removed from the mask 51 and the mask can be reused for the same operation on another integrated circuit die.
  • FIGS. 6 and 6A show part of a silicon mask to illustrate the use of the mask for a combination of process steps, ie for the sputter etching of a substrate using reactive ions and the subsequent deposition of a metal pattern in the etched areas of the substrate .
  • FIG. 6 shows a substrate 60 on which a metal layer 61 and an insulating layer 62 are applied.
  • the silicon mask 63 is placed in contact with the insulating layer 62. ii To simplify the illustration, only the thin part of the mask and an opening 64 made in the mask 63 can be seen.
  • a cathode sputter etching step in which, as described above with reference to FIG.
  • the silicon mask 63 as described in connection with FIG. 4, is preferably coated with a thin aluminum layer 66 before the mask is used in the sputtering etching step. The result is shown in FIG. 6.
  • Metal is then deposited in the same manner as discussed in connection with FIG. 5 to create a pattern of metallic interconnections 68 in the openings 65 that extend through the insulating layer 62.
  • the connections 68 have the task of establishing connections to the underlying metal layer 61.
  • the rest of the metal deposition 67 applied over the entire surface is removed by lifting off the silicon mask 63. '
EP78100294A 1977-07-05 1978-07-03 Procédé de fabrication d'un masque de silicium et son utilisation Expired EP0001038B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US81294177A 1977-07-05 1977-07-05
US812941 1985-12-23

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Publication Number Publication Date
EP0001038A1 true EP0001038A1 (fr) 1979-03-21
EP0001038B1 EP0001038B1 (fr) 1981-09-02

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EP78100294A Expired EP0001038B1 (fr) 1977-07-05 1978-07-03 Procédé de fabrication d'un masque de silicium et son utilisation

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EP (1) EP0001038B1 (fr)
JP (1) JPS5414680A (fr)
DE (1) DE2860999D1 (fr)
IT (1) IT1109829B (fr)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0019779A2 (fr) * 1979-06-01 1980-12-10 International Business Machines Corporation Masque à ouvertures pour la réalisation de surfaces texturées et procédé de fabrication de celui-ci
EP0061787A1 (fr) * 1981-03-02 1982-10-06 BBC Aktiengesellschaft Brown, Boveri & Cie. Procédé pour le dopage de corps semiconducteurs pour la fabrication de dispositifs semiconducteurs
EP0078336A1 (fr) * 1981-10-30 1983-05-11 Ibm Deutschland Gmbh Masque projetant l'ombre pour l'implantation d'ions et pour la lithographie par rayons d'ions
EP0048291B1 (fr) * 1980-09-19 1985-07-03 Ibm Deutschland Gmbh Structure comprenant un corps de silicium présentant une ouverture le traversant de part en part et procédé de fabrication
EP0163074A2 (fr) * 1984-05-21 1985-12-04 International Business Machines Corporation Procédé pour la formation des ouvertures de contact ayant des parois verticales obliques dans une couche en polymère
EP0237844A1 (fr) * 1986-03-18 1987-09-23 BBC Brown Boveri AG Procédé pour la fabrication d'une couche de passivation dans la technologie des semi-conducteurs, et application de cette couche
EP0368089A2 (fr) * 1988-11-07 1990-05-16 Fujitsu Limited Procédé de fabrication d'un masque pour la texturation lithographique
EP0399998A2 (fr) * 1989-05-26 1990-11-28 IMS Ionen Mikrofabrikations Systeme Gesellschaft m.b.H. Procédé de fabrication de masques d'ombre en silice de haute définition
EP0542519A1 (fr) * 1991-11-14 1993-05-19 International Business Machines Corporation Masque à membrane avec entaille inférieure pour gravure par exposition avec des photons de haute énergie
US5234781A (en) * 1988-11-07 1993-08-10 Fujitsu Limited Mask for lithographic patterning and a method of manufacturing the same
WO2001077009A1 (fr) * 2000-04-07 2001-10-18 Robert Bosch Gmbh Composant micromecanique et son procede de production

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3476281D1 (en) * 1984-07-16 1989-02-23 Ibm Deutschland Process to repair transmission masks
JP2506019B2 (ja) * 1991-04-25 1996-06-12 富士通株式会社 透過マスクの製造方法
US6335534B1 (en) 1998-04-17 2002-01-01 Kabushiki Kaisha Toshiba Ion implantation apparatus, ion generating apparatus and semiconductor manufacturing method with ion implantation processes

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GB1235077A (en) * 1969-05-07 1971-06-09 Standard Telephones Cables Ltd Improvements in or relating to pressure transducers
FR2233654A1 (fr) * 1973-06-18 1975-01-10 Texas Instruments Inc
FR2252907A1 (fr) * 1973-11-29 1975-06-27 Siemens Ag
US4021276A (en) * 1975-12-29 1977-05-03 Western Electric Company, Inc. Method of making rib-structure shadow mask for ion implantation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1235077A (en) * 1969-05-07 1971-06-09 Standard Telephones Cables Ltd Improvements in or relating to pressure transducers
FR2233654A1 (fr) * 1973-06-18 1975-01-10 Texas Instruments Inc
FR2252907A1 (fr) * 1973-11-29 1975-06-27 Siemens Ag
US4021276A (en) * 1975-12-29 1977-05-03 Western Electric Company, Inc. Method of making rib-structure shadow mask for ion implantation

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0019779A2 (fr) * 1979-06-01 1980-12-10 International Business Machines Corporation Masque à ouvertures pour la réalisation de surfaces texturées et procédé de fabrication de celui-ci
EP0019779A3 (en) * 1979-06-01 1981-10-28 International Business Machines Corporation Apertured mask for creating patterned surfaces and process for its manufacture
EP0048291B1 (fr) * 1980-09-19 1985-07-03 Ibm Deutschland Gmbh Structure comprenant un corps de silicium présentant une ouverture le traversant de part en part et procédé de fabrication
EP0061787A1 (fr) * 1981-03-02 1982-10-06 BBC Aktiengesellschaft Brown, Boveri & Cie. Procédé pour le dopage de corps semiconducteurs pour la fabrication de dispositifs semiconducteurs
EP0078336A1 (fr) * 1981-10-30 1983-05-11 Ibm Deutschland Gmbh Masque projetant l'ombre pour l'implantation d'ions et pour la lithographie par rayons d'ions
EP0163074A3 (en) * 1984-05-21 1988-11-02 International Business Machines Corporation A process for forming via holes sloping side walls in a polymer film
EP0163074A2 (fr) * 1984-05-21 1985-12-04 International Business Machines Corporation Procédé pour la formation des ouvertures de contact ayant des parois verticales obliques dans une couche en polymère
EP0237844A1 (fr) * 1986-03-18 1987-09-23 BBC Brown Boveri AG Procédé pour la fabrication d'une couche de passivation dans la technologie des semi-conducteurs, et application de cette couche
US4764249A (en) * 1986-03-18 1988-08-16 Bbc Brown, Boveri Ltd. Method for producing a coating layer for semiconductor technology and also use of the coating layer
EP0368089A2 (fr) * 1988-11-07 1990-05-16 Fujitsu Limited Procédé de fabrication d'un masque pour la texturation lithographique
EP0368089A3 (fr) * 1988-11-07 1991-05-22 Fujitsu Limited Procédé de fabrication d'un masque pour la texturation lithographique
US5234781A (en) * 1988-11-07 1993-08-10 Fujitsu Limited Mask for lithographic patterning and a method of manufacturing the same
EP0399998A2 (fr) * 1989-05-26 1990-11-28 IMS Ionen Mikrofabrikations Systeme Gesellschaft m.b.H. Procédé de fabrication de masques d'ombre en silice de haute définition
EP0399998A3 (fr) * 1989-05-26 1991-07-17 IMS Ionen Mikrofabrikations Systeme Gesellschaft m.b.H. Procédé de fabrication de masques d'ombre en silice de haute définition
EP0542519A1 (fr) * 1991-11-14 1993-05-19 International Business Machines Corporation Masque à membrane avec entaille inférieure pour gravure par exposition avec des photons de haute énergie
WO2001077009A1 (fr) * 2000-04-07 2001-10-18 Robert Bosch Gmbh Composant micromecanique et son procede de production
US7041225B2 (en) 2000-04-07 2006-05-09 Robert Bosch Gmbh Micromechanical component and method for producing the same

Also Published As

Publication number Publication date
JPS6158974B2 (fr) 1986-12-13
EP0001038B1 (fr) 1981-09-02
IT7824892A0 (it) 1978-06-23
IT1109829B (it) 1985-12-23
DE2860999D1 (en) 1981-11-26
JPS5414680A (en) 1979-02-03

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