EP0000384B1 - Disposition de montage de circuits intégrés rapides comportant des capacités de découplage pour les bornes d'alimentation et procédé de réalisation. - Google Patents

Disposition de montage de circuits intégrés rapides comportant des capacités de découplage pour les bornes d'alimentation et procédé de réalisation. Download PDF

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Publication number
EP0000384B1
EP0000384B1 EP78100332A EP78100332A EP0000384B1 EP 0000384 B1 EP0000384 B1 EP 0000384B1 EP 78100332 A EP78100332 A EP 78100332A EP 78100332 A EP78100332 A EP 78100332A EP 0000384 B1 EP0000384 B1 EP 0000384B1
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EP
European Patent Office
Prior art keywords
holes
substrate
mask
layer
metal
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP78100332A
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German (de)
English (en)
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EP0000384A1 (fr
Inventor
Ven Young Doo
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International Business Machines Corp
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International Business Machines Corp
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Publication of EP0000384A1 publication Critical patent/EP0000384A1/fr
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base

Definitions

  • the invention relates to an arrangement for packing fast-switching monolithically integrated semiconductor circuits, which has decoupling capacitors for the connection points of the power supply of the semiconductor die, and a method for producing the arrangement.
  • Monolithically integrated semiconductor circuits have been developed to operate at increasing operating speeds.
  • logic circuits for the use of computers have been developed.
  • the increased frequency of the signals of the monolithically integrated semiconductor circuits has also required comparable improvements in the structure of the arrangement for packaging the monolithically integrated semiconductor circuits.
  • crosstalk resulting from coupling between circuits adjacent to the signal lines becomes significant when operating very quickly because of the rates of change of the electric and magnetic fields during the transients. This problem is pronounced when using high-frequency signals.
  • Another major problem is limiting voltage fluctuations in the driver stage power supply lines, often referred to as driver interference voltages. Since the current flowing in the lines of the driver circuit is relatively high, the driver interference voltages are primarily influenced by the inductance of the lines.
  • Decoupling capacitors have been proposed to reduce driver interference voltages.
  • conventional decoupling capacitors are designed as discrete components and are necessarily at a certain distance from the driver stage and normally require additional transmission lines which increase the inductance, as a result of which the effect of the decoupling capacitors is reduced.
  • the structure of an arrangement for packaging the monolithically integrated semiconductor circuits is often the limiting factor which prevents the better operating properties of the semiconductor components from being fully exploited.
  • the invention seeks to remedy this.
  • the invention as characterized in the claims, solves the problem of creating an arrangement for packing fast-switching monolithically integrated semiconductor circuits which has decoupling capacitors for the connection points of the power supply and in which, due to their structure, the power supply lines which occur when the semiconductor components are switched Voltage fluctuations, which represent interference voltages, are reduced.
  • the invention solves the problem of specifying a method for producing such an arrangement.
  • the arrangement has a substrate 10 made of ceramic material, which preferably has an expansion coefficient which is very close to that of silicon.
  • a large number of solder pads are arranged on the surface in a configuration that corresponds to the configuration of connection pads on the semiconductor die to be soldered.
  • the outer rows 12 and 14 of the solder pads are used to connect to the signal input / output connection points on the die.
  • Conductor tracks 16 and 18 applied to the substrate 10 make electrical contact with the surfaces 12 and 14 for the input / output signals and via pins which extend through the substrate 10 to a connection point (not shown) on the underside.
  • connection areas 20 for connection to the connection points for the power supply and the ground potential of the semiconductor die to be fastened on the substrate. In general, these connection areas are more widely distributed than that shown in FIG. 1.
  • Each of the pads 20 is connected to an underlying via that is in a hole in the substrate 10 and is connected to a connection point on the opposite lower side of the substrate.
  • a decoupling capacitor is arranged above the connecting pin, which lies below the connection area 20, which is explained in more detail in the description below.
  • the inventive arrangement for packaging monolithically integrated semiconductor circuits seeks to alleviate a significant problem associated with such arrangements in general, thereby making the arrangement more compatible with today's very sophisticated semiconductor circuits, particularly those designed to perform logic operations quickly working computers were developed.
  • the arrangement according to the invention for packaging monolithically integrated semiconductor circuits can be produced using currently known production methods.
  • the mentioned problem with arrangements for packaging monolithically integrated semiconductor circuits is to reduce the driver interference voltage. This is the voltage change in the driver circuit caused by the inductance of the power supply lines and the other lines. In order to increase the operating speed of a computer system, it is very desirable that many driver circuits switch at the same time.
  • the limiting factor for the number of driver stages that are operated simultaneously is the driver interference voltage.
  • decoupling capacitors are provided in the immediate vicinity of the connections for the power supply. The relationship applies to the driver interference voltage V: in which n is the number of driver stages switching simultaneously during the time interval dt, L is the inductance and is the change in current over time during switching.
  • the value of is determined by the operating parameters of the monolithically integrated semiconductor circuit and cannot be changed significantly.
  • the inductance L is a variable which, when reduced, also reduces the driver interference voltage according to the relationship given above.
  • the following size equation is of interest where V is the speed of light, L is inductance and C is capacitance. As the relationship shows, the product C x L is a constant. Therefore, if C is made larger, L becomes smaller, which is desirable. Therefore, the driver interference voltage can be made smaller by increasing the capacity of the power supply lines.
  • This capacitance can be increased by using decoupling capacitors which are assigned to the conductor tracks of the arrangement for packaging monolithically integrated semiconductor circuits.
  • the operating speed of highly integrated monolithic circuits is largely limited by the transmission delay caused by the arrangement for packing the circuits. This is because the switching delay of the active switching elements becomes relatively insignificant with regard to the propagation delay in the arrangement for packaging the monolithically highly integrated semiconductor circuits.
  • the propagation delay is due in large part to the large dielectric constant of the insulating material between the layers of a conventional arrangement for packaging the monolithically integrated semiconductor circuits.
  • the dielectric constant of insulating material is greater than one.
  • the dielectric constant of ceramic material is approximately nine. The greater the dielectric constant, the lower the speed of signal propagation.
  • a third problem associated with conventional arrangements for packaging monolithic semiconductor integrated circuits is crosstalk between the signal lines.
  • the crosstalk between generally parallel signal lines is caused by the inductive and capacitive coupling of the lines.
  • Due to a special embodiment of the invention, a metal plate connected to the reference potential is arranged in the immediate vicinity of the signal lines and above them, around which to reduce capacitive coupling of adjacent lines.
  • a substrate 10 is formed from an insulating material, preferably a material that has a coefficient of thermal expansion that substantially corresponds to the coefficient of thermal expansion of silicon. Ceramic and glass ceramic are the usual materials suitable for this purpose.
  • the thickness of the substrate 10 is preferably on the order of 0.5 to 1.5 mm.
  • Holes 22 are provided, which are preferably conical, as shown. In general, the holes 22 have a diameter of 75 to 150 ⁇ m at the narrower end and one of 250 to 500 ⁇ m at the larger end.
  • the perforated substrate can be made in any suitable manner.
  • a ceramic slurry containing a finely divided ceramic material and a binder can be brought to the desired thickness with a doctor blade.
  • the holes are punched or shaped and the sheet of green ceramic material obtained is sintered.
  • the substrate can also be pressed and sintered if desired.
  • the holes 22 are formed in the substrate 10 such that their configuration lies under the connection pads 20 of the semiconductor die, which supply the electrical energy to it, as is shown in FIG.
  • the substrate 10 can be manufactured in any suitable size and can accommodate any suitable number of semiconductor wafers. In general, however, it is difficult to place more than three dies on a substrate if only one level of metallization is used.
  • the configuration of the holes 22 must be designed before punching and must take into account the substrate shrinkage during sintering. Therefore, the output pattern in the green substrate must be larger than the pattern on the die by the amount the substrate shrinks during sintering. As shown in FIG. 3, the substrate is masked with a photoresist layer 24 on the surface on which the holes have the larger diameter.
  • the photoresist is exposed and developed to leave an opening 25 above the holes in which the decoupling capacitors are formed. In general, these openings are below the connections for the power supply and the ground potential of the semiconductor die after it has been applied.
  • Layer 24 therefore covers openings 22 which serve as simple through holes for the signal lines.
  • a thin layer 26 of a base metal and a layer 27 within the holes are then deposited on the substrate not covered by the mask 24. Either aluminum, titanium, tantalum or copper, which is deposited to a thickness of the order of a few micrometers, is preferably used as the base metal.
  • the deposition of metal can be achieved by vapor deposition, deposition by sputtering or by electroless metal deposition.
  • the film that deposits on the surface of photoresist 24 is removed along with that layer.
  • the thickness of layers 26 and 27 can be increased by electroplating, if desired. This method is known and is generally carried out in such a way that the conductive layers 26 and 27 form the cathode in a galvanic bath.
  • the reinforced layers 26 and 27 are anodized to form a thin dielectric layer 28, which preferably has a thickness in the range from 0.25 to a few nanometers, as indicated in FIG. 4.
  • This dielectric layer 28 is formed by anodizing the metal layer in a suitable solution. The oxide thus formed depends on the nature of the starting layer.
  • the layers 26 and 27 are made of aluminum, Al 2 0 3 is formed, if the initial layers are made of titanium, Ti0 2 is formed and if they are made of tantalum, Ta205 is formed.
  • the anodized substrate can then be heated in an oxidizing atmosphere to oxidize the metal that was not well covered by the anodizing process due to the presence of pinholes in the anodized oxide.
  • the base metal is copper, a thin oxide layer such as Si0 2 , A1 2 0 3 etc. is deposited on the copper by sputtering or in some other way.
  • the mask 30 can be formed by pre-punching a plastic film which has openings 31 with a larger diameter than the exposed openings of the holes 22.
  • the masking film 30 is attached to the surface of the substrate 10 and the openings are filled with an electrically conductive paste which preferably consists of copper with 3 to 6% zinc and / or tin in combination with a suitable carrier.
  • the paste can be pressed into the openings 22 and the openings 31 of the mask.
  • holes 22 may be filled separately before mask 30 is applied.
  • holes 22 and 31 can be chemically metallized.
  • At least one of the holes 22 can be masked prior to anodizing.
  • the hole can be masked by forming a photoresist layer over the opening or by covering it with paraffin.
  • the inner surface of the masked hole is not anodized during anodizing.
  • the conductive paste is subsequently introduced, as shown in FIG. 5, the conductive cone 41 thus formed is in direct contact with the conductive layer 27.
  • the conductive paste is Cones formed in the holes are separated from the conductive layer 27 by the anodized layer 28, which is made of a dielectric material.
  • the structure obtained after the removal of the masking layer 30 is, as indicated in FIG.
  • the cone 41 which is in direct contact with the layer 27, forms the ground connection for the layer 26, which connects all the layers 27 of the decoupling capacitors to one another.
  • a metallization pattern is formed from the strips 16 and 18 on the opposite side of the substrate 10, which, as shown in FIG. 1, connects the signal connections of the semiconductor die to be applied to the substrate with the through connections 38, which are not underneath the semiconductor chip.
  • This metallization pattern can be formed in any suitable manner, e.g. B.
  • a perforated masking layer on the surface of the substrate, forming the openings for the metallization strips by cutting with an electron beam and then filling the openings with a conductive paste.
  • a metallic cover layer can be applied and a suitable pattern can be produced by subtractive etching, which is known.
  • Another alternative method is to cut a thin metal layer (0.1 nm), form a window of photoresist corresponding to the pattern of the signal lines, then electrodeposition in the window, remove the photoresist and finally dip-etch to remove the initial thin metal coating along the lines to remove and thereby separate them electrically.
  • the structure obtained has a series of signal connections 39 and a series of power supply connections 43, to which a decoupling capacitor is assigned, which is arranged in the immediate vicinity of the power supply connections of the semiconductor die.
  • FIG. 6A Another structure is shown in FIG. 6A which has been manufactured in a different way.
  • the substrate 10A is provided with cylindrical holes 22A arranged in the same basic configuration that was explained in connection with FIG. 2.
  • a masking photoresist layer similar to layer 24 shown in FIG. 1, is deposited, exposed and developed to expose the area surrounding the via holes for supplying the supply voltages and ground potential.
  • a metal layer 27A is then deposited in the exposed area by any suitable method. This layer 27A need not extend to the through hole walls 22A, although it may be provided if desired.
  • coaxial cable pieces 40A are inserted into the through holes for supplying the power supply voltage, the ends 43A of which extend beyond the surface and thereby form connections for fastening on a supporting card or other structure.
  • the upper ends of the coaxial cable pieces 40A are stripped of the insulating layer 28A.
  • the outer metal layer 27A of the coaxial cable makes electrical contact with the layer 26A.
  • the insulating layer 28A electrically insulates the coaxial cable piece 40A from its outer metal layer 27A and thereby forms a decoupling capacitor.
  • a piece of wire 41A is inserted into the hole 22A and forms the connection 45A of the decoupling capacitors, which is connected to the ground potential. Similar pieces 38A are inserted in the signal through holes, thereby forming the signal terminals 39A.
  • the side for receiving the semiconductor die is kept flat, if necessary by grinding.
  • a dielectric cover layer 42A is formed over the side intended to receive the semiconductor die and holes are etched in the cover layer at the locations where the wire pieces 38A, 41A and 40A are located. Particular care must be taken to ensure that the hole over the inner conductor 40A of the coaxial cable piece does not extend to the dielectric layer 28A.
  • a multilayer metallic cover layer such as Cr-Cu-Cr is applied by any suitable method and the metallization patterns 16A and 18A and contact areas 20A are produced by conventional subtractive etching.
  • This substrate can be processed further in the same manner as that described for the first exemplary embodiment shown in FIG. 6.
  • recesses can be formed between the conductor tracks 16 and 18, which reduce the capacitive coupling by increasing the amount of air dielectric.
  • the recesses 30 can be cut with an electron beam or with a wet saw and are preferably 25 to 35 micrometers deep. If glass ceramic is used as the substrate 10, the recesses can be formed by etching, the metal surface serving as an etching mask.
  • FIG. 7 A silicon die 34 with monolithically integrated circuits is soldered onto the solder pads 20 and the connection pads 12 and 14 of the metallization for the signals.
  • the connectors 43, which form part of the driver circuit, and the connectors 39, which form part of the metallization for the signals, are connected to connectors on a suitable circuit card or other carrier.
  • a ground plane 50 is provided which is located closely above the strip-shaped metallization for the signal lines 16 and 18.
  • the ground plane 50 has an opening 51 for receiving the semiconductor die 34 and is provided with spacers 52 made of insulating material which touch the surface of the substrate or the strip-like metallization and thereby maintain a certain distance.
  • the spacers 52 made of insulating material can alternatively also be provided on the substrate. 8 shows the substrate 10 with the ground plane 50 arranged above it.
  • the ground plane 50 is connected to the ground potential by means of suitable electrical connections.
  • a water cooling plate 60 is attached to the module with a preferably serpentine-like water path.
  • the water cooling plate 60 may be connected to the ground plane 50 or, alternatively, the ground plane may be an integral part of the water cooling plate.
  • the central region of the water cooling plate above the semiconductor plate 34 is fastened to the latter with a highly heat-conducting, electrically insulating paste-like material 62 in order to improve the heat dissipation from the semiconductor plate 34 to the water cooling plate 60.
  • the thermally conductive paste-like material conducts the heat from the semiconductor die to the water cooling plate and serves as a buffer for the thermal expansion and contraction of the semiconductor die, thereby avoiding thermal stresses in the semiconductor die 34.
  • Inlet 64 and outlet 66 may be connected to any suitable source of water to circulate the water.
  • the space surrounding the die can be easily and effectively sealed by a seal 52 between the flange 50 and the substrate 10 and a second seal 53 between the water cooling plate 60 and the ground plane 50.
  • the seals 52 and 53 can be formed from any suitable material, e.g. B. from an organic resin material or a low-melting solder.
  • ground plane 70 is divided into a series of sections. As can be seen from FIG. 11, insulating layers 72 and 74 are applied to the metal plate 70 forming the substrate, which has a hole 71 which corresponds to the semiconductor die, on the upper and lower main surfaces. Metal layers 76 and 78 are deposited over the insulating layers 72 and 74 on the sections. A water connection 80 is provided in the space between the quadrants of the metal layer 78 and extends through the dielectric layer 74 to the metal substrate 70. Terminal areas 82 are formed on the metal layer 78 in direct electrical contact with it. When the ground plane 70 is placed on the substrate 10, as shown in the plan view according to FIG. 1, the connection areas 80 with the connection areas 81 on the substrate and the connection areas 82 connected with the metal layer 78 with the connection areas 83 on the substrate 10 connected.

Claims (10)

1. Dispositif pour monter des circuits semiconducteurs monolithiquement intégrés à vitesse élevée comportant des condensateurs de découplage pour les lignes d'alimentation de la microplaquette semiconductrice, caractérisé en ce que les condensateurs de découplage sont placés dans les trous d'un substrat de matériau électriquement isolant recevant la microplaquette semi-conductrice, lesdits trous étant destinés à amener la tension d'alimentation à la microplaquette semi-conductrice, et en ce que la tension d'alimentation est appliqué à la microplaquette semiconductrice à travers la première électrode d'un condensateur de découplage.
2. Dispositif selon la revendication 1, caractérisé en ce que les secondes électrodes de tous les condensateurs de découplage du substrat sont connectées entre elles et avec le potentiel de référence.
3. Procédé pour fabriquer un dispositif selon l'une des revendications 1 et 2, caractérisé en ce que l'on:
a) dépose, sur le substrat d'un matériau électriquement isolant comportant des trous, un masque (24; figure 3) qui ne recouvre pas ceux des trous et leur environnement immédiat qui sont destinés à amener la tension d'alimentation à la microplaquette semi-conductrice,
b) dépose dans lesdits trous et leur environnement immédiat une couche mince (26, 27; figure 3) d'un des métaux: aluminium, tantale ou titane,
c) renforce, par galvanisation, la couche de métal mince déposée,
d) enlève le masque et on oxyde anodiquement une partie de la couche métallique pour former une couche diélectrique superposée sur cette couche (28; figure 4),
e) remplit les trous du substrat avec du métal, et
f) forme sur le substrat des conducteurs qui établissent un contact avec le métal situé dans les trous.
4. Procédé selon la revendication 3, caractérisé en ce que la couche métallique mince déposée dans l'étape b) est déposée chimiquement.
5. Procédé selon la revendication 3, caractérisé en ce que la couche métallique mince déposée dans l'étape b) est déposée sous vide.
6. Procédé selon la revendication 3, caractérisé en ce que les trous réalisés dans le substrat sont remplis de métal en étalant dans les trous une pâte de particules métalliques finement dispersées et d'un liant organique à l'aide de la technique d'impression par écran.
7. Procédé selon la revendication 6, caractérisé en ce que l'on fixe un masque préperforé sur le substrat de telle sorte que les trous du masque dont le diamètre est supérieur à celui des trous du substrat sont disposés concentriquement par rapport à ces derniers, et en ce que l'on étale la pâte dans les trous du masque et du substrat, on enlève le masque et on fritte la pâte.
8. Procédé selon la revendication 3, caractérisé en ce que les conducteurs du substrat sont formés par:
a) dépôt d'une couche métallique de recouvrement sur le substrat,
b) dépôt, exposition et développement d'une couche de résine photosensible définissant la configuration de conducteurs désirée, et
c) décapage du métal en excès.
9. Procédé selon la revendication 3, caractérisé en ce que la configuration de conducteurs est formée par:
a) dépôt, sur le substrat, d'un masque métallique comportant des ouvertures qui correspondent à la configuration de conducteur désirée, et
b) remplissage des ouvertures du masque avec une pâte électriquement conductrice à l'aide de la technique d'impression par écran.
10. Procédé pour fabriquer un dispositif selon l'une quelconque des revendications 1 et 2, caractérisé en ce que l'on forme les condensateurs de découplage en insérant des parties de câble coaxial dans les trous du substrat d'un matériau électriquement isolant.
EP78100332A 1977-07-15 1978-07-07 Disposition de montage de circuits intégrés rapides comportant des capacités de découplage pour les bornes d'alimentation et procédé de réalisation. Expired EP0000384B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US815951 1977-07-15
US05/815,951 US4153988A (en) 1977-07-15 1977-07-15 High performance integrated circuit semiconductor package and method of making

Publications (2)

Publication Number Publication Date
EP0000384A1 EP0000384A1 (fr) 1979-01-24
EP0000384B1 true EP0000384B1 (fr) 1981-12-30

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EP78100332A Expired EP0000384B1 (fr) 1977-07-15 1978-07-07 Disposition de montage de circuits intégrés rapides comportant des capacités de découplage pour les bornes d'alimentation et procédé de réalisation.

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Country Link
US (1) US4153988A (fr)
EP (1) EP0000384B1 (fr)
JP (1) JPS5421170A (fr)
CA (1) CA1090002A (fr)
DE (1) DE2861463D1 (fr)
IT (1) IT1109828B (fr)

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Also Published As

Publication number Publication date
EP0000384A1 (fr) 1979-01-24
JPS5710577B2 (fr) 1982-02-26
CA1090002A (fr) 1980-11-18
DE2861463D1 (en) 1982-02-18
US4153988A (en) 1979-05-15
JPS5421170A (en) 1979-02-17
IT1109828B (it) 1985-12-23
IT7824893A0 (it) 1978-06-23

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