JPH0776917B2
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1984-12-29 |
1995-08-16 |
ソニー株式会社 |
マイクロコンピユ−タ
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1986-01-29 |
1991-07-02 |
Douglas W. Clark |
Dispositif et methode d'execution d'instructions de branchement
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1986-03-13 |
1991-02-05 |
International Business Machines Corporation |
Pipeline processing apparatus for executing instructions in three streams, including branch stream pre-execution processor for pre-executing conditional branch instructions
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JPS6393041A
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1986-10-07 |
1988-04-23 |
Mitsubishi Electric Corp |
計算機
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JPS63245525A
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1987-03-31 |
1988-10-12 |
Toshiba Corp |
マイクロプログラム処理装置
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1987-07-20 |
1992-07-28 |
International Business Machines Corporation |
Computer system with logic for writing instruction identifying data into array control lists for precise post-branch recoveries
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1987-08-13 |
1992-03-17 |
Digital Equipment Corporation |
Graphics workstation for creating graphics data structure which are stored retrieved and displayed by a graphics subsystem for competing programs
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1987-08-13 |
1993-10-05 |
Digital Equipment Corporation |
Method of operating a computer graphics system including asynchronously traversing its nodes
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JP2583525B2
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1987-09-30 |
1997-02-19 |
健 坂村 |
データ処理装置
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JP2723238B2
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1988-01-18 |
1998-03-09 |
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情報処理装置
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1988-02-23 |
1996-05-28 |
Mitsubishi Denki Kabushiki Kaisha |
Branch target and next instruction address calculation in a pipeline processor
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JPH01283635A
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1988-05-11 |
1989-11-15 |
Nec Corp |
バッファ制御回路
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1988-07-27 |
1988-09-01 |
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Data processing apparatus
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1988-08-25 |
1992-03-31 |
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Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO
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1988-10-03 |
1991-09-17 |
Duke University |
Method and apparatus for using extracted program flow information to prepare for execution multiple instruction streams
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1988-11-25 |
1996-10-02 |
Nec Corporation |
Microcalculateur capable de traiter rapidement un code d'instruction de branchement
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1988-12-20 |
1992-02-19 |
Fujitsu Limited |
Appareil de traitement d'images et système l'utilisant
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1989-01-13 |
1992-06-30 |
International Business Machines Corporation |
System for reducing delay in instruction execution by executing branch instructions in separate processor while dispatching subsequent instructions to primary processor
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1989-02-03 |
1990-12-19 |
Nec Corp |
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1989-08-28 |
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1989-08-28 |
1997-11-19 |
日本電気株式会社 |
情報処理装置及びその制御方法
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1989-10-23 |
1994-07-12 |
Motorola, Inc. |
Microprocessor which optimizes bus utilization based upon bus speed
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1990-02-26 |
1993-07-20 |
Nexgen Microsystems |
Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence
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1990-06-29 |
1992-02-26 |
Hitachi Ltd |
条件分岐命令制御方式
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1990-11-27 |
1993-07-06 |
Sun Microsystems, Inc. |
Method for selectively transferring data instructions to a cache memory
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1991-02-18 |
1992-09-18 |
Mitsubishi Electric Corp |
マイクロコンピュータ
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1992-02-07 |
1998-06-04 |
三菱電機株式会社 |
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1992-08-27 |
1995-06-06 |
Northern Telecom Limited |
Branch target tagging
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1994-04-28 |
1997-08-19 |
International Business Machines Corporation |
Multiple condition code branching system in a multi-processor environment
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1994-06-22 |
1994-08-10 |
Inmos Ltd |
A computer system for executing branch instructions
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1994-07-29 |
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Sun Microsyst Inc |
ディスパッチされた制御転送命令状態に基づきより高速で命令を先取りするための方法及び装置
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1996-05-07 |
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Lucent Technologies Inc. |
Apparatus and method for aborting un-needed instruction fetches in a digital microprocessor device
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1997-01-30 |
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Toshiba Corp |
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1997-06-30 |
1999-01-29 |
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演算処理装置およびその方法
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1999-09-14 |
Motorola, Inc. |
Method and apparatus for controlling conditional branch execution in a data processor
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1999-09-01 |
2006-08-02 |
Intel Corp |
Instruction de branchement pour processeur
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1999-09-01 |
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Intel Corporation |
Ensemble de registres utilise dans une architecture de processeurs multifiliere paralleles
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2000-01-13 |
2005-06-21 |
Texas Instruments Incorporated |
Processor with conditional instruction execution based upon state of corresponding annul bit of annul code
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2000-02-16 |
2003-10-21 |
Hewlett-Packard Development Company, L.P. |
Method and apparatus for resteering failing speculation check instructions
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2000-08-31 |
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Intel Corporation |
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Intel Corporation |
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2001-08-27 |
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Intel Corporation |
Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms
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2001-08-27 |
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Intel Corporation |
Software controlled content addressable memory in a general purpose execution datapath
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2001-08-27 |
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Intel Corporation |
Multithreaded microprocessor with register allocation based on number of active threads
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2002-01-25 |
2009-10-27 |
Intel Corporation |
Data transfer mechanism using unidirectional pull bus and push bus
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2006-02-21 |
Hitachi, Ltd. |
Control forwarding in a pipeline digital processor
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2002-04-03 |
2008-10-14 |
Intel Corporation |
Registers for data transfers
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2002-05-30 |
2003-12-03 |
STMicroelectronics Limited |
Tampon de préextraction
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2002-06-14 |
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International Business Machines Corporation |
Enhanced instruction prefetch engine
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2002-08-13 |
2008-02-26 |
Intel Corporation |
Free list and ring data structure management
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2003-01-10 |
2005-09-06 |
Intel Corporation |
Memory interleaving
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2011-08-30 |
2013-03-07 |
Empire Technology Development Llc |
Compression matérielle de tableaux
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2020-08-27 |
2023-10-24 |
Ventana Micro Systems Inc. |
Processor that mitigates side channel attacks by expeditiously initiating flushing of instructions dependent upon a load instruction that causes a need for an architectural exception
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2020-08-27 |
2024-01-09 |
Ventana Micro Systems Inc. |
Processor that mitigates side channel attacks by preventing all dependent instructions from consuming architectural register result produced by instruction that causes a need for an architectural exception
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2020-08-27 |
2024-02-20 |
Ventana Micro Systems Inc. |
Processor that mitigates side channel attacks by preventing cache memory state from being affected by a missing load operation by inhibiting or canceling a fill request of the load operation if an older load generates a need for an architectural exception
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2020-10-06 |
2023-08-22 |
Ventana Micro Systems Inc. |
Processor that mitigates side channel attacks by providing random load data as a result of execution of a load operation that does not have permission to access a load address
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2020-10-06 |
2023-08-22 |
Ventana Micro Systems Inc. |
Processor that mitigates side channel attacks by prevents cache line data implicated by a missing load address from being filled into a data cache memory when the load address specifies a location with no valid address translation or no permission to read from the location
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2020-10-06 |
2023-12-26 |
Ventana Micro Systems Inc. |
Processor that mitigates side channel attacks by refraining from allocating an entry in a data TLB for a missing load address when the load address misses both in a data cache memory and in the data TLB and the load address specifies a location without a valid address translation or without permission to read from the location
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