DE3586899T2 - Instruktionsvorgriffsystem fuer bedingte sprungbefehle in einer zentralen verarbeitungseinrichtung. - Google Patents

Instruktionsvorgriffsystem fuer bedingte sprungbefehle in einer zentralen verarbeitungseinrichtung.

Info

Publication number
DE3586899T2
DE3586899T2 DE8585400967T DE3586899T DE3586899T2 DE 3586899 T2 DE3586899 T2 DE 3586899T2 DE 8585400967 T DE8585400967 T DE 8585400967T DE 3586899 T DE3586899 T DE 3586899T DE 3586899 T2 DE3586899 T2 DE 3586899T2
Authority
DE
Germany
Prior art keywords
processing device
central processing
prevention system
conditional jump
jump commands
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585400967T
Other languages
English (en)
Other versions
DE3586899D1 (de
Inventor
William F Bruckert
Tryggve Fossum
Rosa De Jr
Richard E Glackemeyer
Allan E Helenius
John C Manton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of DE3586899D1 publication Critical patent/DE3586899D1/de
Application granted granted Critical
Publication of DE3586899T2 publication Critical patent/DE3586899T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
DE8585400967T 1984-05-21 1985-05-15 Instruktionsvorgriffsystem fuer bedingte sprungbefehle in einer zentralen verarbeitungseinrichtung. Expired - Fee Related DE3586899T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/612,621 US4742451A (en) 1984-05-21 1984-05-21 Instruction prefetch system for conditional branch instruction for central processor unit

Publications (2)

Publication Number Publication Date
DE3586899D1 DE3586899D1 (de) 1993-01-28
DE3586899T2 true DE3586899T2 (de) 1993-07-15

Family

ID=24453941

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585400967T Expired - Fee Related DE3586899T2 (de) 1984-05-21 1985-05-15 Instruktionsvorgriffsystem fuer bedingte sprungbefehle in einer zentralen verarbeitungseinrichtung.

Country Status (9)

Country Link
US (1) US4742451A (de)
EP (1) EP0162778B1 (de)
JP (1) JPS6158044A (de)
AU (1) AU576858B2 (de)
CA (1) CA1226958A (de)
DE (1) DE3586899T2 (de)
DK (1) DK221585A (de)
FI (1) FI851738L (de)
IE (1) IE851252L (de)

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US7681018B2 (en) 2000-08-31 2010-03-16 Intel Corporation Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set
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US6868476B2 (en) 2001-08-27 2005-03-15 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
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US11797673B2 (en) * 2020-08-27 2023-10-24 Ventana Micro Systems Inc. Processor that mitigates side channel attacks by expeditiously initiating flushing of instructions dependent upon a load instruction that causes a need for an architectural exception
US11868469B2 (en) 2020-08-27 2024-01-09 Ventana Micro Systems Inc. Processor that mitigates side channel attacks by preventing all dependent instructions from consuming architectural register result produced by instruction that causes a need for an architectural exception
US11907369B2 (en) 2020-08-27 2024-02-20 Ventana Micro Systems Inc. Processor that mitigates side channel attacks by preventing cache memory state from being affected by a missing load operation by inhibiting or canceling a fill request of the load operation if an older load generates a need for an architectural exception
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Also Published As

Publication number Publication date
EP0162778A2 (de) 1985-11-27
AU4266085A (en) 1985-11-28
EP0162778A3 (en) 1988-02-24
US4742451A (en) 1988-05-03
DK221585D0 (da) 1985-05-20
CA1226958A (en) 1987-09-15
IE851252L (en) 1985-11-21
FI851738L (fi) 1985-11-22
DE3586899D1 (de) 1993-01-28
FI851738A0 (fi) 1985-05-02
JPH0585926B2 (de) 1993-12-09
JPS6158044A (ja) 1986-03-25
EP0162778B1 (de) 1992-12-16
DK221585A (da) 1985-11-22
AU576858B2 (en) 1988-09-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee