DE69943402D1 - Speichersteuerungseinheit und -verfahren und Medium mit Ausführungsprogramm - Google Patents

Speichersteuerungseinheit und -verfahren und Medium mit Ausführungsprogramm

Info

Publication number
DE69943402D1
DE69943402D1 DE69943402T DE69943402T DE69943402D1 DE 69943402 D1 DE69943402 D1 DE 69943402D1 DE 69943402 T DE69943402 T DE 69943402T DE 69943402 T DE69943402 T DE 69943402T DE 69943402 D1 DE69943402 D1 DE 69943402D1
Authority
DE
Germany
Prior art keywords
medium
control unit
memory control
execution program
execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69943402T
Other languages
English (en)
Inventor
Toshiyuki Ochiai
Yosuke Furukawa
Yutaka Tanaka
Kozo Kimura
Makoto Hirai
Tokuzo Kiyohara
Hideshi Nishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Panasonic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP02365198A external-priority patent/JP3922487B2/ja
Priority claimed from JP34452298A external-priority patent/JP4234829B2/ja
Application filed by Panasonic Corp filed Critical Panasonic Corp
Application granted granted Critical
Publication of DE69943402D1 publication Critical patent/DE69943402D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1647—Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Information Transfer Systems (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
DE69943402T 1998-02-04 1999-02-02 Speichersteuerungseinheit und -verfahren und Medium mit Ausführungsprogramm Expired - Lifetime DE69943402D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP02365198A JP3922487B2 (ja) 1998-02-04 1998-02-04 メモリ制御装置および方法
JP34452298A JP4234829B2 (ja) 1998-12-03 1998-12-03 メモリ制御装置

Publications (1)

Publication Number Publication Date
DE69943402D1 true DE69943402D1 (de) 2011-06-16

Family

ID=26361051

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69943402T Expired - Lifetime DE69943402D1 (de) 1998-02-04 1999-02-02 Speichersteuerungseinheit und -verfahren und Medium mit Ausführungsprogramm

Country Status (4)

Country Link
US (1) US6340973B1 (de)
EP (2) EP2357564A3 (de)
CN (1) CN1262929C (de)
DE (1) DE69943402D1 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000148997A (ja) * 1998-11-13 2000-05-30 Minolta Co Ltd 画像処理装置
JP2001356961A (ja) 2000-06-13 2001-12-26 Nec Corp 調停装置
US7168093B2 (en) * 2001-01-25 2007-01-23 Solutionary, Inc. Method and apparatus for verifying the integrity and security of computer networks and implementation of counter measures
JP2004520658A (ja) 2001-05-22 2004-07-08 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ メモリへのアクセス速度を向上させる方法とシステム
JP3868250B2 (ja) * 2001-10-09 2007-01-17 松下電器産業株式会社 データ転送装置、データ転送システム、およびデータ転送方法
JP3778055B2 (ja) * 2001-11-02 2006-05-24 ソニー株式会社 記録再生装置及び記録再生方法
JP2003308246A (ja) * 2002-04-17 2003-10-31 Fujitsu Ltd メモリコントローラのクロック制御装置及び方法
KR100750273B1 (ko) * 2003-01-27 2007-08-17 마츠시타 덴끼 산교 가부시키가이샤 메모리 제어장치
JP2005332370A (ja) * 2004-04-19 2005-12-02 Toshiba Corp 制御装置
JP4748641B2 (ja) 2004-12-06 2011-08-17 ルネサスエレクトロニクス株式会社 情報処理システム
US7275143B1 (en) * 2004-12-13 2007-09-25 Nvidia Corporation System, apparatus and method for avoiding page conflicts by characterizing addresses in parallel with translations of memory addresses
US7930439B2 (en) * 2006-03-31 2011-04-19 Panasonic Corporation Command output control apparatus
CN101082852B (zh) * 2006-05-29 2012-07-18 联阳半导体股份有限公司 用于存储器的控制装置及控制方法
JP2008073895A (ja) * 2006-09-19 2008-04-03 Ricoh Co Ltd 画像形成装置、画像形成方法、画像形成プログラム、及び、情報記録媒体
DE102007005866B4 (de) * 2007-02-06 2021-11-04 Intel Deutschland Gmbh Anordnung, Verfahren und Computerprogramm-Produkt zum Anzeigen einer Folge von digitalen Bildern
US20100325342A1 (en) * 2007-07-20 2010-12-23 Panasonic Corporation Memory controller and nonvolatile storage device using same
CN101539981B (zh) * 2009-05-06 2011-07-20 成都市华为赛门铁克科技有限公司 一种数据安全控制方法、系统及传感器节点
CN101692346B (zh) * 2009-06-19 2013-06-26 无锡中星微电子有限公司 一种存储器数据采样装置及一种采样控制器
US8392689B1 (en) * 2010-05-24 2013-03-05 Western Digital Technologies, Inc. Address optimized buffer transfer requests
CN102402410A (zh) * 2010-09-09 2012-04-04 奇景光电股份有限公司 显示装置及控制方法
CN102411982B (zh) * 2010-09-25 2014-12-10 杭州华三通信技术有限公司 内存控制器及命令控制方法
CN102339261B (zh) * 2011-09-16 2015-09-30 上海智翔信息科技股份有限公司 一种ddr2sdram控制器
KR102650603B1 (ko) * 2018-07-24 2024-03-27 삼성전자주식회사 불휘발성 메모리 장치, 불휘발성 메모리 장치의 동작 방법 및 불휘발성 메모리 장치를 제어하는 메모리 컨트롤러의 동작 방법
CN114048157A (zh) * 2021-11-16 2022-02-15 安徽芯纪元科技有限公司 一种内部总线地址重映射装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5043874A (en) * 1989-02-03 1991-08-27 Digital Equipment Corporation Memory configuration for use with means for interfacing a system control unit for a multi-processor system with the system main memory
JP3039557B2 (ja) * 1989-11-01 2000-05-08 日本電気株式会社 記憶装置
JPH03238539A (ja) * 1990-02-15 1991-10-24 Nec Corp メモリアクセス制御装置
US5295255A (en) * 1991-02-22 1994-03-15 Electronic Professional Services, Inc. Method and apparatus for programming a solid state processor with overleaved array memory modules
JP2938706B2 (ja) 1992-04-27 1999-08-25 三菱電機株式会社 同期型半導体記憶装置
US5600605A (en) * 1995-06-07 1997-02-04 Micron Technology, Inc. Auto-activate on synchronous dynamic random access memory
US5881264A (en) * 1996-01-31 1999-03-09 Kabushiki Kaisha Toshiba Memory controller and memory control system
JP3686155B2 (ja) * 1996-03-21 2005-08-24 株式会社ルネサステクノロジ 画像復号装置
US5864512A (en) * 1996-04-12 1999-01-26 Intergraph Corporation High-speed video frame buffer using single port memory chips
US6026478A (en) * 1997-08-01 2000-02-15 Micron Technology, Inc. Split embedded DRAM processor
US6044206A (en) * 1997-10-14 2000-03-28 C-Cube Microsystems Out of order instruction processing using dual memory banks
US6070227A (en) * 1997-10-31 2000-05-30 Hewlett-Packard Company Main memory bank indexing scheme that optimizes consecutive page hits by linking main memory bank address organization to cache memory address organization
US6205511B1 (en) * 1998-09-18 2001-03-20 National Semiconductor Corp. SDRAM address translator

Also Published As

Publication number Publication date
EP0935199A3 (de) 2005-09-07
EP2357564A2 (de) 2011-08-17
CN1227953A (zh) 1999-09-08
CN1262929C (zh) 2006-07-05
EP2357564A3 (de) 2011-11-23
EP0935199B1 (de) 2011-05-04
US6340973B1 (en) 2002-01-22
EP0935199A2 (de) 1999-08-11

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