DE69634182D1 - Direktspeicherzugriffssteuerung mit programmierbarer Zeitsteuerung - Google Patents

Direktspeicherzugriffssteuerung mit programmierbarer Zeitsteuerung

Info

Publication number
DE69634182D1
DE69634182D1 DE69634182T DE69634182T DE69634182D1 DE 69634182 D1 DE69634182 D1 DE 69634182D1 DE 69634182 T DE69634182 T DE 69634182T DE 69634182 T DE69634182 T DE 69634182T DE 69634182 D1 DE69634182 D1 DE 69634182D1
Authority
DE
Germany
Prior art keywords
memory access
direct memory
control
programmable time
access control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69634182T
Other languages
English (en)
Other versions
DE69634182T2 (de
Inventor
Jeff W Wolford
Robert A Lester
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compaq Computer Corp
Original Assignee
Compaq Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compaq Computer Corp filed Critical Compaq Computer Corp
Application granted granted Critical
Publication of DE69634182D1 publication Critical patent/DE69634182D1/de
Publication of DE69634182T2 publication Critical patent/DE69634182T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/30—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/287—Multiplexed DMA
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/3625—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a time dependent access

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
DE69634182T 1995-03-03 1996-02-27 Direktspeicherzugriffssteuerung mit programmierbarer Zeitsteuerung Expired - Lifetime DE69634182T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/398,358 US5603050A (en) 1995-03-03 1995-03-03 Direct memory access controller having programmable timing
US398358 1995-03-03

Publications (2)

Publication Number Publication Date
DE69634182D1 true DE69634182D1 (de) 2005-02-24
DE69634182T2 DE69634182T2 (de) 2005-06-30

Family

ID=23575079

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69634182T Expired - Lifetime DE69634182T2 (de) 1995-03-03 1996-02-27 Direktspeicherzugriffssteuerung mit programmierbarer Zeitsteuerung

Country Status (3)

Country Link
US (3) US5603050A (de)
EP (1) EP0730235B1 (de)
DE (1) DE69634182T2 (de)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5603050A (en) * 1995-03-03 1997-02-11 Compaq Computer Corporation Direct memory access controller having programmable timing
US5850529A (en) * 1995-08-11 1998-12-15 Kabushiki Kaisha Toshiba Method and apparatus for detecting a resource lock on a PCI bus
JPH0981507A (ja) * 1995-09-08 1997-03-28 Toshiba Corp コンピュータシステム
US5857117A (en) * 1995-12-22 1999-01-05 Intel Corporation Apparatus and method for multiplexing integrated device electronics circuitry with an industry standard architecture bus
US5859990A (en) * 1995-12-29 1999-01-12 Intel Corporation System for transferring data segments from a first storage device to a second storage device using an alignment stage including even and odd temporary devices
US5864696A (en) * 1996-01-19 1999-01-26 Stmicroelectronics, Inc. Circuit and method for setting the time duration of a write to a memory cell
US5740452A (en) * 1996-03-29 1998-04-14 Vlsi Technology, Inc. System for passing Industry Standard Architecture (ISA) legacy interrupts across Peripheral Component Interconnect (PCI) connectors and methods therefor
US5905912A (en) * 1996-04-08 1999-05-18 Vlsi Technology, Inc. System for implementing peripheral device bus mastering in a computer using a list processor for asserting and receiving control signals external to the DMA controller
US5774743A (en) * 1996-04-08 1998-06-30 Vlsi Technology, Inc. System for implementing peripheral device bus mastering in mobile computer via micro-controller for programming DMA controller, generating and sending command signals, and receiving completion status
US5809333A (en) * 1996-04-08 1998-09-15 Vlsi Technology, Inc. System for implementing peripheral device bus mastering in desktop PC via hardware state machine for programming DMA controller, generating command signals and receiving completion status
US5822568A (en) * 1996-05-20 1998-10-13 Advanced Micro Devices, Inc. System for improving the real-time functionality of a personal computer which employs an interrupt servicing DMA controller
US5867733A (en) * 1996-06-04 1999-02-02 Micron Electronics, Inc. Mass data storage controller permitting data to be directly transferred between storage devices without transferring data to main memory and without transferring data over input-output bus
US6170031B1 (en) * 1997-07-08 2001-01-02 Seagate Technology Llc Read/write state machines for transferring data to/from host interface in a digital data storage system
US5938744A (en) * 1997-11-04 1999-08-17 Aiwa/Raid Technlogy, Method for managing multiple DMA queues by a single controller
US6112272A (en) * 1998-06-02 2000-08-29 Adaptec, Inc. Non-invasive bus master back-off circuit and method for systems having a plurality of bus masters
KR20010102285A (ko) * 1999-02-22 2001-11-15 마이클 골위저, 호레스트 쉐퍼 직접 메모리 접근 촉진 방법 및 장치
US6334163B1 (en) * 1999-03-05 2001-12-25 International Business Machines Corp. Elastic interface apparatus and method therefor
US6255869B1 (en) * 1999-09-29 2001-07-03 Agere Systems Guardian Corp. Method and apparatus for system resource negotiation
TW448365B (en) * 1999-11-15 2001-08-01 Via Tech Inc Bus arbitration method providing preemption function between control chip sets
US7007122B2 (en) * 2002-11-27 2006-02-28 Lsi Logic Corporation Method for pre-emptive arbitration
JP2005056067A (ja) 2003-08-01 2005-03-03 Matsushita Electric Ind Co Ltd Ｄｍａ転送制御装置
JP4293141B2 (ja) * 2005-02-18 2009-07-08 セイコーエプソン株式会社 データ転送制御装置及び電子機器
US7930444B2 (en) * 2005-06-30 2011-04-19 Freescale Semiconductor, Inc. Device and method for controlling multiple DMA tasks
WO2007003984A1 (en) 2005-06-30 2007-01-11 Freescale Semiconductor, Inc. Device and method for arbitrating between direct memory access task requests
JP2009510543A (ja) * 2005-06-30 2009-03-12 フリースケール セミコンダクター インコーポレイテッド Ｄｍａタスクの実行を制御するためのデバイスおよび方法
US7428603B2 (en) * 2005-06-30 2008-09-23 Sigmatel, Inc. System and method for communicating with memory devices via plurality of state machines and a DMA controller
EP1899827B1 (de) * 2005-06-30 2010-09-08 Freescale Semiconductor, Inc. Einrichtung und verfahren zum ausführen einer dma-task
WO2007083197A1 (en) 2006-01-18 2007-07-26 Freescale Semiconductor Inc. Device having data sharing capabilities and a method for sharing data
US20080120471A1 (en) * 2006-11-06 2008-05-22 On Demand Microelectronics Method and apparatus for least-recently-used replacement of a block frame in an electronic memory device
US9405683B2 (en) * 2007-11-06 2016-08-02 Samsung Electronics Co., Ltd. Processor and memory control method for allocating instructions to a cache and a scratch pad memory
KR101312281B1 (ko) * 2007-11-06 2013-09-30 재단법인서울대학교산학협력재단 프로세서 및 메모리 제어 방법
JP2010044814A (ja) * 2008-08-11 2010-02-25 Toshiba Storage Device Corp 記憶装置の制御方法及び記憶装置
US9336357B2 (en) 2012-09-28 2016-05-10 Intel Corporation Secure access management of devices
US20170091896A1 (en) * 2015-09-30 2017-03-30 Samsung Display Co., Ltd. Independent multi-source display device

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3236302A1 (de) * 1982-09-30 1984-04-05 Siemens AG, 1000 Berlin und 8000 München Speicherprogrammierbare steuerung
JPS6385955A (ja) * 1986-09-30 1988-04-16 Toshiba Corp ダイレクトメモリアクセス転送制御装置
BG45675A1 (en) * 1987-10-16 1989-07-14 Tsentralen Inst Za Izchislitel Controlling device for direct access
US5041962A (en) * 1989-04-14 1991-08-20 Dell Usa Corporation Computer system with means for regulating effective processing rates
JP2978539B2 (ja) * 1989-07-24 1999-11-15 日本電気株式会社 データ転送制御装置
JPH03269659A (ja) * 1990-03-19 1991-12-02 Nec Corp マイクロプロセッサ
US5452432A (en) * 1990-08-14 1995-09-19 Chips And Technologies, Inc. Partially resettable, segmented DMA counter
US5333294A (en) * 1990-10-09 1994-07-26 Compaq Computer Corporation Configurable data width direct memory access device with a read address counter and a write address counter which increments the addresses based on the desired data transfer width
US5239631A (en) * 1991-10-15 1993-08-24 International Business Machines Corporation Cpu bus allocation control
JPH05108548A (ja) * 1991-10-15 1993-04-30 Nec Ic Microcomput Syst Ltd Ｄｍａコントローラ
US5471640A (en) * 1992-07-06 1995-11-28 Hewlett-Packard Programmable disk array controller having n counters for n disk drives for stripping data where each counter addresses specific memory location by a count n
US5603050A (en) * 1995-03-03 1997-02-11 Compaq Computer Corporation Direct memory access controller having programmable timing

Also Published As

Publication number Publication date
US5884095A (en) 1999-03-16
EP0730235B1 (de) 2005-01-19
DE69634182T2 (de) 2005-06-30
EP0730235A1 (de) 1996-09-04
US5603050A (en) 1997-02-11
US5692216A (en) 1997-11-25

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Legal Events

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