DE69731066D1 - Speichersteuerungsvorrichtung mit programmierbarer Impulsverzögerung - Google Patents

Speichersteuerungsvorrichtung mit programmierbarer Impulsverzögerung

Info

Publication number
DE69731066D1
DE69731066D1 DE69731066T DE69731066T DE69731066D1 DE 69731066 D1 DE69731066 D1 DE 69731066D1 DE 69731066 T DE69731066 T DE 69731066T DE 69731066 T DE69731066 T DE 69731066T DE 69731066 D1 DE69731066 D1 DE 69731066D1
Authority
DE
Germany
Prior art keywords
control device
memory control
pulse delay
programmable pulse
programmable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69731066T
Other languages
English (en)
Other versions
DE69731066T2 (de
Inventor
Pierre-Yves Thoulon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of DE69731066D1 publication Critical patent/DE69731066D1/de
Application granted granted Critical
Publication of DE69731066T2 publication Critical patent/DE69731066T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4239—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)
DE69731066T 1997-01-23 1997-01-23 Speichersteuerungsvorrichtung mit programmierbarer Impulsverzögerung Expired - Fee Related DE69731066T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP97410009A EP0855653B1 (de) 1997-01-23 1997-01-23 Speichersteuerungsvorrichtung mit programmierbarer Impulsverzögerung

Publications (2)

Publication Number Publication Date
DE69731066D1 true DE69731066D1 (de) 2004-11-11
DE69731066T2 DE69731066T2 (de) 2005-10-06

Family

ID=8229944

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69731066T Expired - Fee Related DE69731066T2 (de) 1997-01-23 1997-01-23 Speichersteuerungsvorrichtung mit programmierbarer Impulsverzögerung

Country Status (3)

Country Link
EP (1) EP0855653B1 (de)
JP (1) JPH10232818A (de)
DE (1) DE69731066T2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6067594A (en) 1997-09-26 2000-05-23 Rambus, Inc. High frequency bus system
US7050959B1 (en) 1999-12-23 2006-05-23 Intel Corporation Dynamic thermal management for integrated circuits
US6578125B2 (en) * 2000-02-14 2003-06-10 Sanyo Electric Co., Ltd. Memory access circuit and memory access control circuit
JP2001337862A (ja) * 2000-05-29 2001-12-07 Fujitsu Ltd メモリシステム及びそのセットアップ方法
WO2002001363A1 (fr) * 2000-06-27 2002-01-03 Matsushita Electric Industrial, Co., Ltd. Dispositif et procede de commande de memoire
KR100389916B1 (ko) * 2000-08-28 2003-07-04 삼성전자주식회사 메모리 모듈 및 메모리 컨트롤러
US6553472B2 (en) * 2001-01-12 2003-04-22 Sun Microsystems, Inc. Method for programming clock delays, command delays, read command parameter delays, and write command parameter delays of a memory controller in a high performance microprocessor
DE60220863T2 (de) * 2001-04-24 2008-03-13 Rambus Inc., Los Altos Verfahren und Gerät zum Koordinieren von Speicheroperationen zwischen unterschiedlich angeordneten Speicherkomponenten
US8391039B2 (en) 2001-04-24 2013-03-05 Rambus Inc. Memory module with termination component
US6675272B2 (en) 2001-04-24 2004-01-06 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components
US6697926B2 (en) 2001-06-06 2004-02-24 Micron Technology, Inc. Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device
US6918048B2 (en) * 2001-06-28 2005-07-12 Intel Corporation System and method for delaying a strobe signal based on a slave delay base and a master delay adjustment
US20040215912A1 (en) * 2003-04-24 2004-10-28 George Vergis Method and apparatus to establish, report and adjust system memory usage
EP1479883A1 (de) 2003-05-10 2004-11-24 Universität Stuttgart Verfahren und Vorrichtung zur Reinigung von Abgasen
US7301831B2 (en) 2004-09-15 2007-11-27 Rambus Inc. Memory systems with variable delays for write data signals
US7966439B1 (en) * 2004-11-24 2011-06-21 Nvidia Corporation Apparatus, system, and method for a fast data return memory controller
CN101401165B (zh) * 2006-03-13 2012-08-29 Nxp股份有限公司 电子电路、双倍数据率接口和处理器以及双倍数据率传输的方法
CN101925885A (zh) * 2008-01-29 2010-12-22 松下电器产业株式会社 存储器存取定时调整装置以及存储器存取定时调整方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5335337A (en) * 1989-01-27 1994-08-02 Digital Equipment Corporation Programmable data transfer timing
US5572722A (en) * 1992-05-28 1996-11-05 Texas Instruments Incorporated Time skewing arrangement for operating random access memory in synchronism with a data processor
US5509138A (en) * 1993-03-22 1996-04-16 Compaq Computer Corporation Method for determining speeds of memory modules
US5557782A (en) * 1994-07-12 1996-09-17 Zenith Data Systems Corporation Flexible deterministic state machine
WO1997015897A1 (en) * 1995-10-26 1997-05-01 Motorola Inc. Method and device for encoding/decoding a displaced frame difference

Also Published As

Publication number Publication date
EP0855653A1 (de) 1998-07-29
EP0855653B1 (de) 2004-10-06
DE69731066T2 (de) 2005-10-06
JPH10232818A (ja) 1998-09-02

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee