WO2002001363A1 - Dispositif et procede de commande de memoire - Google Patents

Dispositif et procede de commande de memoire Download PDF

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Publication number
WO2002001363A1
WO2002001363A1 PCT/JP2001/005412 JP0105412W WO0201363A1 WO 2002001363 A1 WO2002001363 A1 WO 2002001363A1 JP 0105412 W JP0105412 W JP 0105412W WO 0201363 A1 WO0201363 A1 WO 0201363A1
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WIPO (PCT)
Prior art keywords
memory control
delay adjustment
control device
memory
data
Prior art date
Application number
PCT/JP2001/005412
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English (en)
Japanese (ja)
Inventor
Daisuke Kondou
Yasushi Ueda
Toru Aoki
Original Assignee
Matsushita Electric Industrial, Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial, Co., Ltd. filed Critical Matsushita Electric Industrial, Co., Ltd.
Publication of WO2002001363A1 publication Critical patent/WO2002001363A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Definitions

  • the present invention relates to a memory control, and more particularly to a memory control having a characteristic with respect to a timing at which data recorded in a DRAM is taken into a read data register.
  • FIG. 12 is a configuration diagram of a conventional memory control device and t-RAM.
  • reference numeral 101 denotes a memory control device, which includes an enable signal generation unit 111, a delay circuit 112, and a read data storage register 113.
  • Reference numeral 121 denotes a DRAM: and 122 denotes a data bus which is a data path between the memory control device 101 and the DRAM 121.
  • the operation of the conventional memory control device having the above configuration is as follows.
  • the enable signal generator 111 indicates the value of Higii or Low.
  • the enable signal is output to the DRAM 121.
  • the DRAM 121 outputs the read data on the data path 122 when the enable signal is Low, that is, when the active state is activated.
  • the enable signal generated by the rice pull signal generation unit 111 is also output to the delay circuit 112.
  • the enable signal input to the delay circuit 1 1 2 has its polarity inverted and is used as a trigger signal delayed by the setup time of the read data storage register 1 13 as a read data storage register 1 1 Output to 3.
  • the setup time is the time during which stable input data must be added before the trigger signal rises in order to load normal data into the read data storage register. is there.
  • the read data storage register 113 takes in the read data that has been output from the DRAM 121 and is fixed on the data bus 122 by using a trigger signal.
  • the DRAM outputs read data to the data bus 122 by outputting an enable signal.
  • a DRAM such as a synchronous DRAM (SDRAM)
  • SDRAM synchronous DRAM
  • all the operations are performed by a clock.
  • Synchronous when a read command is output to such an SDRAM, read data is output on the read bus after a predetermined time has elapsed after the command is accepted, and this type of memory control is determined.
  • Devices also exist. In such a memory controller, the “predetermined time” and the time during which data is determined on the read path are all uniquely set with respect to the rising edge of the clock of the SDRAM. Thus, data can be output without using an enable signal.
  • the timing of the data capture given by the trigger signal is fixed, wiring delay occurs due to temperature changes, etc., and the capture timing is set at a time when the read data is not fixed on the data bus 122. Possibilities arise. Also, the wiring delay varies depending on the distance between the memory controller 101 and the DRAM 122, so that it is necessary to reset the data fetch timing every time the wiring is performed. For example, when a designed circuit is implemented as an LSI, if the wiring distance to the storage register is long, the read data from the DRAM, which is the input signal of the LSI, means that the read data has not yet been determined at the rise of the trigger signal. , Setup time is not satisfied and data cannot be stored. Therefore, in order to adjust the rise time of the trigger signal in consideration of those wiring delays, it is necessary to reset the data acquisition timing. This is the same in a memory control device that does not use an enable signal and is used for an SDRAM or the like. Disclosure of the invention
  • the present invention has been made in view of the above problems, and has as its object to provide a memory control device capable of acquiring read data at an optimal acquisition timing even when a wiring delay occurs in a data path. aimed to.
  • a first invention (corresponding to claim 1) includes a clock generation circuit for generating a clock
  • a delay adjustment process for delaying the variable delay value with a variable delay value And a delay adjustment circuit that outputs the captured clock.
  • a memory control device comprising: a read data register for reading data stored in a memory based on the fetch clock and storing the read data.
  • a second aspect of the present invention (corresponding to claim '2) is the present invention, wherein the delay adjustment circuit starts the delay adjustment processing based on an environmental change around the memory control device.
  • a third aspect of the present invention (corresponding to claim 3) is the present invention, wherein the delay adjustment circuit starts the delay adjustment processing at a predetermined cycle.
  • a fourth aspect of the present invention (corresponding to claim 4) is the above-described aspect of the present invention, wherein the delay adjustment circuit starts delay adjustment processing based on an error detection or error correction operation for the memory.
  • a fifth aspect of the present invention (corresponding to claim 5) is the above-mentioned aspect of the present invention, wherein the delay adjustment circuit varies the delay value based on an environmental change around the memory control device.
  • a sixth aspect of the present invention is the present invention, wherein the delay adjustment circuit varies the delay value based on a predetermined cycle.
  • a seventh aspect of the present invention (corresponding to claim 7) is that the delay adjustment circuit has one or a plurality of delay elements,
  • the present invention is the above-mentioned invention in which the clock delay processing is performed by passing the clock through a predetermined number of the delay elements.
  • An eighth aspect of the present invention is the above-described aspect of the present invention, wherein the delay adjustment circuit can adjust a delay amount in the delay adjustment processing by external control.
  • a ninth invention is a comparison data register for storing the same data as data to be recorded in the memory, A comparison circuit that compares the data stored in the read data register with the data stored in the comparison data register, wherein a predetermined address in the memory is set in the comparison data register; After the data is written, the read data register reads the predetermined data, and the comparison circuit reads the predetermined data in the read data register and the predetermined data in the comparison data register.
  • the present invention is the above-mentioned present invention, which performs a write / read confirmation process for collating with the data of the above.
  • a tenth aspect of the present invention (corresponding to claim 10) further comprises a register whose contents can be rewritten from the outside,
  • the present invention is the above-described present invention, wherein the comparison circuit performs the write Z read confirmation process using the data set in the register.
  • the eleventh present invention is the present invention in which the register is at least set to the predetermined address of the memory.
  • the delay adjustment circuit performs the delay adjustment processing after the end of the write / read confirmation processing.
  • the comparison circuit After the delay adjustment processing is performed, the comparison circuit performs write Z read repetition confirmation processing for performing the write / read confirmation processing again, and performs the write Z read confirmation processing or the write / read confirmation processing. And the delay value is optimized by the write Z-read repetition confirmation processing.
  • a thirteenth aspect of the present invention (corresponding to claim 13) is the above-described aspect of the present invention, in which the delay adjustment circuit performs the delay adjustment processing when a control signal is input from the outside.
  • a fourteenth aspect of the present invention is that the external signal is The present invention is the signal indicating that the power of the memory control device is turned on.
  • a fifteenth aspect of the present invention is the present invention, wherein the external signal is a signal indicating initialization or reset of the memory control device.
  • a sixteenth aspect of the present invention (corresponding to claim 16) is the present invention, wherein the external signal is a signal indicating a return from the sleep state of the memory control device.
  • the seventeenth invention (corresponding to claim 17) further comprises an arbitration circuit for confirming the access of the block having the access right to the memory and determining the access priority of the block.
  • the delay adjustment circuit is the present invention that performs the delay adjustment processing. .
  • the eighteenth aspect of the present invention (corresponding to claim 18) is that, when the arbitration circuit confirms that the block is accessing the memory, the delay adjustment circuit performs the delay adjustment processing.
  • the present invention does not perform the above.
  • a nineteenth invention (corresponding to claim 19) further comprises a counter for counting the number of times that can be set externally or by the register, wherein the arbitration circuit is configured so that the block accesses the memory.
  • the delay adjustment circuit does not perform the delay adjustment processing, increments the value of the counter, and performs the delay adjustment processing when the value of the counter reaches a predetermined value. It is an invention.
  • the 20th invention (corresponding to claim 20) further includes a timer for measuring time
  • the delay adjustment circuit In the present invention, the delay adjustment processing is performed every interval.
  • a twenty-first invention (corresponding to claim 21) is the present invention, wherein the predetermined time can be set in the register.
  • the second 2 of the present invention (corresponding to claim 2 2) is provided with further temperature monitor for measuring the temperature, 1
  • the delay adjustment circuit according to the present invention, wherein the delay adjustment circuit performs the delay adjustment processing based on a temperature change of the block having an access right to the memory.
  • a predetermined temperature can be set in the register.
  • the present invention is the above-described present invention, wherein when the temperature monitor detects the predetermined temperature, the delay adjustment processing is performed. '
  • a twenty-fourth aspect of the present invention (corresponding to claim 24) further includes a voltage monitor for measuring a voltage
  • the delay adjusting circuit performs the delay adjusting process based on a block having an access right to the memory or a voltage change of the memory control device.
  • a predetermined voltage can be set in the register
  • the present invention is the above-described present invention, wherein the delay adjustment process is performed when the voltage monitor detects a voltage equal to or higher than the predetermined voltage.
  • a twenty-sixth aspect of the present invention is a method for detecting an error when an error detection block having an access right to the memory detects an error by accessing the memory.
  • the delay adjustment circuit is the present invention that performs the delay adjustment processing.
  • a twenty-seventh aspect of the present invention is characterized in that when an error correction block having an access right to the memory performs error correction by accessing the memory, However, when the number of times becomes larger than a predetermined number, the delay adjustment circuit performs the delay adjustment processing. 1
  • the twenty-eighth invention (corresponding to claim 28) is characterized in that, when the number of times that the block having access right to the memory writes data to the memory reaches a predetermined number,
  • the delay adjusting circuit is the present invention that performs the delay adjusting process.
  • a twentieth invention (corresponding to claim 29) is the invention described above, wherein the predetermined number of times can be set in the register.
  • the provision of the delay adjustment circuit enables the read data capture timing to be adjusted even during actual operation, and sets the capture timing at a time when the read data is always determined. Will be able to be captured. This makes it possible to perform the layout without considering the wiring delay between the memory controller and the DRAM.
  • a thirty-fifth aspect of the present invention includes: a clock generation step of generating a clock;
  • a read data register storing step of reading data recorded in a memory and storing the read data in a read data register based on the capture clock.
  • the delay adjustment step is characterized in that the delay adjustment processing is performed based on an environmental change around the memory controller.
  • the present invention is to start the above.
  • a thirty-second aspect of the present invention (corresponding to claim 32) is the present invention, wherein the delay adjustment step starts the delay adjustment processing at a predetermined cycle.
  • a thirty-third aspect of the present invention (corresponding to claim 33) is the present invention in which the delay adjustment step starts a delay adjustment process based on an error detection or error correction operation for the memory.
  • a thirty-fourth aspect of the present invention includes: a comparison data register storing step of storing the same data as the data to be recorded in the memory in the comparison data register;
  • a thirty-fifth aspect of the present invention is the memory control device according to the first aspect of the present invention, wherein the clock generation circuit generates a clock.
  • the computer functions as all or a part of a delay adjustment circuit that performs delay adjustment processing for delaying and outputs as a capture clock, and a read data register that reads and stores data recorded in a memory based on the capture clock. It is a program for
  • the 36th invention (corresponding to claim 36) is a 30th invention of the present invention.
  • the computer executes all or part of a read data register storage step of reading data recorded in a memory and storing the data in a read data register. It is a program.
  • a thirty-seventh aspect of the present invention is the memory control device according to the first aspect of the present invention, wherein the clock generation circuit generates a clock, and the clock is delayed by a variable delay value.
  • a delay adjustment circuit that performs delay adjustment processing to output the data as a capture clock, and a read data register that reads and stores data recorded in a memory based on the capture clock.
  • a thirty-eighth aspect of the present invention is a memory control method according to a thirtieth aspect of the present invention, wherein the clock generating step of generating a clock; A delay adjustment step of performing delay adjustment processing for delaying the data and outputting it as a capture clock; and a read data register for reading data recorded in a memory based on the capture clock and storing the data in a read data register.
  • a medium that carries a program for causing a computer to execute all or a part of the storage process and is a medium that can be processed by a computer.
  • FIG. 1 is a block diagram of a memory control apparatus according to the first embodiment of the present invention
  • FIG. 2 is a timing chart for storing read data from the DRAM.
  • FIG. 3 is a configuration diagram of a memory control device according to Embodiment 2 of the present invention.
  • FIG. 4 is a configuration diagram of a memory control device according to Embodiment 3 of the present invention.
  • FIG. 5 is a configuration diagram of a memory control device according to Embodiment 4 of the present invention.
  • FIG. 6 is a configuration diagram of a memory control device according to the fifth embodiment of the present invention.
  • FIG. 7 is a configuration diagram of a memory control device according to Embodiment 6 of the present invention.
  • FIG. 8 is a configuration diagram of a memory control device according to Embodiment 7 of the present invention.
  • FIG. 9 is a configuration diagram of a memory control device according to Embodiment 8 of the present invention.
  • FIG. 10 is a configuration diagram of a memory control device according to Embodiment 9 of the present invention.
  • FIG. 11 is a configuration diagram of a memory control device in which the embodiments of the present invention are collectively configured.
  • FIG. 12 is a configuration diagram of a memory control device according to a conventional technique.
  • Figure 13 is a timing chart for storing read data from the DRAM of the prior art.
  • FIG. 14 (a) is a diagram for describing an example of the write Z-read process according to the second embodiment of the present invention. '
  • FIG. 14B is a diagram for explaining an example of the write / read processing according to the second embodiment of the present invention.
  • FIG. 1 is a configuration diagram of a memory control device according to a first embodiment of the present invention.
  • 1 is a memory control device, and 1 is a capture clock.
  • a generation circuit, 12 is a delay adjustment circuit, 13 is a read data register, and 31 is a DRAM.
  • 100 is an rice signal generator, and 110 is a data path.
  • FIG. 2 is a diagram showing the timing of storing data read from the DRAM 31 in the read data register 13.
  • the time during which the data read from the DRAM 31 is determined on the data bus 110 (t_data) is determined by the period of the enable signal output from the enable signal generator 100, and the time The read data must be loaded into the read data register 13.
  • the delay adjustment circuit 12 adjusts the delay time and outputs the adjusted capture clock to the read data register 13.
  • the read data can be stored in the read data register 13 even if the time during which the read data is determined on the data bus 110 fluctuates due to wiring delay or the like.
  • the setting of the delay value in the delay adjustment circuit 12 is performed as follows. In advance, determine an appropriate delay value from the specifications of the DRAM 31 and the wiring delay of the read data, enable signal, etc. from the DRAM 31 and set it at approximately the center of the fixed time of the read data on the output data bus 110. Set the value so that the capture clock comes, and set this as the initial value.
  • the delay value in the delay adjustment circuit 12 is reset according to that, and the read data is read. You can adjust the amount of delay in the capture window so that it is time to capture it reliably.
  • the read data is always stored on the data bus 110.
  • the data can be surely taken into the read data register 13 at the time determined above.
  • a plurality of delay elements may be provided, and the number of delay elements that pass through the intake port may be changed according to a desired delay value.
  • Means for changing the delay value according to the control of an external CPU or the like may be used. .
  • the memory control device includes a circuit necessary for confirming whether or not the write / read operation can be normally performed on the DRAM 31. This will be described below with reference to FIG.
  • FIG. 3 is a configuration diagram of a memory control device according to Embodiment 2 of the present invention.
  • Reference numeral 14 denotes a comparison data register
  • reference numeral 15 denotes a comparison circuit
  • reference numeral 19 denotes a register
  • reference numeral 32 denotes a block A.
  • the description of the enable signal generation circuit 100 is omitted because the same configuration and operation as those of the first embodiment are performed.
  • the comparison data register When data is written from the block A32 to the DRAM31, the comparison data register stores the same data from the block A32.
  • the comparison circuit 15 compares the read data with the data stored in the read data register 13. And compare it with the data stored in the data register 14.
  • comparison circuit 15 If the comparison result of comparison circuit 15 is the same, it was written to DRAM 31 If the capture clock is set within the time that the data is read data is determined, and there is a discrepancy in the comparison result, the capture clock is shifted, so the delay adjustment circuit 12 resets the delay value. It is possible to confirm that it is necessary to carry out.
  • the data written in the DRAM 31 and the address in the DRAM 31 can be specified by setting the register 19 which can be rewritten from the outside.
  • the data read to the read data register 13 and the data in the comparison data register 14 are Is referred to as a write Z read process.
  • the delay value data in the delay adjustment circuit 12 may be set in the register 19, or the fetched clock input to the delay adjustment circuit 12 may be inverted, and Alternatively, data such as inversion control data for adjustment by the delay adjustment circuit 12 1 may be set and used for the write / read processing.
  • FIG. 14 shows an example of the inversion control data. As shown in Fig.
  • the capture clock if the capture clock is set at a timing when the read data is not determined, the write / read signal is inverted by the inversion control data as shown in Fig. 14 (b). Inverts the capture clock during read processing. Thus, the capture clock can be set at the timing when the read data is determined.
  • the read data from the DRAM 31 is set within the range determined on the data path 110 and the read data is set. It is not known at which timing in the range where the data is fixed the capture timer is set. In this case, a small delay may cause the capture clock to shift to the time domain where the read data is not determined. In such a case, write an arbitrary value to the DRAM 31 and make sure that the value can be read.
  • ⁇ Set a predetermined delay value in the delay adjustment circuit 12 and check with the method described above. I do.
  • the delay value in the delay adjusting circuit 12 is set to a value different from the predetermined value, and the write / read processing is performed again. At this time, the delay value may be set to the front or the back of the time arbitrarily. For example, by alternately setting the front and the back, it is possible to determine the direction of the delay value shift. Become.
  • the delay adjusting circuit 12 sets the center value of the delay value having the predetermined range as the final delay value.
  • the memory control device of the present embodiment it is possible to set the capture clock at a timing at which the data of DRAM 31 can be reliably read.
  • the memory control device is such that the delay adjustment processing is performed when an external signal is input. This will be described below with reference to FIG.
  • FIG. 4 is a configuration diagram of a memory control device according to Embodiment 3 of the present invention.
  • the same or corresponding parts as those in FIG. 21 is an arbitration circuit.
  • Description of the enable signal generation circuit 100 is omitted because it performs the same configuration and operation as in the first embodiment.
  • the signal input to the memory control device 1 as an external signal includes a signal indicating a power-on, a reset signal, and a signal indicating a return from a sleep state of the power supply.
  • the delay adjustment circuit 12 performs the delay adjustment processing when an external signal is input, thereby setting before the block A32 accesses the DRAM 31.
  • the read data from the DRAM 31 can be surely taken into the read data register 13.
  • the arbitration circuit 21 block A 32 is not accessing the DRAM 31, and during that time, the delay adjustment circuit 12 performs delay adjustment processing.
  • the time when the DRAM 31 is not accessed can be effectively used without interrupting the access to the DRAM 31 of the block A32, and the data of the DRAM 31 can always be read reliably. It becomes possible to do.
  • the arbitration circuit 21 is mounted on the configuration of the second embodiment
  • the arbitration circuit may be added to the configuration of the first embodiment. Can obtain the same effect as that of the present embodiment c (Embodiment 4).
  • FIG. 5 is a configuration diagram of a memory control device according to Embodiment 4 of the present invention.
  • the same or corresponding parts as in FIGS. 1 to 4 are denoted by the same reference numerals, and description thereof will be omitted.
  • 16 is a timer
  • 20 is a counter.
  • the enable signal generation circuit 100 has the same configuration and operation as the first embodiment, so that the description is omitted.
  • Embodiment 4 of the present invention having the above configuration
  • the operation of the device will be described, and an embodiment of the memory control method according to the present invention will be described.
  • portions common to Embodiments 2 to 4 are omitted, and only differences are described.
  • the time is set by the timer 16 and the delay adjusting circuit 12 performs the delay adjusting process at a fixed time interval, which is an example of the predetermined time of the present invention, set in the timer 16.
  • the fixed time interval may be set by an external register 19 to be adjustable, or may be a fixed value held by the delay adjustment circuit 12. Good.
  • the register 19 may be omitted.
  • the arbitration circuit 21 permits access to the DRA 31 of the block A 32, and if the access is being made, the arbitration circuit 21 gives priority to the access to the DRA 31 and delay adjustment processing is performed. Is not performed, or the delay adjustment processing a is performed after the access of the block A32 to the DRAM 31 is completed.
  • the counter 20 counts the number of times that the access of the block A32 has priority, and the count value is incremented to a certain number. If it has, the priority of block A32 is lowered and the delay adjustment circuit 12 performs delay adjustment processing.
  • the memory control device of the present embodiment it is possible to always reliably read the data of DRAM 31 by adjusting the delay value periodically.
  • FIG. 6 is a configuration diagram of a memory control device according to Embodiment 5 of the present invention.
  • the same or corresponding parts as in FIGS. 1 to 4 are denoted by the same reference numerals, and description thereof will be omitted.
  • 17 is a temperature monitor.
  • the enable signal generation circuit 100 has the same configuration and operation as in the first embodiment, so that the description is omitted. '
  • the temperature monitor 17 monitors the temperatures of the DRAM 31 and the memory controller 1, and if there is a change from the temperature when the block A 32 previously accessed the DRAM 31, the delay adjustment circuit 1 2 performs delay adjustment processing. This makes it possible to set the optimum delay value according to the temperature change during operation.
  • the temperature at which the delay adjustment circuit 12 performs the delay adjustment is not limited to the temperature of the previous DRAM 31 and the memory controller 1 but may be a value that can be externally set by the register 19. You may. Of course, the register 19 may be omitted.
  • the arbitration circuit 21 if the arbitration circuit 21 permits access to the DRAM 31 of the block A32 and the access is being made, the arbitration circuit 21 gives priority to that access and does not perform the delay adjustment processing. Alternatively, the delay adjustment processing is performed after the access to the DRAM 31 of the block A32 is completed.
  • counter 20 counts the number of times block A32 has been given priority in access. When the count value reaches a certain number, the priority of block A32 is lowered, and the delay adjustment circuit 12 performs delay adjustment processing.
  • the delay value is adjusted, so that the DRAM 31 data can always be read reliably. It is possible to do.
  • FIG. 7 is a configuration diagram of a memory control device according to Embodiment 6 of the present invention.
  • the same or corresponding parts as in FIGS. 1 to 4 are denoted by the same reference numerals, and description thereof will be omitted.
  • Reference numeral 18 denotes a power supply voltage monitor. The description of the enable signal generation circuit 100 is omitted because the same configuration and operation as in the first embodiment are performed.
  • Embodiment 5 of the present invention having the above-described configuration will be described below, and an embodiment of the memory control method of the present invention will be described. However, parts common to Embodiments 2 to 5 are omitted, and only differences are described.
  • the wiring delay changes to the data path 110 due to a change in the power supply voltage or the like, and there is a possibility that the read data cannot be taken.
  • the power supply voltage monitor 18 monitors the power supply voltage of the memory controller 1 and delays if there is a change from the voltage when block A 32 previously accessed the DRAM 31.
  • Adjustment circuit 12 performs delay adjustment processing. This makes it possible to set the optimum delay value according to the voltage change during operation.
  • the voltage at which the delay adjustment circuit 12 performs the delay adjustment is not limited to the voltage at which the block A 32 previously accessed the DRAM 31 but may be externally applied to the register. It may be a value that can be set according to 19.
  • the register 19 may be omitted.
  • the arbitration circuit 21 permits access to the DRAM 31 of the block A 32, and when the access is being made, the arbitration circuit 21 gives priority to the access, and the delay adjustment processing is performed. Should not be performed, or delay adjustment processing will be performed after the access of block A32 to DRAM 31 is completed. "
  • counter 20 counts the number of times that block A 32 has priority over access, and the count value reaches a certain number. In this case, the priority of the block A32 is lowered, and the delay adjustment circuit 12 performs the delay adjustment processing.
  • the delay value is adjusted, so that the data of the DRAM 31 is always reliably read. It is possible to do.
  • the power supply voltage monitor of the present embodiment is an example of the voltage monitor of the present invention, and the voltage monitor of the present invention is not limited to the operation of the above embodiment, and may be a predetermined portion of the memory control device ⁇ , or The voltage of the block performing data access may be monitored.
  • FIG. 8 is a configuration diagram of a memory control device according to Embodiment 7 of the present invention.
  • 33 is an error detection block.
  • the description of the enable signal generation circuit 10 is omitted in order to perform the same configuration and operation as in the first embodiment.
  • the counter 20 counts the number of error detections per specific number of codewords to be detected, and when the number of times exceeds a certain number, the delay adjusting circuit 12 adjusts the delay. Perform processing.
  • a fixed number of error detection times may be set in an externally rewritable register 19 or may be stored in the DRAM 31 as a constant in advance. When the data is stored in the DRAM 31, the register 19 may be omitted.
  • the arbitration circuit 21 permits access to the DR A M31 of the block A32, and if access is being made, the arbitration circuit 21 gives priority to the access and does not perform the delay adjustment processing. Or, after the access to the DRAM 31 of the block A 32 is completed, the delay adjustment processing a is performed.
  • the counter 20 counts the number of times that the access of the block A32 is prioritized, and when the count value reaches a certain number, the block counts. Lower the priority of A32 so that the delay adjustment circuit 12 performs delay adjustment processing.
  • the memory control device of the present embodiment it is possible to prevent an increase in the number of error detections due to incorrect reading of the DRAM 31.
  • FIG. 9 is a configuration diagram of a memory control device according to the eighth embodiment of the present invention.
  • the same or corresponding parts as in FIGS. 1 to 4 are denoted by the same reference numerals, and description thereof will be omitted.
  • Reference numeral 34 denotes an error correction block. The description of the enable signal generation circuit 100 is omitted because it performs the same configuration and operation as in the first embodiment. '
  • the error correction block 34 makes an error correction by accessing the DRAM 31, if the error occurs, the data recorded in the DRAM 31 as well as the data that actually contains the error will be confirmed. There is a possibility that they cannot be imported to the Internet.
  • the number of error corrections is counted by the counter 20, and when the number of corrections becomes larger than a certain number, the delay adjusting circuit 12 performs a delay adjusting process.
  • the fixed number of error correction times may be set to the number set in the externally rewritable register 19, or may be stored in the DRAM 31 as a constant in advance.
  • the register 19 may be omitted.
  • the arbitration circuit 21 permits access to the DRAM 31 of the block A 32, and when the access is being performed, the arbitration circuit 21 gives priority to the access, and the delay adjustment processing is performed. Either this is not performed, or delay adjustment processing is performed after access to DRAM 31 of block A 32 is completed. '
  • the counter 20 counts the number of times that the block A32 has been given priority for access, and when the count value reaches a certain number, the priority of the block A32 is lowered, and the delay adjustment circuit 12 performs the delay adjustment processing. Try to do it.
  • the number of times at this time may be retained in the DRAM 31 with the force set in the register 19. '
  • the memory control device of the present embodiment it is possible to prevent an increase in the number of uncorrectable errors due to incorrect reading of the DRAM 31.
  • FIG. 10 is a configuration diagram of a memory control device according to Embodiment 9 of the present invention.
  • the same or corresponding parts as in FIGS. 1 to 4 are denoted by the same reference numerals, and description thereof will be omitted.
  • description of the enable signal generation circuit 100 is omitted because the same configuration and operation as those in the first embodiment are performed.
  • the memory control device performs delay adjustment processing in accordance with the number of times of writing of the block A3'2, and counts the number of times that the block A32 has written to the DR A31 by the counter 20, and When the number of times of writing becomes larger than a certain number, the delay adjusting circuit 12 performs a delay adjusting process. At this time, a fixed number of write times may be set in the externally rewritable register 19, or may be stored in the DRAM 31 as a constant in advance. When the data is stored in the DRAM 31, the register 19 may be omitted.
  • the DRA By adjusting the delay value every time the number of writes to M31 reaches a specific number, it is possible to always read the data of DRAM31 reliably.
  • the memory control device may be realized in one memory control device as shown in FIG. 11, and in this case, the environment surrounding the memory control device, the data access
  • the optimal data capture timing can be obtained according to various conditions, such as the situation and the number of times.
  • the memory of the present invention is a DRAM in each embodiment, but may be an SRAM in other embodiments. In this case, the same effect as described above can be obtained.
  • the present invention provides a memory such as an SDRAM.
  • the operation may be implemented as a memory control device for a memory whose operations are all synchronized with a clock, output data without using an enable signal, and can be determined on a data bus. That is, the present invention is implemented as a memory control device having no enable signal generation unit 100 or means equivalent thereto.
  • the delay value of the delay adjustment circuit 12 is determined by the temperature monitor 17. The voltage may be changed based on the temperature measured by the power supply or the voltage measured by the power supply voltage monitor 18. Further, it may be changed based on a predetermined cycle set by the timer 16 and the counter 20.
  • the memory control device according to the embodiment of the present invention has been described.
  • the present invention relates to all or a part of the memory control device of the present invention described above (or the device). , Elements, circuits, sections, etc.) by a computer. It may be a program that operates in cooperation with a computer.
  • the present invention is a program for causing a computer to execute all or some of the steps (or steps, operations, actions, etc.) of the above-described memory control method of the present invention. May be a program that works
  • the present invention is a medium which carries a program for causing a computer to execute all or a part of the functions of all or part of the memory control device of the present invention described above.
  • the read program may be a medium that executes the function in cooperation with the computer.
  • the present invention is a medium that carries a program for causing a computer to execute all or a part of the operations of all or some of the above-described memory control methods of the present invention.
  • the read program may be a medium that executes the operation in cooperation with the computer.
  • some devices (or elements, circuits, units, and the like) of the present invention mean several devices among a plurality of devices, or one device among one device. It means a unit means (or an element, a circuit, a unit, or the like), or means a part of functions of a group of three means.
  • a computer-readable recording medium that records the program of the present invention is also included in the present invention.
  • One use form of the program of the present invention may be a form in which the program is recorded on a computer-readable recording medium and operates in cooperation with the computer.
  • one usage form of the program of the present invention may be a mode in which the program is transmitted through a transmission medium, read by a computer, and operates in cooperation with a ⁇ computer. .
  • the data structure of the present invention includes a database, a data format, a data table, a data list, a data type, and the like.
  • the recording medium includes ROM and the like
  • the transmission medium includes a transmission medium such as the Internet, light, radio waves, and sound waves.
  • the computer of the present invention described above is not limited to pure hardware such as a CPU, but may include a firmware, an OS, and peripheral devices.
  • the configuration of the present invention may be implemented in a software manner or in hardware.
  • INDUSTRIAL APPLICABILITY As is clear from the above description, according to the present invention, it is possible to adjust the timing at which the read data is captured, and to surely recover the read data even in various situations. Data can be captured.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)

Abstract

L'invention concerne un dispositif de commande de mémoire permettant de commander une DRAM, les données enregistrées dans la DRAM étant saisies de manière certaine dans un registre. Ce dispositif de commande de mémoire comprend un circuit générateur d'horloge de saisie (11) permettant de générer une horloge, un circuit de régulation de retard (12) permettant de réaliser dans l'horloge une régulation du retard à l'aide d'une valeur de retard variable, et de produire l'horloge traitée en tant qu'horloge de saisie, et un registre lecteur de données (13) permettant de lire et de stocker les données enregistrées dans une mémoire sur la base de l'horloge de saisie.
PCT/JP2001/005412 2000-06-27 2001-06-25 Dispositif et procede de commande de memoire WO2002001363A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000193464 2000-06-27
JP2000-193464 2000-06-27

Publications (1)

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WO2002001363A1 true WO2002001363A1 (fr) 2002-01-03

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010038422A1 (fr) * 2008-10-01 2010-04-08 パナソニック株式会社 Interface de mémoire
WO2010137330A1 (fr) * 2009-05-27 2010-12-02 パナソニック株式会社 Dispositif d'ajustement de retard et procédé d'ajustement de retard
CN113825898A (zh) * 2019-05-20 2021-12-21 舍弗勒技术股份两合公司 用于操作机电式凸轮轴相位器的方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0454544A (ja) * 1990-06-21 1992-02-21 Nec Corp メモリアクセス制御装置
JPH05342085A (ja) * 1992-06-09 1993-12-24 Mitsubishi Electric Corp メモリアクセス制御回路
JPH07146814A (ja) * 1993-11-24 1995-06-06 Matsushita Electric Ind Co Ltd メモリ装置
JPH09185427A (ja) * 1995-12-28 1997-07-15 Graphics Commun Lab:Kk クロック位相調整回路およびクロック位相調整方法
JPH10232818A (ja) * 1997-01-23 1998-09-02 Hewlett Packard Co <Hp> メモリ・コントローラ
JPH11161601A (ja) * 1997-08-19 1999-06-18 Matsushita Electric Ind Co Ltd 複数伝送線路間の遅延時間の調整装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0454544A (ja) * 1990-06-21 1992-02-21 Nec Corp メモリアクセス制御装置
JPH05342085A (ja) * 1992-06-09 1993-12-24 Mitsubishi Electric Corp メモリアクセス制御回路
JPH07146814A (ja) * 1993-11-24 1995-06-06 Matsushita Electric Ind Co Ltd メモリ装置
JPH09185427A (ja) * 1995-12-28 1997-07-15 Graphics Commun Lab:Kk クロック位相調整回路およびクロック位相調整方法
JPH10232818A (ja) * 1997-01-23 1998-09-02 Hewlett Packard Co <Hp> メモリ・コントローラ
JPH11161601A (ja) * 1997-08-19 1999-06-18 Matsushita Electric Ind Co Ltd 複数伝送線路間の遅延時間の調整装置

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010038422A1 (fr) * 2008-10-01 2010-04-08 パナソニック株式会社 Interface de mémoire
WO2010137330A1 (fr) * 2009-05-27 2010-12-02 パナソニック株式会社 Dispositif d'ajustement de retard et procédé d'ajustement de retard
US8363492B2 (en) 2009-05-27 2013-01-29 Panasonic Corporation Delay adjustment device and delay adjustment method
CN113825898A (zh) * 2019-05-20 2021-12-21 舍弗勒技术股份两合公司 用于操作机电式凸轮轴相位器的方法
US11680498B2 (en) 2019-05-20 2023-06-20 Schaeffler Technologies AG & Co. KG Method for operating an electromechanical camshaft phaser
CN113825898B (zh) * 2019-05-20 2023-11-24 舍弗勒技术股份两合公司 用于操作机电式凸轮轴相位器的方法

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