DE69615447D1 - Serieller Zugriffspeicher mit reduzierter Kreisverzögerung - Google Patents

Serieller Zugriffspeicher mit reduzierter Kreisverzögerung

Info

Publication number
DE69615447D1
DE69615447D1 DE69615447T DE69615447T DE69615447D1 DE 69615447 D1 DE69615447 D1 DE 69615447D1 DE 69615447 T DE69615447 T DE 69615447T DE 69615447 T DE69615447 T DE 69615447T DE 69615447 D1 DE69615447 D1 DE 69615447D1
Authority
DE
Germany
Prior art keywords
access memory
serial access
reduced circular
circular delay
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69615447T
Other languages
English (en)
Other versions
DE69615447T2 (de
Inventor
Itsuro Iwakiri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Application granted granted Critical
Publication of DE69615447D1 publication Critical patent/DE69615447D1/de
Publication of DE69615447T2 publication Critical patent/DE69615447T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
DE69615447T 1995-05-16 1996-04-29 Serieller Zugriffspeicher mit reduzierter Kreisverzögerung Expired - Fee Related DE69615447T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7117065A JPH08315579A (ja) 1995-05-16 1995-05-16 シリアルアクセスメモリ装置

Publications (2)

Publication Number Publication Date
DE69615447D1 true DE69615447D1 (de) 2001-10-31
DE69615447T2 DE69615447T2 (de) 2002-05-29

Family

ID=14702561

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69615447T Expired - Fee Related DE69615447T2 (de) 1995-05-16 1996-04-29 Serieller Zugriffspeicher mit reduzierter Kreisverzögerung

Country Status (5)

Country Link
US (1) US5801981A (de)
EP (1) EP0743649B1 (de)
JP (1) JPH08315579A (de)
KR (1) KR100362207B1 (de)
DE (1) DE69615447T2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6184928B1 (en) 1997-04-30 2001-02-06 Eastman Kodak Company Method and apparatus for split shift register addressing
US6728799B1 (en) * 2000-01-13 2004-04-27 Hewlett-Packard Development Company, L.P. Hybrid data I/O for memory applications
JP2001222463A (ja) * 2000-02-10 2001-08-17 Hitachi Ltd メモリ装置
JP4026597B2 (ja) * 2004-01-19 2007-12-26 セイコーエプソン株式会社 スキップ機能を有するシフトレジスタ並びにそれを用いた表示ドライバ装置、表示装置及び電子機器
US7974124B2 (en) * 2009-06-24 2011-07-05 Sandisk Corporation Pointer based column selection techniques in non-volatile memories
KR102572678B1 (ko) 2021-12-03 2023-08-30 (주)디엠디센터 엘리베이터카의 핸드레일 장착장치

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5694589A (en) * 1979-12-27 1981-07-31 Nec Corp Memory device
JPS5963869A (ja) * 1982-10-04 1984-04-11 Fuji Xerox Co Ltd 原稿読取装置
EP0363031B1 (de) * 1988-09-20 1994-11-17 Fujitsu Limited Halbleiterspeicher mit Serieneingang/Serienausgang
EP0547830A2 (de) * 1991-12-19 1993-06-23 Texas Instruments Incorporated Schaltungsanordnung und Verfahren zum sequentiellen Zugriff auf eine Speicherarray

Also Published As

Publication number Publication date
EP0743649A3 (de) 1997-11-12
KR100362207B1 (ko) 2003-02-19
KR960042751A (ko) 1996-12-21
DE69615447T2 (de) 2002-05-29
JPH08315579A (ja) 1996-11-29
EP0743649B1 (de) 2001-09-26
US5801981A (en) 1998-09-01
EP0743649A2 (de) 1996-11-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee