DE69837123D1 - Hochgeschwindigkeits-Daten-Ein/Ausgangsgerät zur Übertragung der Daten in den internen Speicher, Behandlungsausführung auf den Daten und Ausgabe der Daten - Google Patents

Hochgeschwindigkeits-Daten-Ein/Ausgangsgerät zur Übertragung der Daten in den internen Speicher, Behandlungsausführung auf den Daten und Ausgabe der Daten

Info

Publication number
DE69837123D1
DE69837123D1 DE69837123T DE69837123T DE69837123D1 DE 69837123 D1 DE69837123 D1 DE 69837123D1 DE 69837123 T DE69837123 T DE 69837123T DE 69837123 T DE69837123 T DE 69837123T DE 69837123 D1 DE69837123 D1 DE 69837123D1
Authority
DE
Germany
Prior art keywords
data
transferring
outputting
processing
output device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69837123T
Other languages
English (en)
Other versions
DE69837123T2 (de
Inventor
Fumio Nakatsuji
Toshinori Maeda
Hiroshi Kamiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE69837123D1 publication Critical patent/DE69837123D1/de
Publication of DE69837123T2 publication Critical patent/DE69837123T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1657—Access to multiple memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10527—Audio or video recording; Data buffering arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)
  • Bus Control (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
DE69837123T 1997-04-02 1998-04-01 Hochgeschwindigkeits-Daten-Ein/Ausgangsgerät zur Übertragung der Daten in den internen Speicher, Behandlungsausführung auf den Daten und Ausgabe der Daten Expired - Lifetime DE69837123T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP8364297 1997-04-02
JP8364297 1997-04-02

Publications (2)

Publication Number Publication Date
DE69837123D1 true DE69837123D1 (de) 2007-04-05
DE69837123T2 DE69837123T2 (de) 2007-11-29

Family

ID=13808114

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69837123T Expired - Lifetime DE69837123T2 (de) 1997-04-02 1998-04-01 Hochgeschwindigkeits-Daten-Ein/Ausgangsgerät zur Übertragung der Daten in den internen Speicher, Behandlungsausführung auf den Daten und Ausgabe der Daten

Country Status (8)

Country Link
US (1) US6041368A (de)
EP (1) EP0874320B1 (de)
JP (1) JP3968167B2 (de)
KR (1) KR100455012B1 (de)
CN (2) CN1154908C (de)
DE (1) DE69837123T2 (de)
HK (1) HK1015479A1 (de)
TW (1) TW432362B (de)

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US6253349B1 (en) * 1997-04-02 2001-06-26 Matsushita Electric Industrial Co., Ltd. Error detective information adding equipment
US6115837A (en) * 1998-07-29 2000-09-05 Neomagic Corp. Dual-column syndrome generation for DVD error correction using an embedded DRAM
US6662334B1 (en) * 1999-02-25 2003-12-09 Adaptec, Inc. Method and device for performing error correction on ECC data sectors
JP2002041445A (ja) 2000-05-19 2002-02-08 Matsushita Electric Ind Co Ltd 高性能ｄｍａコントローラ
TW541519B (en) * 2000-05-24 2003-07-11 Acer Labs Inc Encoding/decoding system in optical disk storage device
KR100403634B1 (ko) * 2001-10-17 2003-10-30 삼성전자주식회사 고속 파이프라인 리드-솔로몬 디코더에 적용하기 위한메모리 장치와 메모리 액세스 방법 및 그 메모리 장치를구비한 리드-솔로몬 디코더
FR2834146A1 (fr) * 2001-12-20 2003-06-27 St Microelectronics Sa Turbo-decodeur compact a haute efficacite
CN1307556C (zh) * 2002-03-18 2007-03-28 松下电器产业株式会社 信息处理装置
JP3743509B2 (ja) * 2002-03-20 2006-02-08 セイコーエプソン株式会社 データ転送制御装置及び電子機器
US6941428B2 (en) * 2002-09-25 2005-09-06 International Business Machines Corporation Memory controller optimization
JP4551635B2 (ja) 2003-07-31 2010-09-29 ソニー株式会社 パイプライン処理システムおよび情報処理装置
US20050038946A1 (en) * 2003-08-12 2005-02-17 Tadpole Computer, Inc. System and method using a high speed interface in a system having co-processors
JP4082300B2 (ja) 2003-08-29 2008-04-30 ソニー株式会社 パイプライン処理システムおよび情報処理装置
CN1300703C (zh) * 2003-11-05 2007-02-14 松下电器产业株式会社 调节电路及其具有它的功能处理电路
US7219258B2 (en) * 2003-12-10 2007-05-15 International Business Machines Corporation Method, system, and product for utilizing a power subsystem to diagnose and recover from errors
JP2006004560A (ja) * 2004-06-18 2006-01-05 Elpida Memory Inc 半導体記憶装置及びその誤り訂正方法
JP2006190346A (ja) * 2004-12-28 2006-07-20 Toshiba Corp エラー訂正処理装置及びエラー訂正処理方法
US7496695B2 (en) * 2005-09-29 2009-02-24 P.A. Semi, Inc. Unified DMA
US20070260963A1 (en) * 2006-04-21 2007-11-08 Kuo-Lung Chien Error correction system and related method thereof
US20070260960A1 (en) * 2006-04-21 2007-11-08 Kuo-Lung Chien Error correction system and related method thereof
US20070260961A1 (en) * 2006-04-21 2007-11-08 Kuo-Lung Chien Error correction system and related method thereof
GB0622408D0 (en) * 2006-11-10 2006-12-20 Ibm Device and method for detection and processing of stalled data request
JP2011130008A (ja) * 2009-12-15 2011-06-30 Hitachi-Lg Data Storage Inc データ入出力装置
US8612834B2 (en) * 2011-03-08 2013-12-17 Intel Corporation Apparatus, system, and method for decoding linear block codes in a memory controller
JP2014071834A (ja) * 2012-10-01 2014-04-21 Toshiba Corp 通信装置およびプログラム
US9299387B2 (en) * 2014-07-25 2016-03-29 Kabushiki Kaisha Toshiba Magnetic disk apparatus, controller and data processing method
US9800271B2 (en) * 2015-09-14 2017-10-24 Qualcomm Incorporated Error correction and decoding
KR102504176B1 (ko) * 2016-06-23 2023-03-02 에스케이하이닉스 주식회사 반도체장치

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JPS60254463A (ja) * 1984-05-31 1985-12-16 Sony Corp デジタルデ−タの記録ないし再生方式
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JP2703417B2 (ja) * 1991-04-05 1998-01-26 富士通株式会社 受信バッファ
US5530901A (en) * 1991-11-28 1996-06-25 Ricoh Company, Ltd. Data Transmission processing system having DMA channels running cyclically to execute data transmission from host to memory and from memory to processing unit successively
EP0582370B1 (de) * 1992-06-05 1998-10-07 Compaq Computer Corporation Plattenantriebsteuergerät mit Nachschreibcachespeicher
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Also Published As

Publication number Publication date
CN1154908C (zh) 2004-06-23
CN1501248B (zh) 2010-05-26
DE69837123T2 (de) 2007-11-29
KR100455012B1 (ko) 2004-12-17
EP0874320A3 (de) 2001-01-17
CN1501248A (zh) 2004-06-02
EP0874320B1 (de) 2007-02-21
EP0874320A2 (de) 1998-10-28
CN1202646A (zh) 1998-12-23
JPH10334040A (ja) 1998-12-18
KR19980081024A (ko) 1998-11-25
US6041368A (en) 2000-03-21
JP3968167B2 (ja) 2007-08-29
HK1015479A1 (en) 1999-10-15
TW432362B (en) 2001-05-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP