DE69835505T2 - Verfahren zur bereitstellung eines getters bei der herstellung von integrierten silizium-auf-isolator-schaltungen - Google Patents

Verfahren zur bereitstellung eines getters bei der herstellung von integrierten silizium-auf-isolator-schaltungen Download PDF

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Publication number
DE69835505T2
DE69835505T2 DE69835505T DE69835505T DE69835505T2 DE 69835505 T2 DE69835505 T2 DE 69835505T2 DE 69835505 T DE69835505 T DE 69835505T DE 69835505 T DE69835505 T DE 69835505T DE 69835505 T2 DE69835505 T2 DE 69835505T2
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DE
Germany
Prior art keywords
silicon
gettering
regions
providing
soi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69835505T
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German (de)
English (en)
Other versions
DE69835505D1 (de
Inventor
J. Theodore LETAVIC
P. Rene ZINGG
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Application granted granted Critical
Publication of DE69835505D1 publication Critical patent/DE69835505D1/de
Publication of DE69835505T2 publication Critical patent/DE69835505T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Dicing (AREA)
DE69835505T 1997-12-23 1998-10-05 Verfahren zur bereitstellung eines getters bei der herstellung von integrierten silizium-auf-isolator-schaltungen Expired - Lifetime DE69835505T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US996672 1997-12-23
US08/996,672 US6093624A (en) 1997-12-23 1997-12-23 Method of providing a gettering scheme in the manufacture of silicon-on-insulator (SOI) integrated circuits
PCT/IB1998/001532 WO1999034432A1 (en) 1997-12-23 1998-10-05 Method of providing a gettering scheme in the manufacture of silicon-on-insulator (soi) integrated circuits

Publications (2)

Publication Number Publication Date
DE69835505D1 DE69835505D1 (de) 2006-09-21
DE69835505T2 true DE69835505T2 (de) 2007-04-05

Family

ID=25543175

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69835505T Expired - Lifetime DE69835505T2 (de) 1997-12-23 1998-10-05 Verfahren zur bereitstellung eines getters bei der herstellung von integrierten silizium-auf-isolator-schaltungen

Country Status (6)

Country Link
US (1) US6093624A (enExample)
EP (1) EP0965141B1 (enExample)
JP (1) JP4372847B2 (enExample)
KR (1) KR100541539B1 (enExample)
DE (1) DE69835505T2 (enExample)
WO (1) WO1999034432A1 (enExample)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4573953B2 (ja) * 2000-06-27 2010-11-04 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6498061B2 (en) * 2000-12-06 2002-12-24 International Business Machines Corporation Negative ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formation
US6383924B1 (en) * 2000-12-13 2002-05-07 Micron Technology, Inc. Method of forming buried conductor patterns by surface transformation of empty spaces in solid state materials
US6444534B1 (en) 2001-01-30 2002-09-03 Advanced Micro Devices, Inc. SOI semiconductor device opening implantation gettering method
US6376336B1 (en) 2001-02-01 2002-04-23 Advanced Micro Devices, Inc. Frontside SOI gettering with phosphorus doping
US6670259B1 (en) 2001-02-21 2003-12-30 Advanced Micro Devices, Inc. Inert atom implantation method for SOI gettering
US7142577B2 (en) * 2001-05-16 2006-11-28 Micron Technology, Inc. Method of forming mirrors by surface transformation of empty spaces in solid state materials and structures thereon
US6898362B2 (en) * 2002-01-17 2005-05-24 Micron Technology Inc. Three-dimensional photonic crystal waveguide structure and method
US6987037B2 (en) * 2003-05-07 2006-01-17 Micron Technology, Inc. Strained Si/SiGe structures by ion implantation
US7273788B2 (en) * 2003-05-21 2007-09-25 Micron Technology, Inc. Ultra-thin semiconductors bonded on glass substrates
US7501329B2 (en) * 2003-05-21 2009-03-10 Micron Technology, Inc. Wafer gettering using relaxed silicon germanium epitaxial proximity layers
US7662701B2 (en) 2003-05-21 2010-02-16 Micron Technology, Inc. Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers
US7008854B2 (en) 2003-05-21 2006-03-07 Micron Technology, Inc. Silicon oxycarbide substrates for bonded silicon on insulator
US6929984B2 (en) * 2003-07-21 2005-08-16 Micron Technology Inc. Gettering using voids formed by surface transformation
US7153753B2 (en) * 2003-08-05 2006-12-26 Micron Technology, Inc. Strained Si/SiGe/SOI islands and processes of making same
US20050255677A1 (en) * 2004-05-17 2005-11-17 Weigold Jason W Integrated circuit with impurity barrier
US20060115958A1 (en) * 2004-11-22 2006-06-01 Weigold Jason W Method and apparatus for forming buried oxygen precipitate layers in multi-layer wafers
JP2006196514A (ja) * 2005-01-11 2006-07-27 Nec Electronics Corp 半導体装置及びその製造方法
TWI355046B (en) * 2007-07-10 2011-12-21 Nanya Technology Corp Two bit memory structure and method of making the
US7928690B2 (en) * 2007-11-29 2011-04-19 GM Global Technology Operations LLC Method and system for determining a state of charge of a battery
JP5470766B2 (ja) * 2008-07-18 2014-04-16 株式会社Ｓｕｍｃｏ 半導体デバイスの製造方法
US9231020B2 (en) 2014-01-16 2016-01-05 Tower Semiconductor Ltd. Device and method of gettering on silicon on insulator (SOI) substrate
KR102399356B1 (ko) 2017-03-10 2022-05-19 삼성전자주식회사 기판, 기판의 쏘잉 방법, 및 반도체 소자

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56103447A (en) * 1980-01-22 1981-08-18 Toshiba Corp Dicing method of semiconductor wafer
US5096855A (en) * 1988-05-23 1992-03-17 U.S. Philips Corporation Method of dicing semiconductor wafers which produces shards less than 10 microns in size
JPH04266047A (ja) * 1991-02-20 1992-09-22 Fujitsu Ltd 埋め込み層形成に相当するｓｏｉ型半導体装置の製造方法及び半導体装置
US5244819A (en) * 1991-10-22 1993-09-14 Honeywell Inc. Method to getter contamination in semiconductor devices
US5556793A (en) * 1992-02-28 1996-09-17 Motorola, Inc. Method of making a structure for top surface gettering of metallic impurities
DE4317721C1 (de) * 1993-05-27 1994-07-21 Siemens Ag Verfahren zur Vereinzelung von Chips aus einem Wafer
TW274628B (enExample) * 1994-06-03 1996-04-21 At & T Corp
US5429981A (en) * 1994-06-30 1995-07-04 Honeywell Inc. Method of making linear capacitors for high temperature applications
KR0172548B1 (ko) * 1995-06-30 1999-02-01 김주용 반도체 소자 및 그 제조방법
US5646053A (en) * 1995-12-20 1997-07-08 International Business Machines Corporation Method and structure for front-side gettering of silicon-on-insulator substrates
US5622899A (en) * 1996-04-22 1997-04-22 Taiwan Semiconductor Manufacturing Company Ltd. Method of fabricating semiconductor chips separated by scribe lines used for endpoint detection

Also Published As

Publication number Publication date
KR20000076026A (ko) 2000-12-26
DE69835505D1 (de) 2006-09-21
JP2001513948A (ja) 2001-09-04
EP0965141B1 (en) 2006-08-09
US6093624A (en) 2000-07-25
KR100541539B1 (ko) 2006-01-12
JP4372847B2 (ja) 2009-11-25
WO1999034432A1 (en) 1999-07-08
EP0965141A1 (en) 1999-12-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN

8327 Change in the person/name/address of the patent owner

Owner name: NXP B.V., EINDHOVEN, NL