DE69831734D1 - Herstellungsverfahren eines diffundierten emitter bipolar transistors - Google Patents

Herstellungsverfahren eines diffundierten emitter bipolar transistors

Info

Publication number
DE69831734D1
DE69831734D1 DE69831734T DE69831734T DE69831734D1 DE 69831734 D1 DE69831734 D1 DE 69831734D1 DE 69831734 T DE69831734 T DE 69831734T DE 69831734 T DE69831734 T DE 69831734T DE 69831734 D1 DE69831734 D1 DE 69831734D1
Authority
DE
Germany
Prior art keywords
manufacturing
bipolar transistor
different emitted
emitted
different
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69831734T
Other languages
English (en)
Other versions
DE69831734T2 (de
Inventor
A Randazzo
J Seliskar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LSI Corp
Original Assignee
LSI Logic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LSI Logic Corp filed Critical LSI Logic Corp
Application granted granted Critical
Publication of DE69831734D1 publication Critical patent/DE69831734D1/de
Publication of DE69831734T2 publication Critical patent/DE69831734T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/009—Bi-MOS
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/944—Shadow

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE69831734T 1997-04-03 1998-04-02 Herstellungsverfahren eines diffundierten emitter bipolar transistors Expired - Lifetime DE69831734T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/832,245 US5780329A (en) 1997-04-03 1997-04-03 Process for fabricating a moderate-depth diffused emitter bipolar transistor in a BICMOS device without using an additional mask
US832245 1997-04-03
PCT/US1998/006540 WO1998044553A1 (en) 1997-04-03 1998-04-02 Process for fabricating a diffused emitter bipolar transistor

Publications (2)

Publication Number Publication Date
DE69831734D1 true DE69831734D1 (de) 2005-11-03
DE69831734T2 DE69831734T2 (de) 2006-06-22

Family

ID=25261096

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69831734T Expired - Lifetime DE69831734T2 (de) 1997-04-03 1998-04-02 Herstellungsverfahren eines diffundierten emitter bipolar transistors

Country Status (7)

Country Link
US (1) US5780329A (de)
EP (1) EP0972305B1 (de)
JP (1) JP4386468B2 (de)
AU (1) AU7245298A (de)
DE (1) DE69831734T2 (de)
TW (1) TW398080B (de)
WO (1) WO1998044553A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10289961A (ja) * 1997-04-15 1998-10-27 Nec Corp 半導体装置の製造方法
US6001701A (en) * 1997-06-09 1999-12-14 Lucent Technologies Inc. Process for making bipolar having graded or modulated collector
JPH11204540A (ja) * 1998-01-16 1999-07-30 Mitsubishi Electric Corp 半導体装置の製造方法
JPH11307544A (ja) * 1998-02-20 1999-11-05 Seiko Instruments Inc バイポーラトランジスタ及び半導体集積回路装置
US6174760B1 (en) * 1999-05-19 2001-01-16 United Microelectronics Corp. Method of improving vertical BJT gain
US6117718A (en) * 1999-08-31 2000-09-12 United Microelectronics Corp. Method for forming BJT via formulation of high voltage device in ULSI
JP2002026134A (ja) * 2000-07-12 2002-01-25 Seiko Epson Corp 半導体集積回路の製造方法及びこの方法により製造した半導体集積回路
US8901823B2 (en) 2008-10-24 2014-12-02 Ilumisys, Inc. Light and light sensor

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3879186D1 (de) * 1988-04-19 1993-04-15 Ibm Verfahren zur herstellung von integrierten halbleiterstrukturen welche feldeffekttransistoren mit kanallaengen im submikrometerbereich enthalten.
JPH0247874A (ja) * 1988-08-10 1990-02-16 Fuji Electric Co Ltd Ｍｏｓ型半導体装置の製造方法
JPH0362568A (ja) * 1989-07-31 1991-03-18 Hitachi Ltd 半導体装置の製造方法
FR2663156A1 (fr) * 1990-06-11 1991-12-13 Sgs Thomson Microelectronics Transistor bipolaire supportant des polarisations inverses et procede de fabrication.
US5091290A (en) * 1990-12-03 1992-02-25 Micron Technology, Inc. Process for promoting adhesion of a layer of photoresist on a substrate having a previous layer of photoresist
US5286607A (en) * 1991-12-09 1994-02-15 Chartered Semiconductor Manufacturing Pte Ltd. Bi-layer resist process for semiconductor processing
EP0565231A3 (en) * 1992-03-31 1996-11-20 Sgs Thomson Microelectronics Method of fabricating a polysilicon thin film transistor
US5342794A (en) * 1992-09-10 1994-08-30 Vlsi Technology, Inc. Method for forming laterally graded deposit-type emitter for bipolar transistor
US5348897A (en) * 1992-12-01 1994-09-20 Paradigm Technology, Inc. Transistor fabrication methods using overlapping masks
US5288652A (en) * 1992-12-18 1994-02-22 Vlsi Technology, Inc. BICMOS-compatible method for creating a bipolar transistor with laterally graded emitter structure
US5444003A (en) * 1993-06-23 1995-08-22 Vlsi Technology, Inc. Method and structure for creating a self-aligned bicmos-compatible bipolar transistor with a laterally graded emitter structure
US5510287A (en) * 1994-11-01 1996-04-23 Taiwan Semiconductor Manuf. Company Method of making vertical channel mask ROM

Also Published As

Publication number Publication date
JP2002514351A (ja) 2002-05-14
WO1998044553A1 (en) 1998-10-08
AU7245298A (en) 1998-10-22
DE69831734T2 (de) 2006-06-22
US5780329A (en) 1998-07-14
TW398080B (en) 2000-07-11
JP4386468B2 (ja) 2009-12-16
EP0972305A1 (de) 2000-01-19
EP0972305B1 (de) 2005-09-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition