DE69815308D1 - Dram mit integralem sram sowie systeme und verfahren zu deren benutzung - Google Patents

Dram mit integralem sram sowie systeme und verfahren zu deren benutzung

Info

Publication number
DE69815308D1
DE69815308D1 DE69815308T DE69815308T DE69815308D1 DE 69815308 D1 DE69815308 D1 DE 69815308D1 DE 69815308 T DE69815308 T DE 69815308T DE 69815308 T DE69815308 T DE 69815308T DE 69815308 D1 DE69815308 D1 DE 69815308D1
Authority
DE
Germany
Prior art keywords
address bits
circuitry
accessing
array
cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69815308T
Other languages
English (en)
Inventor
R Rao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Silicon Aquarius Inc
Original Assignee
Silicon Aquarius Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=25221300&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69815308(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Silicon Aquarius Inc filed Critical Silicon Aquarius Inc
Application granted granted Critical
Publication of DE69815308D1 publication Critical patent/DE69815308D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Apparatus For Radiation Diagnosis (AREA)
  • Control Of Electric Motors In General (AREA)
  • Detergent Compositions (AREA)
DE69815308T 1997-03-13 1998-03-13 Dram mit integralem sram sowie systeme und verfahren zu deren benutzung Expired - Lifetime DE69815308D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/816,663 US5835932A (en) 1997-03-13 1997-03-13 Methods and systems for maintaining data locality in a multiple memory bank system having DRAM with integral SRAM
PCT/US1998/005048 WO1998040891A1 (en) 1997-03-13 1998-03-13 Dram with integral sram and systems and methods using the same

Publications (1)

Publication Number Publication Date
DE69815308D1 true DE69815308D1 (de) 2003-07-10

Family

ID=25221300

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69815308T Expired - Lifetime DE69815308D1 (de) 1997-03-13 1998-03-13 Dram mit integralem sram sowie systeme und verfahren zu deren benutzung

Country Status (8)

Country Link
US (2) US5835932A (de)
EP (1) EP0966741B1 (de)
JP (1) JP2001525086A (de)
KR (1) KR20000076226A (de)
AT (1) ATE242536T1 (de)
DE (1) DE69815308D1 (de)
TW (1) TW389903B (de)
WO (1) WO1998040891A1 (de)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6388314B1 (en) 1995-08-17 2002-05-14 Micron Technology, Inc. Single deposition layer metal dynamic random access memory
US5838631A (en) 1996-04-19 1998-11-17 Integrated Device Technology, Inc. Fully synchronous pipelined ram
US5835932A (en) * 1997-03-13 1998-11-10 Silicon Aquarius, Inc. Methods and systems for maintaining data locality in a multiple memory bank system having DRAM with integral SRAM
US5903491A (en) 1997-06-09 1999-05-11 Micron Technology, Inc. Single deposition layer metal dynamic random access memory
US6263448B1 (en) * 1997-10-10 2001-07-17 Rambus Inc. Power control system for synchronous memory device
US6173356B1 (en) * 1998-02-20 2001-01-09 Silicon Aquarius, Inc. Multi-port DRAM with integrated SRAM and systems and methods using the same
US6115320A (en) 1998-02-23 2000-09-05 Integrated Device Technology, Inc. Separate byte control on fully synchronous pipelined SRAM
US6272594B1 (en) * 1998-07-31 2001-08-07 Hewlett-Packard Company Method and apparatus for determining interleaving schemes in a computer system that supports multiple interleaving schemes
US6237130B1 (en) * 1998-10-29 2001-05-22 Nexabit Networks, Inc. Chip layout for implementing arbitrated high speed switching access of pluralities of I/O data ports to internally cached DRAM banks and the like
US6467018B1 (en) * 1999-01-04 2002-10-15 International Business Machines Corporation Method and apparatus for addressing individual banks of DRAMs on a memory card
JP2000268559A (ja) * 1999-03-12 2000-09-29 Nec Corp 半導体集積回路装置
JP2000339954A (ja) 1999-05-31 2000-12-08 Fujitsu Ltd 半導体記憶装置
US7069406B2 (en) * 1999-07-02 2006-06-27 Integrated Device Technology, Inc. Double data rate synchronous SRAM with 100% bus utilization
US6272070B1 (en) * 2000-02-09 2001-08-07 Micron Technology, Inc. Method and apparatus for setting write latency
JP2001243211A (ja) * 2000-02-29 2001-09-07 Mitsubishi Electric Corp マイクロコンピュータ
US6766431B1 (en) * 2000-06-16 2004-07-20 Freescale Semiconductor, Inc. Data processing system and method for a sector cache
US6658523B2 (en) * 2001-03-13 2003-12-02 Micron Technology, Inc. System latency levelization for read data
US7085186B2 (en) * 2001-04-05 2006-08-01 Purple Mountain Server Llc Method for hiding a refresh in a pseudo-static memory
JP4731730B2 (ja) * 2001-06-04 2011-07-27 ルネサスエレクトロニクス株式会社 半導体記憶装置
JP3851865B2 (ja) * 2001-12-19 2006-11-29 株式会社東芝 半導体集積回路
US6728159B2 (en) * 2001-12-21 2004-04-27 International Business Machines Corporation Flexible multibanking interface for embedded memory applications
US6751113B2 (en) * 2002-03-07 2004-06-15 Netlist, Inc. Arrangement of integrated circuits in a memory module
US7139213B2 (en) 2003-06-02 2006-11-21 Silicon Aquarius, Inc. Multiple data path memories and systems
US7254690B2 (en) * 2003-06-02 2007-08-07 S. Aqua Semiconductor Llc Pipelined semiconductor memories and systems
US7707330B2 (en) * 2003-09-18 2010-04-27 Rao G R Mohan Memories for electronic systems
US20050018495A1 (en) * 2004-01-29 2005-01-27 Netlist, Inc. Arrangement of integrated circuits in a memory module
KR100632946B1 (ko) * 2004-07-13 2006-10-12 삼성전자주식회사 불 휘발성 메모리 장치 및 그것의 프로그램 방법
US7755961B2 (en) * 2006-07-07 2010-07-13 Rao G R Mohan Memories with selective precharge
US7724593B2 (en) * 2006-07-07 2010-05-25 Rao G R Mohan Memories with front end precharge
US7995409B2 (en) * 2007-10-16 2011-08-09 S. Aqua Semiconductor, Llc Memory with independent access and precharge
US8095853B2 (en) 2007-10-19 2012-01-10 S. Aqua Semiconductor Llc Digital memory with fine grain write operation
US8521951B2 (en) * 2008-01-16 2013-08-27 S. Aqua Semiconductor Llc Content addressable memory augmented memory
US20090182977A1 (en) * 2008-01-16 2009-07-16 S. Aqua Semiconductor Llc Cascaded memory arrangement
US8050080B2 (en) * 2008-03-05 2011-11-01 S. Aqua Semiconductor Llc Random access memory with CMOS-compatible nonvolatile storage element in series with storage capacitor
US8000140B2 (en) * 2008-03-24 2011-08-16 S. Aqua Semiconductor, Llc Random access memory with CMOS-compatible nonvolatile storage element
US7885110B2 (en) * 2008-03-25 2011-02-08 Rao G R Mohan Random access memory with CMOS-compatible nonvolatile storage element and parallel storage capacitor
US7916572B1 (en) 2008-07-28 2011-03-29 Altera Corporation Memory with addressable subword support
JP5165630B2 (ja) * 2009-04-09 2013-03-21 京セラコネクタプロダクツ株式会社 コネクタ
WO2014011149A1 (en) * 2012-07-10 2014-01-16 Hewlett-Packard Development Company, L.P. List sort static random access memory
US10020036B2 (en) * 2012-12-12 2018-07-10 Nvidia Corporation Address bit remapping scheme to reduce access granularity of DRAM accesses
US9824024B1 (en) * 2014-10-31 2017-11-21 Altera Corporation Configurable storage blocks with embedded first-in first-out and delay line circuitry

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943786B2 (ja) * 1979-03-30 1984-10-24 パナフアコム株式会社 記憶装置のアクセス方式
US4292674A (en) * 1979-07-27 1981-09-29 Sperry Corporation One word buffer memory system
US4758993A (en) * 1984-11-19 1988-07-19 Fujitsu Limited Random access memory device formed on a semiconductor substrate having an array of memory cells divided into sub-arrays
US4894770A (en) * 1987-06-01 1990-01-16 Massachusetts Institute Of Technology Set associative memory
US5226147A (en) * 1987-11-06 1993-07-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device for simple cache system
JP2777247B2 (ja) * 1990-01-16 1998-07-16 三菱電機株式会社 半導体記憶装置およびキャッシュシステム
JP2938511B2 (ja) * 1990-03-30 1999-08-23 三菱電機株式会社 半導体記憶装置
JP2862948B2 (ja) * 1990-04-13 1999-03-03 三菱電機株式会社 半導体記憶装置
US5269010A (en) * 1990-08-31 1993-12-07 Advanced Micro Devices, Inc. Memory control for use in a memory system incorporating a plurality of memory banks
EP0811979B1 (de) * 1990-12-25 2004-02-11 Mitsubishi Denki Kabushiki Kaisha Halbleiterspeichervorrichtung
JPH04307495A (ja) * 1991-04-04 1992-10-29 Mitsubishi Electric Corp 半導体記憶装置
US5680570A (en) * 1991-06-12 1997-10-21 Quantum Corporation Memory system with dynamically allocatable non-volatile storage capability
EP0895162A3 (de) * 1992-01-22 1999-11-10 Enhanced Memory Systems, Inc. Verbesserte DRAM mit eingebauten Registern
JP3304413B2 (ja) * 1992-09-17 2002-07-22 三菱電機株式会社 半導体記憶装置
JP3305056B2 (ja) * 1993-08-31 2002-07-22 沖電気工業株式会社 ダイナミックｒａｍ
US5761694A (en) * 1995-11-30 1998-06-02 Cirrus Logic, Inc. Multi-bank memory system and method having addresses switched between the row and column decoders in different banks
US5787457A (en) * 1996-10-18 1998-07-28 International Business Machines Corporation Cached synchronous DRAM architecture allowing concurrent DRAM operations
US5835932A (en) * 1997-03-13 1998-11-10 Silicon Aquarius, Inc. Methods and systems for maintaining data locality in a multiple memory bank system having DRAM with integral SRAM

Also Published As

Publication number Publication date
JP2001525086A (ja) 2001-12-04
KR20000076226A (ko) 2000-12-26
EP0966741B1 (de) 2003-06-04
WO1998040891A1 (en) 1998-09-17
TW389903B (en) 2000-05-11
US5890195A (en) 1999-03-30
US5835932A (en) 1998-11-10
ATE242536T1 (de) 2003-06-15
EP0966741A1 (de) 1999-12-29

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