DE69726233D1 - Taktschema - Google Patents

Taktschema

Info

Publication number
DE69726233D1
DE69726233D1 DE69726233T DE69726233T DE69726233D1 DE 69726233 D1 DE69726233 D1 DE 69726233D1 DE 69726233 T DE69726233 T DE 69726233T DE 69726233 T DE69726233 T DE 69726233T DE 69726233 D1 DE69726233 D1 DE 69726233D1
Authority
DE
Germany
Prior art keywords
clocking scheme
clocking
scheme
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69726233T
Other languages
English (en)
Other versions
DE69726233T2 (de
Inventor
Robert J Proebsting
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of DE69726233D1 publication Critical patent/DE69726233D1/de
Application granted granted Critical
Publication of DE69726233T2 publication Critical patent/DE69726233T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006—Changing the frequency

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Logic Circuits (AREA)
DE69726233T 1996-09-12 1997-09-06 Taktschema Expired - Lifetime DE69726233T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US2598496P 1996-09-12 1996-09-12
US25984P 1996-09-12
US08/901,594 US5939919A (en) 1996-09-12 1997-07-28 Clock signal distribution method for reducing active power dissipation
US901594 2001-07-11

Publications (2)

Publication Number Publication Date
DE69726233D1 true DE69726233D1 (de) 2003-12-24
DE69726233T2 DE69726233T2 (de) 2004-08-05

Family

ID=26700562

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69726233T Expired - Lifetime DE69726233T2 (de) 1996-09-12 1997-09-06 Taktschema

Country Status (6)

Country Link
US (1) US5939919A (de)
EP (1) EP0829963B1 (de)
JP (1) JP3962455B2 (de)
KR (1) KR100487099B1 (de)
DE (1) DE69726233T2 (de)
TW (1) TW359823B (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6965974B1 (en) * 1997-11-14 2005-11-15 Agere Systems Inc. Dynamic partitioning of memory banks among multiple agents
JP3415444B2 (ja) 1998-06-12 2003-06-09 Ｎｅｃエレクトロニクス株式会社 クロック制御方法および回路
US6333659B1 (en) * 1998-06-01 2001-12-25 Nec Corporation Clock control method and circuit
US6504414B2 (en) 1998-06-12 2003-01-07 Nec Corporation Clock control method and circuit
JP3087734B2 (ja) * 1998-10-09 2000-09-11 日本電気株式会社 クロック信号生成回路
JP2001338985A (ja) * 1999-09-20 2001-12-07 Matsushita Electric Ind Co Ltd クロック回路及びその設計方法
US6975154B1 (en) * 2003-04-29 2005-12-13 Altera Corporation Reduced power consumption clock network
JP2005148972A (ja) * 2003-11-13 2005-06-09 Kawasaki Microelectronics Kk クロック信号生成回路
US7528638B2 (en) * 2003-12-22 2009-05-05 Micron Technology, Inc. Clock signal distribution with reduced parasitic loading effects
US20090015066A1 (en) * 2007-07-10 2009-01-15 Yazaki North America, Inc. Close-loop relay driver with equal-phase interval
KR101636497B1 (ko) * 2009-07-10 2016-07-05 에스케이하이닉스 주식회사 클럭 전달회로 및 반도체 장치

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5941338B2 (ja) * 1976-05-10 1984-10-06 日本電気株式会社 クロツクパルス再生回路
CA1129036A (en) * 1978-05-30 1982-08-03 Colin R. Betts Digital data transmission
US4476401A (en) * 1983-01-31 1984-10-09 Motorola, Inc. Write strobe generator for clock synchronized memory
US4583008A (en) * 1983-02-25 1986-04-15 Harris Corporation Retriggerable edge detector for edge-actuated internally clocked parts
US4807266A (en) * 1987-09-28 1989-02-21 Compaq Computer Corporation Circuit and method for performing equal duty cycle odd value clock division and clock synchronization
JP2629028B2 (ja) * 1988-08-10 1997-07-09 株式会社日立製作所 クロック信号供給方法および装置
JPH02194721A (ja) * 1989-01-24 1990-08-01 Hitachi Ltd 半導体集積回路装置
DE4020719A1 (de) * 1990-06-29 1992-01-02 Broadcast Television Syst Verfahren zur uebertragung eines digitalen datensignals
US5125009A (en) * 1990-07-13 1992-06-23 Hewlett-Packard Co. Method and apparatus for synchronously distribution digital signals in high speed systems
US5481573A (en) * 1992-06-26 1996-01-02 International Business Machines Corporation Synchronous clock distribution system
US5249214A (en) * 1992-06-30 1993-09-28 Vlsi Technology, Inc. Low skew CMOS clock divider
KR200148592Y1 (ko) * 1993-03-19 1999-06-15 구본준 모드변환 리셋회로
US5570054A (en) * 1994-09-26 1996-10-29 Hitachi Micro Systems, Inc. Method and apparatus for adaptive clock deskewing
US5713005A (en) * 1995-02-10 1998-01-27 Townsend And Townsend And Crew Llp Method and apparatus for pipelining data in an integrated circuit
JPH09312635A (ja) * 1996-05-21 1997-12-02 Nec Yonezawa Ltd クロック信号伝送装置

Also Published As

Publication number Publication date
EP0829963B1 (de) 2003-11-19
EP0829963A3 (de) 1999-01-20
DE69726233T2 (de) 2004-08-05
TW359823B (en) 1999-06-01
JPH10214131A (ja) 1998-08-11
KR100487099B1 (ko) 2005-08-01
EP0829963A2 (de) 1998-03-18
JP3962455B2 (ja) 2007-08-22
KR19980024393A (ko) 1998-07-06
US5939919A (en) 1999-08-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: MAGNACHIP SEMICONDUCTOR, LTD., CHEONGJU, KR

8327 Change in the person/name/address of the patent owner

Owner name: HYNIX SEMICONDUCTOR INC., ICHON, KYONGGI, KR