DE69717054D1 - Verbesserungen an oder bezüglich integrierten Schaltungen - Google Patents

Verbesserungen an oder bezüglich integrierten Schaltungen

Info

Publication number
DE69717054D1
DE69717054D1 DE69717054T DE69717054T DE69717054D1 DE 69717054 D1 DE69717054 D1 DE 69717054D1 DE 69717054 T DE69717054 T DE 69717054T DE 69717054 T DE69717054 T DE 69717054T DE 69717054 D1 DE69717054 D1 DE 69717054D1
Authority
DE
Germany
Prior art keywords
integrated circuits
regarding integrated
regarding
circuits
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69717054T
Other languages
English (en)
Other versions
DE69717054T2 (de
Inventor
David R Brown
Shoji Wada
Kazuya Ito
Yasuhito Ichimura
Ken Saitoh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Texas Instruments Inc
Original Assignee
Hitachi Ltd
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Texas Instruments Inc filed Critical Hitachi Ltd
Application granted granted Critical
Publication of DE69717054D1 publication Critical patent/DE69717054D1/de
Publication of DE69717054T2 publication Critical patent/DE69717054T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
DE69717054T 1996-12-03 1997-12-03 Verbesserungen an oder bezüglich integrierten Schaltungen Expired - Lifetime DE69717054T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US3233096P 1996-12-03 1996-12-03

Publications (2)

Publication Number Publication Date
DE69717054D1 true DE69717054D1 (de) 2002-12-19
DE69717054T2 DE69717054T2 (de) 2003-11-13

Family

ID=21864364

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69717054T Expired - Lifetime DE69717054T2 (de) 1996-12-03 1997-12-03 Verbesserungen an oder bezüglich integrierten Schaltungen

Country Status (5)

Country Link
US (1) US5831925A (de)
EP (1) EP0847058B1 (de)
JP (1) JPH10240617A (de)
KR (1) KR100499295B1 (de)
DE (1) DE69717054T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6226723B1 (en) * 1996-09-20 2001-05-01 Advanced Memory International, Inc. Bifurcated data and command/address communication bus architecture for random access memories employing synchronous communication protocols
US6088774A (en) 1996-09-20 2000-07-11 Advanced Memory International, Inc. Read/write timing for maximum utilization of bidirectional read/write bus
US6111757A (en) * 1998-01-16 2000-08-29 International Business Machines Corp. SIMM/DIMM memory module
US6175951B1 (en) * 1998-03-25 2001-01-16 Winbond Electronics Corp. Method for fabricating a customer-configured integrated circuit and customer-configured integrated circuit for exclusive use by a customer background of the invention
US6404660B1 (en) * 1999-12-23 2002-06-11 Rambus, Inc. Semiconductor package with a controlled impedance bus and method of forming same
US7610447B2 (en) * 2001-02-28 2009-10-27 Rambus Inc. Upgradable memory system with reconfigurable interconnect
US6889304B2 (en) * 2001-02-28 2005-05-03 Rambus Inc. Memory device supporting a dynamically configurable core organization
KR100390238B1 (ko) * 2001-05-18 2003-07-07 주식회사 하이닉스반도체 뱅크 어드레스를 이용한 반도체 메모리 소자의 어드레스제어 장치
US7131033B1 (en) 2002-06-21 2006-10-31 Cypress Semiconductor Corp. Substrate configurable JTAG ID scheme
US6982892B2 (en) 2003-05-08 2006-01-03 Micron Technology, Inc. Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules
US7818640B1 (en) 2004-10-22 2010-10-19 Cypress Semiconductor Corporation Test system having a master/slave JTAG controller
US7466620B2 (en) * 2006-01-04 2008-12-16 Baker Mohammad System and method for low power wordline logic for a memory
WO2020098549A1 (en) * 2018-11-14 2020-05-22 Changxin Memory Technologies, Inc. Word line control method, word line control circuit device and semiconductor memory

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55150179A (en) * 1979-05-04 1980-11-21 Fujitsu Ltd Semiconductor memory unit
JPS6116095A (ja) * 1984-06-30 1986-01-24 Toshiba Corp 半導体集積回路装置
JPS6254949A (ja) * 1985-09-04 1987-03-10 Toshiba Corp 半導体集積回路
US5161124A (en) * 1988-10-27 1992-11-03 Texas Instruments Incorporated Bond programmable integrated circuit
EP0476282A3 (en) * 1990-07-31 1992-06-24 Texas Instruments Incorporated Improvements in or relating to integrated circuits
JP3476231B2 (ja) * 1993-01-29 2003-12-10 三菱電機エンジニアリング株式会社 同期型半導体記憶装置および半導体記憶装置
JP3304531B2 (ja) * 1993-08-24 2002-07-22 富士通株式会社 半導体記憶装置
JPH07130788A (ja) * 1993-09-09 1995-05-19 Mitsubishi Electric Corp 半導体集積回路装置
US5596740A (en) * 1995-01-26 1997-01-21 Cyrix Corporation Interleaved memory conflict resolution with accesses of variable bank widths and partial return of non-conflicting banks
US5619471A (en) * 1995-06-06 1997-04-08 Apple Computer, Inc. Memory controller for both interleaved and non-interleaved memory

Also Published As

Publication number Publication date
DE69717054T2 (de) 2003-11-13
KR100499295B1 (ko) 2006-04-21
EP0847058A3 (de) 1999-10-20
EP0847058B1 (de) 2002-11-13
KR19980063697A (ko) 1998-10-07
US5831925A (en) 1998-11-03
JPH10240617A (ja) 1998-09-11
EP0847058A2 (de) 1998-06-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition