DE69715472T2 - Herstellungsverfahren für einen integrierten schaltkreis und der damit hergetellte integrierte schaltkreis - Google Patents

Herstellungsverfahren für einen integrierten schaltkreis und der damit hergetellte integrierte schaltkreis

Info

Publication number
DE69715472T2
DE69715472T2 DE69715472T DE69715472T DE69715472T2 DE 69715472 T2 DE69715472 T2 DE 69715472T2 DE 69715472 T DE69715472 T DE 69715472T DE 69715472 T DE69715472 T DE 69715472T DE 69715472 T2 DE69715472 T2 DE 69715472T2
Authority
DE
Germany
Prior art keywords
integrated circuit
manufacturing
produced
circuit produced
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69715472T
Other languages
English (en)
Other versions
DE69715472D1 (de
Inventor
Tomasz Kowalski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Inside Technologies SA
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of DE69715472D1 publication Critical patent/DE69715472D1/de
Application granted granted Critical
Publication of DE69715472T2 publication Critical patent/DE69715472T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69715472T 1997-06-13 1997-06-13 Herstellungsverfahren für einen integrierten schaltkreis und der damit hergetellte integrierte schaltkreis Expired - Fee Related DE69715472T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB1997/000695 WO1998057373A1 (fr) 1997-06-13 1997-06-13 Procede de fabrication d'un circuit integre et circuit integre realise selon ce procede

Publications (2)

Publication Number Publication Date
DE69715472D1 DE69715472D1 (de) 2002-10-17
DE69715472T2 true DE69715472T2 (de) 2003-04-30

Family

ID=11004574

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69715472T Expired - Fee Related DE69715472T2 (de) 1997-06-13 1997-06-13 Herstellungsverfahren für einen integrierten schaltkreis und der damit hergetellte integrierte schaltkreis

Country Status (4)

Country Link
EP (1) EP1012881B1 (de)
AU (1) AU2974297A (de)
DE (1) DE69715472T2 (de)
WO (1) WO1998057373A1 (de)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005028905A1 (de) * 2005-06-22 2006-12-28 Infineon Technologies Ag Transistorbauelement
DE102006039877A1 (de) * 2006-08-25 2008-03-13 Infineon Technologies Ag Chip mit einer vertikalen Kontakt-Struktur
FR3059145A1 (fr) * 2016-11-22 2018-05-25 Stmicroelectronics (Rousset) Sas Procede de formation d'au moins une discontinuite electrique dans un circuit integre et circuit integre correspondant
FR3059144A1 (fr) * 2016-11-22 2018-05-25 Stmicroelectronics (Rousset) Sas Procede de formation d'au moins une discontinuite electrique dans une partie d'interconnexion d'un circuit integre sans ajout de materiau supplementaire, et circuit integre correspondant
US10049991B2 (en) 2016-11-22 2018-08-14 Stmicroelectronics (Rousset) Sas Method for forming at least one electrical discontinuity in an interconnection part of an integrated circuit, and corresponding integrated circuit

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1193758A1 (de) 2000-10-02 2002-04-03 STMicroelectronics S.r.l. Entschlüsselung erschwerende Kontakte
EP1202353A1 (de) * 2000-10-27 2002-05-02 STMicroelectronics S.r.l. Masken-programmiertes ROM und dessen Herstellungsverfahren
US6791191B2 (en) * 2001-01-24 2004-09-14 Hrl Laboratories, Llc Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations
US6740942B2 (en) 2001-06-15 2004-05-25 Hrl Laboratories, Llc. Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact
US6774413B2 (en) * 2001-06-15 2004-08-10 Hrl Laboratories, Llc Integrated circuit structure with programmable connector/isolator
JP4729303B2 (ja) * 2002-05-14 2011-07-20 エイチアールエル ラボラトリーズ，エルエルシー リバースエンジニアリングに対する防御を有する集積回路
DE10221657A1 (de) * 2002-05-15 2003-11-27 Infineon Technologies Ag Informationsmatrix
KR102379370B1 (ko) * 2014-12-23 2022-03-28 인텔 코포레이션 비아 차단 층
FR3069370B1 (fr) 2017-07-21 2021-10-22 St Microelectronics Rousset Circuit integre contenant une structure de leurre

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61147551A (ja) * 1984-12-21 1986-07-05 Nec Corp 半導体装置
US5452355A (en) * 1994-02-02 1995-09-19 Vlsi Technology, Inc. Tamper protection cell

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005028905A1 (de) * 2005-06-22 2006-12-28 Infineon Technologies Ag Transistorbauelement
DE102006039877A1 (de) * 2006-08-25 2008-03-13 Infineon Technologies Ag Chip mit einer vertikalen Kontakt-Struktur
DE102006039877B4 (de) * 2006-08-25 2011-03-31 Infineon Technologies Ag Chip mit einer vertikalen Dummy-Kontakt-Struktur
US7939946B2 (en) 2006-08-25 2011-05-10 Infineon Technologies Ag Chip with a vertical contact structure
FR3059145A1 (fr) * 2016-11-22 2018-05-25 Stmicroelectronics (Rousset) Sas Procede de formation d'au moins une discontinuite electrique dans un circuit integre et circuit integre correspondant
FR3059144A1 (fr) * 2016-11-22 2018-05-25 Stmicroelectronics (Rousset) Sas Procede de formation d'au moins une discontinuite electrique dans une partie d'interconnexion d'un circuit integre sans ajout de materiau supplementaire, et circuit integre correspondant
CN108091577A (zh) * 2016-11-22 2018-05-29 意法半导体(鲁塞)公司 在集成电路的互连部分中形成电中断的方法及集成电路
CN108091576A (zh) * 2016-11-22 2018-05-29 意法半导体(鲁塞)公司 在集成电路中形成至少一个电中断的方法及相应集成电路
US10049982B2 (en) 2016-11-22 2018-08-14 Stmicroelectronics (Rousset) Sas Method for forming at least one electrical discontinuity in an interconnection part of an integrated circuit without addition of additional material, and corresponding integrated circuit
US10049991B2 (en) 2016-11-22 2018-08-14 Stmicroelectronics (Rousset) Sas Method for forming at least one electrical discontinuity in an interconnection part of an integrated circuit, and corresponding integrated circuit
US10177101B2 (en) 2016-11-22 2019-01-08 Stmicroelectronics (Rousset) Sas Method for forming at least one electrical discontinuity in an integrated circuit, and corresponding integrated circuit
US10861802B2 (en) 2016-11-22 2020-12-08 Stmicroelectronics (Rousset) Sas Method for forming at least one electrical discontinuity in an integrated circuit, and corresponding integrated circuit

Also Published As

Publication number Publication date
EP1012881B1 (de) 2002-09-11
AU2974297A (en) 1998-12-30
DE69715472D1 (de) 2002-10-17
WO1998057373A1 (fr) 1998-12-17
EP1012881A1 (de) 2000-06-28

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: INSIDE TECHNOLOGIES, SAINT-CLEMENT-LES-PLACES, FR

8380 Miscellaneous part iii

Free format text: DER ANMELDER IST ZU AENDERN IN: INSIDE TECHNOLOGIES, SAINT-CLEMENT-LES-PLACES, FR

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee