DE69714244T2 - Schnelles laden von prüfvektoren für eine automatische testeinrichtung - Google Patents

Schnelles laden von prüfvektoren für eine automatische testeinrichtung

Info

Publication number
DE69714244T2
DE69714244T2 DE69714244T DE69714244T DE69714244T2 DE 69714244 T2 DE69714244 T2 DE 69714244T2 DE 69714244 T DE69714244 T DE 69714244T DE 69714244 T DE69714244 T DE 69714244T DE 69714244 T2 DE69714244 T2 DE 69714244T2
Authority
DE
Germany
Prior art keywords
vector
loading
vectors
quickly load
automatic test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69714244T
Other languages
English (en)
Other versions
DE69714244D1 (de
Inventor
M Proudfoot
A Reichert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Teradyne Inc
Original Assignee
Teradyne Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teradyne Inc filed Critical Teradyne Inc
Publication of DE69714244D1 publication Critical patent/DE69714244D1/de
Application granted granted Critical
Publication of DE69714244T2 publication Critical patent/DE69714244T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuits
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuits
    • G01R31/31903Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE69714244T 1996-05-22 1997-05-22 Schnelles laden von prüfvektoren für eine automatische testeinrichtung Expired - Fee Related DE69714244T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/653,949 US5737512A (en) 1996-05-22 1996-05-22 Fast vector loading for automatic test equipment
PCT/US1997/009050 WO1997044678A1 (en) 1996-05-22 1997-05-22 Fast vector loading for automatic test equipment

Publications (2)

Publication Number Publication Date
DE69714244D1 DE69714244D1 (de) 2002-08-29
DE69714244T2 true DE69714244T2 (de) 2003-02-27

Family

ID=24622919

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69714244T Expired - Fee Related DE69714244T2 (de) 1996-05-22 1997-05-22 Schnelles laden von prüfvektoren für eine automatische testeinrichtung

Country Status (6)

Country Link
US (1) US5737512A (de)
EP (1) EP0898715B1 (de)
JP (1) JP4311763B2 (de)
KR (1) KR100309658B1 (de)
DE (1) DE69714244T2 (de)
WO (1) WO1997044678A1 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5883906A (en) * 1997-08-15 1999-03-16 Advantest Corp. Pattern data compression and decompression for semiconductor test system
US6047293A (en) * 1997-09-16 2000-04-04 Teradyne, Inc. System for storing and searching named device parameter data in a test system for testing an integrated circuit
US5923098A (en) * 1997-10-03 1999-07-13 Micro Control Company Driver board having stored calibration data
JP2000046916A (ja) * 1998-07-30 2000-02-18 Ando Electric Co Ltd パタンデータ転送回路
US6181151B1 (en) * 1998-10-28 2001-01-30 Credence Systems Corporation Integrated circuit tester with disk-based data streaming
US6321352B1 (en) * 1998-10-28 2001-11-20 Credence Systems Corporation Integrated circuit tester having a disk drive per channel
US6286080B1 (en) * 1999-02-16 2001-09-04 International Business Machines Corporation Advanced read cache emulation
US6226765B1 (en) * 1999-02-26 2001-05-01 Advantest Corp. Event based test system data memory compression
US6718487B1 (en) * 2000-06-27 2004-04-06 Infineon Technologies North America Corp. Method for high speed testing with low speed semiconductor test equipment
US6507842B1 (en) 2000-07-10 2003-01-14 National Instruments Corporation System and method for importing and exporting test executive values from or to a database
US6560756B1 (en) * 2001-07-02 2003-05-06 Ltx Corporation Method and apparatus for distributed test pattern decompression
JP2005524852A (ja) * 2002-05-08 2005-08-18 エヌピーテスト, インコーポレイテッド 多目的メモリを有するテスタシステム
AU2003233536A1 (en) * 2002-05-08 2003-11-11 Nptest, Inc. Tester system having multiple instruction memories
US7404109B2 (en) * 2003-06-12 2008-07-22 Verigy (Singapore) Pte. Ltd. Systems and methods for adaptively compressing test data
EP1724599B1 (de) * 2005-05-20 2007-08-22 Agilent Technologies, Inc. Prüfvorrichtung mit Anpassung des Prüfparameters
TWI294153B (en) * 2006-02-16 2008-03-01 C Chang Edward Improved automatic test equipment (ate) and method of implementing the same
US7657812B2 (en) * 2007-03-21 2010-02-02 Advantest Corporation Test apparatus for updating a value of the bit position in result register by executing a result register update instruction with predetermined value to generate test pattern
US7716541B2 (en) * 2007-03-21 2010-05-11 Advantest Corporation Test apparatus and electronic device for generating test signal to a device under test
US7603604B2 (en) * 2007-04-09 2009-10-13 Advantest Corporation Test apparatus and electronic device
US9188627B2 (en) * 2011-11-08 2015-11-17 King Fahd University Of Petroleum And Minerals Digital integrated circuit testing and characterization system and method
US9910086B2 (en) 2012-01-17 2018-03-06 Allen Czamara Test IP-based A.T.E. instrument architecture

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4339819A (en) * 1980-06-17 1982-07-13 Zehntel, Inc. Programmable sequence generator for in-circuit digital testing
US4931723A (en) * 1985-12-18 1990-06-05 Schlumberger Technologies, Inc. Automatic test system having a "true tester-per-pin" architecture
CA1251575A (en) * 1985-12-18 1989-03-21 A. Keith Jeffrey Automatic test system having a "true tester-per-pin" architecture
US5265101A (en) * 1987-09-14 1993-11-23 Texas Instruments Incorporated Function array sequencing for VLSI test system
US4875210A (en) * 1988-01-06 1989-10-17 Teradyne, Inc. Automatic circuit tester control system
JPH01184700A (ja) * 1988-01-11 1989-07-24 Advantest Corp メモリ試験装置
JP3126127B2 (ja) * 1989-04-28 2001-01-22 アジレント・テクノロジー株式会社 試験データ圧縮方式
JP2584673B2 (ja) * 1989-06-09 1997-02-26 株式会社日立製作所 テストデータ変更回路を有する論理回路テスト装置
JPH0359741A (ja) * 1989-07-28 1991-03-14 Mitsubishi Electric Corp キャッシュメモリ
US5127011A (en) * 1990-01-12 1992-06-30 International Business Machines Corporation Per-pin integrated circuit test system having n-bit interface
US5446742A (en) * 1990-08-01 1995-08-29 Zilog, Inc. Techniques for developing integrated circuit test programs and their use in testing actual circuits
US5225772A (en) * 1990-09-05 1993-07-06 Schlumberger Technologies, Inc. Automatic test equipment system using pin slice architecture
US5321701A (en) * 1990-12-06 1994-06-14 Teradyne, Inc. Method and apparatus for a minimal memory in-circuit digital tester
DE4305442C2 (de) * 1993-02-23 1999-08-05 Hewlett Packard Gmbh Verfahren und Vorrichtung zum Erzeugen eines Testvektors
DE69326004T2 (de) * 1993-09-20 1999-11-25 Hewlett Packard Gmbh Testapparat mit grosser Kapazität
US5570383A (en) * 1994-08-15 1996-10-29 Teradyne, Inc. Timing hazard detector accelerator
US5657486A (en) * 1995-12-07 1997-08-12 Teradyne, Inc. Automatic test equipment with pipelined sequencer

Also Published As

Publication number Publication date
DE69714244D1 (de) 2002-08-29
US5737512A (en) 1998-04-07
JP4311763B2 (ja) 2009-08-12
EP0898715B1 (de) 2002-07-24
KR100309658B1 (ko) 2001-11-15
KR20000015866A (ko) 2000-03-15
WO1997044678A1 (en) 1997-11-27
EP0898715A1 (de) 1999-03-03
JP2000511284A (ja) 2000-08-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee