DE69533018T2 - Struktur und Leistungsabtastprüfung - Google Patents

Struktur und Leistungsabtastprüfung Download PDF

Info

Publication number
DE69533018T2
DE69533018T2 DE69533018T DE69533018T DE69533018T2 DE 69533018 T2 DE69533018 T2 DE 69533018T2 DE 69533018 T DE69533018 T DE 69533018T DE 69533018 T DE69533018 T DE 69533018T DE 69533018 T2 DE69533018 T2 DE 69533018T2
Authority
DE
Germany
Prior art keywords
signal
sample
clock
latch
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69533018T
Other languages
German (de)
English (en)
Other versions
DE69533018D1 (de
Inventor
Robert Bristol Warren
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Ltd Great Britain
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics Ltd Great Britain
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Ltd Great Britain, SGS Thomson Microelectronics Inc filed Critical STMicroelectronics Ltd Great Britain
Application granted granted Critical
Publication of DE69533018D1 publication Critical patent/DE69533018D1/de
Publication of DE69533018T2 publication Critical patent/DE69533018T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318577—AC testing, e.g. current testing, burn-in
    • G01R31/31858—Delay testing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Power Engineering (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE69533018T 1994-09-01 1995-08-22 Struktur und Leistungsabtastprüfung Expired - Fee Related DE69533018T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9417589A GB9417589D0 (en) 1994-09-01 1994-09-01 Scan test
GB9417589 1994-09-01

Publications (2)

Publication Number Publication Date
DE69533018D1 DE69533018D1 (de) 2004-06-17
DE69533018T2 true DE69533018T2 (de) 2005-03-24

Family

ID=10760669

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69533018T Expired - Fee Related DE69533018T2 (de) 1994-09-01 1995-08-22 Struktur und Leistungsabtastprüfung

Country Status (5)

Country Link
US (1) US5719877A (OSRAM)
EP (1) EP0702241B1 (OSRAM)
JP (1) JPH08179014A (OSRAM)
DE (1) DE69533018T2 (OSRAM)
GB (1) GB9417589D0 (OSRAM)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6032278A (en) * 1996-12-26 2000-02-29 Intel Corporation Method and apparatus for performing scan testing
JP3478033B2 (ja) * 1996-12-30 2003-12-10 ソニー株式会社 フリップフロップ回路
US6108807A (en) * 1997-07-28 2000-08-22 Lucent Technologies Inc. Apparatus and method for hybrid pin control of boundary scan applications
GB9810512D0 (en) 1998-05-15 1998-07-15 Sgs Thomson Microelectronics Detecting communication errors across a chip boundary
US7007213B2 (en) * 2001-02-15 2006-02-28 Syntest Technologies, Inc. Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
US8769359B2 (en) 2001-02-15 2014-07-01 Syntest Technologies, Inc. Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
US20030188243A1 (en) * 2002-03-29 2003-10-02 Rajan Krishna B. Method and apparatus for delay fault testing
EP1992955B1 (en) 2003-12-17 2012-07-25 STMicroelectronics (Research & Development) Limited TAP multiplexer
US7457998B1 (en) * 2005-01-07 2008-11-25 Cadence Design Systems, Inc. Scan register and methods of using the same
US7761748B2 (en) * 2005-06-09 2010-07-20 Sony Computer Entertainment Inc. Methods and apparatus for managing clock skew between clock domain boundaries
US9772376B1 (en) * 2016-04-29 2017-09-26 Texas Instruments Incorporated Increase data transfer throughput by enabling dynamic JTAG test mode entry and sharing of all JTAG pins

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6089120A (ja) * 1983-10-21 1985-05-20 Toshiba Corp フリツプフロツプ回路
US4697279A (en) * 1985-11-04 1987-09-29 Hughes Aircraft Company Test/master/slave triple latch flip-flop
US4742293A (en) * 1987-04-06 1988-05-03 Hughes Aircraft Company Pseudo-memory circuit for testing for stuck open faults
US5015875A (en) * 1989-12-01 1991-05-14 Motorola, Inc. Toggle-free scan flip-flop
US5130568A (en) * 1990-11-05 1992-07-14 Vertex Semiconductor Corporation Scannable latch system and method

Also Published As

Publication number Publication date
DE69533018D1 (de) 2004-06-17
US5719877A (en) 1998-02-17
EP0702241A3 (OSRAM) 1996-04-03
JPH08179014A (ja) 1996-07-12
EP0702241B1 (en) 2004-05-12
EP0702241A2 (en) 1996-03-20
GB9417589D0 (en) 1994-10-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee