DE69531282D1 - Isolierung durch aktive Transistoren mit geerdeten Torelektroden - Google Patents

Isolierung durch aktive Transistoren mit geerdeten Torelektroden

Info

Publication number
DE69531282D1
DE69531282D1 DE69531282T DE69531282T DE69531282D1 DE 69531282 D1 DE69531282 D1 DE 69531282D1 DE 69531282 T DE69531282 T DE 69531282T DE 69531282 T DE69531282 T DE 69531282T DE 69531282 D1 DE69531282 D1 DE 69531282D1
Authority
DE
Germany
Prior art keywords
earthed
isolation
gate electrodes
active transistors
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69531282T
Other languages
English (en)
Other versions
DE69531282T2 (de
Inventor
Tsiu Chiu Chan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Publication of DE69531282D1 publication Critical patent/DE69531282D1/de
Application granted granted Critical
Publication of DE69531282T2 publication Critical patent/DE69531282T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/765—Making of isolation regions between components by field effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
DE69531282T 1994-12-20 1995-11-28 Isolierung durch aktive Transistoren mit geerdeten Torelektroden Expired - Fee Related DE69531282T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US36097894A 1994-12-20 1994-12-20
US360978 1994-12-20

Publications (2)

Publication Number Publication Date
DE69531282D1 true DE69531282D1 (de) 2003-08-21
DE69531282T2 DE69531282T2 (de) 2004-05-27

Family

ID=23420157

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69531282T Expired - Fee Related DE69531282T2 (de) 1994-12-20 1995-11-28 Isolierung durch aktive Transistoren mit geerdeten Torelektroden

Country Status (4)

Country Link
US (2) US5849614A (de)
EP (1) EP0718881B1 (de)
JP (1) JPH08222624A (de)
DE (1) DE69531282T2 (de)

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JPH1117000A (ja) 1997-06-27 1999-01-22 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6426532B1 (en) * 1998-06-30 2002-07-30 Sharp Kabushiki Kaisha Semiconductor device and method of manufacture thereof
US6579781B1 (en) * 2000-07-19 2003-06-17 Advanced Micro Devices, Inc. Elimination of n+ contact implant from flash technologies by replacement with standard double-diffused and n+ implants
US6806123B2 (en) 2002-04-26 2004-10-19 Micron Technology, Inc. Methods of forming isolation regions associated with semiconductor constructions
JP2004024203A (ja) * 2002-06-28 2004-01-29 Canon Inc 飛行時間型二次イオン質量分析法によるｒｎａの分析方法
US6756619B2 (en) 2002-08-26 2004-06-29 Micron Technology, Inc. Semiconductor constructions
US7120046B1 (en) 2005-05-13 2006-10-10 Micron Technology, Inc. Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines
US7371627B1 (en) 2005-05-13 2008-05-13 Micron Technology, Inc. Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines
US7902598B2 (en) 2005-06-24 2011-03-08 Micron Technology, Inc. Two-sided surround access transistor for a 4.5F2 DRAM cell
US7888721B2 (en) 2005-07-06 2011-02-15 Micron Technology, Inc. Surround gate access transistors with grown ultra-thin bodies
US7768051B2 (en) 2005-07-25 2010-08-03 Micron Technology, Inc. DRAM including a vertical surround gate transistor
US7696567B2 (en) 2005-08-31 2010-04-13 Micron Technology, Inc Semiconductor memory device
KR100650867B1 (ko) * 2005-12-29 2006-11-28 동부일렉트로닉스 주식회사 협채널 금속 산화물 반도체 트랜지스터
KR100693812B1 (ko) * 2006-02-11 2007-03-12 삼성전자주식회사 반도체 장치 및 그 제조 방법, 반도체 장치의 센스 앰프 및그 형성 방법
US7932577B2 (en) * 2007-12-31 2011-04-26 Silicon Laboratories, Inc. Circuit device and method of forming a circuit device having a reduced peak current density
US20100127333A1 (en) * 2008-11-21 2010-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. novel layout architecture for performance enhancement
US8659072B2 (en) * 2010-09-24 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Series FinFET implementation schemes
US9240476B2 (en) 2013-03-13 2016-01-19 Cree, Inc. Field effect transistor devices with buried well regions and epitaxial layers
US9306061B2 (en) 2013-03-13 2016-04-05 Cree, Inc. Field effect transistor devices with protective regions
US9142668B2 (en) 2013-03-13 2015-09-22 Cree, Inc. Field effect transistor devices with buried well protection regions
US9012984B2 (en) 2013-03-13 2015-04-21 Cree, Inc. Field effect transistor devices with regrown p-layers
US9171911B2 (en) 2013-07-08 2015-10-27 Efficient Power Conversion Corporation Isolation structure in gallium nitride devices and integrated circuits
US9099335B2 (en) * 2013-07-24 2015-08-04 Marvell World Trade Ltd. Analog circuit with improved layout for mismatch optimization
US11862637B2 (en) 2019-06-19 2024-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Tie off device
KR102363387B1 (ko) * 2020-01-21 2022-02-15 금오공과대학교 산학협력단 불소 처리 그래핀을 이용한 2차원 구조 센서

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JPH023257A (ja) * 1988-06-20 1990-01-08 Fujitsu Ltd フィールドシールド構造を有する半導体装置およびその製造方法
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JPH0265254A (ja) * 1988-08-31 1990-03-05 Toshiba Corp 半導体装置
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JPH0770724B2 (ja) * 1988-12-08 1995-07-31 三菱電機株式会社 半導体装置
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JPH0951083A (ja) * 1995-08-10 1997-02-18 Mitsubishi Electric Corp ゲートアレイ型半導体集積回路装置及びその製造方法

Also Published As

Publication number Publication date
EP0718881B1 (de) 2003-07-16
EP0718881A2 (de) 1996-06-26
EP0718881A3 (de) 1996-10-16
DE69531282T2 (de) 2004-05-27
US5821600A (en) 1998-10-13
US5849614A (en) 1998-12-15
JPH08222624A (ja) 1996-08-30

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Legal Events

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8339 Ceased/non-payment of the annual fee