DE69528099D1 - Isolationsverfahren für aktive Zonen eines Halbleitersubstrates mit untiefen planarisierten Graben - Google Patents

Isolationsverfahren für aktive Zonen eines Halbleitersubstrates mit untiefen planarisierten Graben

Info

Publication number
DE69528099D1
DE69528099D1 DE69528099T DE69528099T DE69528099D1 DE 69528099 D1 DE69528099 D1 DE 69528099D1 DE 69528099 T DE69528099 T DE 69528099T DE 69528099 T DE69528099 T DE 69528099T DE 69528099 D1 DE69528099 D1 DE 69528099D1
Authority
DE
Germany
Prior art keywords
planarized
trenches
shallow
semiconductor substrate
isolation method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69528099T
Other languages
English (en)
Other versions
DE69528099T2 (de
Inventor
Maryse Paoli
Pierre Brouquet
Michel Haond
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Orange SA
Original Assignee
France Telecom SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by France Telecom SA filed Critical France Telecom SA
Publication of DE69528099D1 publication Critical patent/DE69528099D1/de
Application granted granted Critical
Publication of DE69528099T2 publication Critical patent/DE69528099T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
DE69528099T 1994-03-11 1995-03-10 Isolationsverfahren für aktive Zonen eines Halbleitersubstrates mit untiefen planarisierten Graben Expired - Lifetime DE69528099T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9402871A FR2717307B1 (fr) 1994-03-11 1994-03-11 Procede d'isolement de zones actives d'un substrat semi-conducteur par tranchees peu profondes quasi planes, et dispositif correspondant

Publications (2)

Publication Number Publication Date
DE69528099D1 true DE69528099D1 (de) 2002-10-17
DE69528099T2 DE69528099T2 (de) 2003-06-05

Family

ID=9460954

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69528099T Expired - Lifetime DE69528099T2 (de) 1994-03-11 1995-03-10 Isolationsverfahren für aktive Zonen eines Halbleitersubstrates mit untiefen planarisierten Graben

Country Status (5)

Country Link
US (1) US5604149A (de)
EP (1) EP0673062B1 (de)
JP (1) JPH0837232A (de)
DE (1) DE69528099T2 (de)
FR (1) FR2717307B1 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3202460B2 (ja) * 1993-12-21 2001-08-27 株式会社東芝 半導体装置およびその製造方法
US5677230A (en) * 1995-12-01 1997-10-14 Motorola Method of making wide bandgap semiconductor devices
US5863828A (en) * 1996-09-25 1999-01-26 National Semiconductor Corporation Trench planarization technique
US5834358A (en) * 1996-11-12 1998-11-10 Micron Technology, Inc. Isolation regions and methods of forming isolation regions
US7157385B2 (en) * 2003-09-05 2007-01-02 Micron Technology, Inc. Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry
US6177344B1 (en) 1998-11-25 2001-01-23 Applied Materials, Inc. BPSG reflow method to reduce thermal budget for next generation device including heating in a steam ambient
US6102042A (en) * 1998-12-22 2000-08-15 Respironics, Inc. Insufflation system, attachment and method
US6037238A (en) * 1999-01-04 2000-03-14 Vanguard International Semiconductor Corporation Process to reduce defect formation occurring during shallow trench isolation formation
US6319796B1 (en) 1999-08-18 2001-11-20 Vlsi Technology, Inc. Manufacture of an integrated circuit isolation structure
US6300219B1 (en) * 1999-08-30 2001-10-09 Micron Technology, Inc. Method of forming trench isolation regions
US6498061B2 (en) 2000-12-06 2002-12-24 International Business Machines Corporation Negative ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formation
US6734080B1 (en) * 2002-05-31 2004-05-11 Advanced Micro Devices, Inc. Semiconductor isolation material deposition system and method
US7125815B2 (en) * 2003-07-07 2006-10-24 Micron Technology, Inc. Methods of forming a phosphorous doped silicon dioxide comprising layer
US7053010B2 (en) * 2004-03-22 2006-05-30 Micron Technology, Inc. Methods of depositing silicon dioxide comprising layers in the fabrication of integrated circuitry, methods of forming trench isolation, and methods of forming arrays of memory cells
US7235459B2 (en) * 2004-08-31 2007-06-26 Micron Technology, Inc. Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry
US7217634B2 (en) * 2005-02-17 2007-05-15 Micron Technology, Inc. Methods of forming integrated circuitry
US20060186509A1 (en) * 2005-02-24 2006-08-24 Honeywell International, Inc. Shallow trench isolation structure with active edge isolation
US7510966B2 (en) * 2005-03-07 2009-03-31 Micron Technology, Inc. Electrically conductive line, method of forming an electrically conductive line, and method of reducing titanium silicide agglomeration in fabrication of titanium silicide over polysilicon transistor gate lines
US8012847B2 (en) 2005-04-01 2011-09-06 Micron Technology, Inc. Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry
US7694397B2 (en) * 2006-02-24 2010-04-13 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Method of manufacturing an acoustic mirror for piezoelectric resonator
KR100818711B1 (ko) * 2006-12-07 2008-04-01 주식회사 하이닉스반도체 반도체 소자의 소자분리막 형성방법
US8105956B2 (en) * 2009-10-20 2012-01-31 Micron Technology, Inc. Methods of forming silicon oxides and methods of forming interlevel dielectrics

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07120703B2 (ja) * 1987-01-27 1995-12-20 松下電器産業株式会社 半導体装置の製造方法
NL8701717A (nl) * 1987-07-21 1989-02-16 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een geplanariseerde opbouw.
US4954459A (en) * 1988-05-12 1990-09-04 Advanced Micro Devices, Inc. Method of planarization of topologies in integrated circuit structures
JPH01307242A (ja) * 1988-06-06 1989-12-12 Sanyo Electric Co Ltd 半導体装置の製造方法
US4952524A (en) * 1989-05-05 1990-08-28 At&T Bell Laboratories Semiconductor device manufacture including trench formation
EP0424608B1 (de) * 1989-10-25 1993-12-01 International Business Machines Corporation Verfahren zur Herstellung breiter mit Dielektrikum gefüllter Isolationsgraben für Halbleiteranordnungen
US5094972A (en) * 1990-06-14 1992-03-10 National Semiconductor Corp. Means of planarizing integrated circuits with fully recessed isolation dielectric
GB2256967B (en) * 1991-06-17 1995-03-29 Motorola Inc Method of depositing a pecvd teos oxide film
JPH05304219A (ja) * 1992-04-27 1993-11-16 Kawasaki Steel Corp 半導体装置における絶縁層の形成方法
US5459096A (en) * 1994-07-05 1995-10-17 Motorola Inc. Process for fabricating a semiconductor device using dual planarization layers

Also Published As

Publication number Publication date
US5604149A (en) 1997-02-18
FR2717307B1 (fr) 1996-07-19
EP0673062A1 (de) 1995-09-20
JPH0837232A (ja) 1996-02-06
EP0673062B1 (de) 2002-09-11
FR2717307A1 (fr) 1995-09-15
DE69528099T2 (de) 2003-06-05

Similar Documents

Publication Publication Date Title
DE69528099T2 (de) Isolationsverfahren für aktive Zonen eines Halbleitersubstrates mit untiefen planarisierten Graben
DE69534888D1 (de) Herstellungsverfahren für Halbleiterbauelement mit Graben
DE69737433D1 (de) Lückenfüllungs- und Planarisierungsverfahren für flache Grabenisolation
DE69529858D1 (de) Oberflächenbehandlung für Halbleitersubstrat
DE69535936D1 (de) Verfahren zum Herstellen einer Halbleitervorrichtung mit Graben
EP0506416A3 (en) Manufacturing method of soi substrate having monocrystal silicon layer on insulating film
SG85156A1 (en) Method of integrating substrate contact on soi wafers with sti process
FR2725074B1 (fr) Procede de fabrication d'une structure comportant une couche mince semi-conductrice sur un substrat
EP0660391A3 (de) Halbleiteranordnung mit einer Isolationszone mit einem Isolationsgraben und Verfahren zur Herstellung derselben.
DE59409300D1 (de) Verfahren zur Herstellung von einem Isolationsgraben in einem Substrat für Smart-Power-Technologien
DE69634711D1 (de) VBB-Referenz für spannungsgepümptes Substrat
DE69334324D1 (de) Herstellungsverfahren für Halbleitersubstrat
SG63797A1 (en) Method for shallow trench isolation
EP0684650A3 (de) SiGe-Dunnfilm-Halbleiteranordnung oder SiGe Schichtstruktur und Verfahren zur Herstellung.
DE69331817T2 (de) Herstellungsverfahren eines Halbleitersubstrat
TW328618B (en) A method for isolating an active region of an MOS semiconductor device using a planarized refill layer which is not substantially overpolished and an MOS device fabricated thereby
DE69132826D1 (de) Heizgerät für Halbleiterwafers oder Substrate
DE69431938T2 (de) Verfahren zur Herstellung einer Halbleiteranordnung mit Grabenstruktur für Element Isolationszonen
DE69628505D1 (de) Halbleitendes Substrat und dessen Herstellungsverfahren
AU6946598A (en) Method of forming a contact opening adjacent to an isolation trench in a semiconductor substrate
DE69513361D1 (de) Trägerbehälter für Substratscheiben
EP0962988A3 (de) SOI-Halbleiteranordnung und Verfahren zur Herstellung
EP0599318A3 (de) Verfahren zur Herstellung einer Halbleiteranordnung unter Verwendung einer Isolationsstruktur mit Gräben
GB9525678D0 (en) Method of growing compound semiconductor layer
TW332342B (en) Structure and fabrication method of split-gate flash memory

Legal Events

Date Code Title Description
8364 No opposition during term of opposition